\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection :
Flash Patch Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Flash Patch global enable
bits : 0 - 0 (1 bit)
KEY : FP_CTRL write-enable key
bits : 1 - 1 (1 bit)
NUM_CODE : Number of implemented code comparators bits [3:0]
bits : 4 - 7 (4 bit)
NUM_LIT : Number of literal comparators
bits : 8 - 11 (4 bit)
NUM_CODE_1 : Number of implemented code comparators bits [6:4]
bits : 12 - 14 (3 bit)
REV : Revision
bits : 28 - 31 (4 bit)
Flash Patch Comparator Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Breakpoint enable
bits : 0 - 0 (1 bit)
FPADDR : Flash Patch address
bits : 2 - 28 (27 bit)
FE : Flash Patch enable
bits : 31 - 31 (1 bit)
Flash Patch Comparator Register n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FP_COMP[%s]
reset_Mask : 0x0
BE : Breakpoint enable
bits : 0 - 0 (1 bit)
BPADDR : Breakpoint address
bits : 1 - 31 (31 bit)
Flash Patch Comparator Register n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Breakpoint enable
bits : 0 - 0 (1 bit)
FPADDR : Flash Patch address
bits : 2 - 28 (27 bit)
FE : Flash Patch enable
bits : 31 - 31 (1 bit)
Flash Patch Comparator Register n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FP_COMP[%s]
reset_Mask : 0x0
BE : Breakpoint enable
bits : 0 - 0 (1 bit)
BPADDR : Breakpoint address
bits : 1 - 31 (31 bit)
Flash Patch Remap Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REMAP : Remap address
bits : 5 - 28 (24 bit)
RMPSPT : Remap supported
bits : 29 - 29 (1 bit)
Flash Patch Comparator Register n
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Breakpoint enable
bits : 0 - 0 (1 bit)
FPADDR : Flash Patch address
bits : 2 - 28 (27 bit)
FE : Flash Patch enable
bits : 31 - 31 (1 bit)
Flash Patch Comparator Register n
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FP_COMP[%s]
reset_Mask : 0x0
BE : Breakpoint enable
bits : 0 - 0 (1 bit)
BPADDR : Breakpoint address
bits : 1 - 31 (31 bit)
Flash Patch Comparator Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Breakpoint enable
bits : 0 - 0 (1 bit)
FPADDR : Flash Patch address
bits : 2 - 28 (27 bit)
FE : Flash Patch enable
bits : 31 - 31 (1 bit)
Flash Patch Comparator Register n
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : FP_COMP[%s]
reset_Mask : 0x0
BE : Breakpoint enable
bits : 0 - 0 (1 bit)
BPADDR : Breakpoint address
bits : 1 - 31 (31 bit)
FPB Software Lock Access Register
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Lock access control
bits : 0 - 31 (32 bit)
Enumeration: KEYSelect
0xC5ACCE55 : UNLOCK
Unlock key value
End of enumeration elements list.
FPB Software Lock Status Register
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLI : Software Lock implemented
bits : 0 - 0 (1 bit)
SLK : Software Lock status
bits : 1 - 1 (1 bit)
nTT : Not thirty-two bit
bits : 2 - 2 (1 bit)
FPB Device Architecture Register
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ARCHPART : Architecture Part
bits : 0 - 11 (12 bit)
ARCHVER : Architecture Version
bits : 12 - 15 (4 bit)
REVISION : Revision
bits : 16 - 19 (4 bit)
PRESENT : DEVARCH Present
bits : 20 - 20 (1 bit)
ARCHITECT : Architect
bits : 21 - 31 (11 bit)
FPB Device Type Register
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Major type
bits : 0 - 3 (4 bit)
SUB : Sub-type
bits : 4 - 7 (4 bit)
FP Peripheral Identification Register 4
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DES_2 : JEP106 continuation code
bits : 0 - 3 (4 bit)
SIZE : 4KB count
bits : 4 - 7 (4 bit)
FP Peripheral Identification Register 5
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FP Peripheral Identification Register 6
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FP Peripheral Identification Register 7
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FP Peripheral Identification Register 0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PART_0 : Part number bits[7:0]
bits : 0 - 7 (8 bit)
FP Peripheral Identification Register 1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PART_1 : Part number bits[11:8]
bits : 0 - 3 (4 bit)
DES_0 : JEP106 identification code bits [3:0]
bits : 4 - 7 (4 bit)
FP Peripheral Identification Register 2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DES_1 : JEP106 identification code bits[6:4]
bits : 0 - 2 (3 bit)
JEDEC : JEDEC assignee value is used
bits : 3 - 3 (1 bit)
REVISION : Component revision
bits : 4 - 7 (4 bit)
FP Peripheral Identification Register 3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMOD : Customer Modified
bits : 0 - 3 (4 bit)
REVAND : RevAnd
bits : 4 - 7 (4 bit)
FP Component Identification Register 0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRMBL_0 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)
FP Component Identification Register 1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRMBL_1 : CoreSight component identification preamble
bits : 0 - 3 (4 bit)
CLASS : CoreSight component class
bits : 4 - 7 (4 bit)
FP Component Identification Register 2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRMBL_2 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)
FP Component Identification Register 3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRMBL_3 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)
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