\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
Peripheral Clock Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Generic Clock Generator Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Generic Clock Generator Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Generic Clock Generator Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Generic Clock Generator Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Generic Clock Generator Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Generic Clock Generator Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Generic Clock Generator Control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Generic Clock Generator Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Synchronization Busy
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchroniation Busy bit
bits : 0 - 0 (1 bit)
access : read-only
GENCTRL0 : Generic Clock Generator Control 0 Synchronization Busy bits
bits : 2 - 2 (1 bit)
access : read-only
Enumeration: GENCTRL0Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
GENCTRL1 : Generic Clock Generator Control 1 Synchronization Busy bits
bits : 3 - 3 (1 bit)
access : read-only
Enumeration: GENCTRL1Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
GENCTRL2 : Generic Clock Generator Control 2 Synchronization Busy bits
bits : 4 - 4 (1 bit)
access : read-only
Enumeration: GENCTRL2Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
GENCTRL3 : Generic Clock Generator Control 3 Synchronization Busy bits
bits : 5 - 5 (1 bit)
access : read-only
Enumeration: GENCTRL3Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
GENCTRL4 : Generic Clock Generator Control 4 Synchronization Busy bits
bits : 6 - 6 (1 bit)
access : read-only
Enumeration: GENCTRL4Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
GENCTRL5 : Generic Clock Generator Control 5 Synchronization Busy bits
bits : 7 - 7 (1 bit)
access : read-only
Enumeration: GENCTRL5Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
GENCTRL6 : Generic Clock Generator Control 6 Synchronization Busy bits
bits : 8 - 8 (1 bit)
access : read-only
Enumeration: GENCTRL6Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
GENCTRL7 : Generic Clock Generator Control 7 Synchronization Busy bits
bits : 9 - 9 (1 bit)
access : read-only
Enumeration: GENCTRL7Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
GENCTRL8 : Generic Clock Generator Control 8 Synchronization Busy bits
bits : 10 - 10 (1 bit)
access : read-only
Enumeration: GENCTRL8Select
0x1 : GCLK0
Generic clock generator 0
0x2 : GCLK1
Generic clock generator 1
0x4 : GCLK2
Generic clock generator 2
0x8 : GCLK3
Generic clock generator 3
0x10 : GCLK4
Generic clock generator 4
0x20 : GCLK5
Generic clock generator 5
0x40 : GCLK6
Generic clock generator 6
0x80 : GCLK7
Generic clock generator 7
0x100 : GCLK8
Generic clock generator 8
End of enumeration elements list.
Generic Clock Generator Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC : Source Select
bits : 0 - 3 (4 bit)
Enumeration: SRCSelect
0x0 : XOSC
XOSC oscillator output
0x1 : GCLKIN
Generator input pad
0x2 : GCLKGEN1
Generic clock generator 1 output
0x3 : OSCULP32K
OSCULP32K oscillator output
0x4 : OSC32K
OSC32K oscillator output
0x5 : XOSC32K
XOSC32K oscillator output
0x6 : OSC16M
OSC16M oscillator output
0x7 : DFLL48M
DFLL48M output
0x8 : DPLL96M
DPLL96M output
End of enumeration elements list.
GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)
IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)
OOV : Output Off Value
bits : 10 - 10 (1 bit)
OE : Output Enable
bits : 11 - 11 (1 bit)
DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)
RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)
DIV : Division Factor
bits : 16 - 31 (16 bit)
Peripheral Clock Control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
Peripheral Clock Control
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)
Enumeration: GENSelect
0x0 : GCLK0
Generic clock generator 0
0x1 : GCLK1
Generic clock generator 1
0x2 : GCLK2
Generic clock generator 2
0x3 : GCLK3
Generic clock generator 3
0x4 : GCLK4
Generic clock generator 4
0x5 : GCLK5
Generic clock generator 5
0x6 : GCLK6
Generic clock generator 6
0x7 : GCLK7
Generic clock generator 7
0x8 : GCLK8
Generic clock generator 8
End of enumeration elements list.
CHEN : Channel Enable
bits : 6 - 6 (1 bit)
WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)
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