\n

GCLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection :

Registers

CTRLA

PCHCTRL32

PCHCTRL33

PCHCTRL34

PCHCTRL35

GENCTRL0

GENCTRL1

GENCTRL2

GENCTRL3

GENCTRL4

GENCTRL5

GENCTRL6

GENCTRL7

SYNCBUSY

GENCTRL8

PCHCTRL0

PCHCTRL1

PCHCTRL2

PCHCTRL3

PCHCTRL4

PCHCTRL5

PCHCTRL6

PCHCTRL7

PCHCTRL8

PCHCTRL9

PCHCTRL10

PCHCTRL11

PCHCTRL12

PCHCTRL13

PCHCTRL14

PCHCTRL15

PCHCTRL16

PCHCTRL17

PCHCTRL18

PCHCTRL19

PCHCTRL20

PCHCTRL21

PCHCTRL22

PCHCTRL23

PCHCTRL24

PCHCTRL25

PCHCTRL26

PCHCTRL27

PCHCTRL28

PCHCTRL29

PCHCTRL30

PCHCTRL31


CTRLA

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST

SWRST : Software Reset
bits : 0 - 0 (1 bit)


PCHCTRL32

Peripheral Clock Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL32 PCHCTRL32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL33

Peripheral Clock Control
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL33 PCHCTRL33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL34

Peripheral Clock Control
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL34 PCHCTRL34 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL35

Peripheral Clock Control
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL35 PCHCTRL35 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


GENCTRL0

Generic Clock Generator Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL0 GENCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


GENCTRL1

Generic Clock Generator Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL1 GENCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


GENCTRL2

Generic Clock Generator Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL2 GENCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


GENCTRL3

Generic Clock Generator Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL3 GENCTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


GENCTRL4

Generic Clock Generator Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL4 GENCTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


GENCTRL5

Generic Clock Generator Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL5 GENCTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


GENCTRL6

Generic Clock Generator Control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL6 GENCTRL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


GENCTRL7

Generic Clock Generator Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL7 GENCTRL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


SYNCBUSY

Synchronization Busy
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST GENCTRL0 GENCTRL1 GENCTRL2 GENCTRL3 GENCTRL4 GENCTRL5 GENCTRL6 GENCTRL7 GENCTRL8

SWRST : Software Reset Synchroniation Busy bit
bits : 0 - 0 (1 bit)
access : read-only

GENCTRL0 : Generic Clock Generator Control 0 Synchronization Busy bits
bits : 2 - 2 (1 bit)
access : read-only

Enumeration: GENCTRL0Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL1 : Generic Clock Generator Control 1 Synchronization Busy bits
bits : 3 - 3 (1 bit)
access : read-only

Enumeration: GENCTRL1Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL2 : Generic Clock Generator Control 2 Synchronization Busy bits
bits : 4 - 4 (1 bit)
access : read-only

Enumeration: GENCTRL2Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL3 : Generic Clock Generator Control 3 Synchronization Busy bits
bits : 5 - 5 (1 bit)
access : read-only

Enumeration: GENCTRL3Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL4 : Generic Clock Generator Control 4 Synchronization Busy bits
bits : 6 - 6 (1 bit)
access : read-only

Enumeration: GENCTRL4Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL5 : Generic Clock Generator Control 5 Synchronization Busy bits
bits : 7 - 7 (1 bit)
access : read-only

Enumeration: GENCTRL5Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL6 : Generic Clock Generator Control 6 Synchronization Busy bits
bits : 8 - 8 (1 bit)
access : read-only

Enumeration: GENCTRL6Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL7 : Generic Clock Generator Control 7 Synchronization Busy bits
bits : 9 - 9 (1 bit)
access : read-only

Enumeration: GENCTRL7Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.

GENCTRL8 : Generic Clock Generator Control 8 Synchronization Busy bits
bits : 10 - 10 (1 bit)
access : read-only

Enumeration: GENCTRL8Select

0x1 : GCLK0

Generic clock generator 0

0x2 : GCLK1

Generic clock generator 1

0x4 : GCLK2

Generic clock generator 2

0x8 : GCLK3

Generic clock generator 3

0x10 : GCLK4

Generic clock generator 4

0x20 : GCLK5

Generic clock generator 5

0x40 : GCLK6

Generic clock generator 6

0x80 : GCLK7

Generic clock generator 7

0x100 : GCLK8

Generic clock generator 8

End of enumeration elements list.


GENCTRL8

Generic Clock Generator Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GENCTRL8 GENCTRL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC GENEN IDC OOV OE DIVSEL RUNSTDBY DIV

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0x0 : XOSC

XOSC oscillator output

0x1 : GCLKIN

Generator input pad

0x2 : GCLKGEN1

Generic clock generator 1 output

0x3 : OSCULP32K

OSCULP32K oscillator output

0x4 : OSC32K

OSC32K oscillator output

0x5 : XOSC32K

XOSC32K oscillator output

0x6 : OSC16M

OSC16M oscillator output

0x7 : DFLL48M

DFLL48M output

0x8 : DPLL96M

DPLL96M output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)


PCHCTRL0

Peripheral Clock Control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL0 PCHCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL1

Peripheral Clock Control
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL1 PCHCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL2

Peripheral Clock Control
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL2 PCHCTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL3

Peripheral Clock Control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL3 PCHCTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL4

Peripheral Clock Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL4 PCHCTRL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL5

Peripheral Clock Control
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL5 PCHCTRL5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL6

Peripheral Clock Control
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL6 PCHCTRL6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL7

Peripheral Clock Control
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL7 PCHCTRL7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL8

Peripheral Clock Control
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL8 PCHCTRL8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL9

Peripheral Clock Control
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL9 PCHCTRL9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL10

Peripheral Clock Control
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL10 PCHCTRL10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL11

Peripheral Clock Control
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL11 PCHCTRL11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL12

Peripheral Clock Control
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL12 PCHCTRL12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL13

Peripheral Clock Control
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL13 PCHCTRL13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL14

Peripheral Clock Control
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL14 PCHCTRL14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL15

Peripheral Clock Control
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL15 PCHCTRL15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL16

Peripheral Clock Control
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL16 PCHCTRL16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL17

Peripheral Clock Control
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL17 PCHCTRL17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL18

Peripheral Clock Control
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL18 PCHCTRL18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL19

Peripheral Clock Control
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL19 PCHCTRL19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL20

Peripheral Clock Control
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL20 PCHCTRL20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL21

Peripheral Clock Control
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL21 PCHCTRL21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL22

Peripheral Clock Control
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL22 PCHCTRL22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL23

Peripheral Clock Control
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL23 PCHCTRL23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL24

Peripheral Clock Control
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL24 PCHCTRL24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL25

Peripheral Clock Control
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL25 PCHCTRL25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL26

Peripheral Clock Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL26 PCHCTRL26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL27

Peripheral Clock Control
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL27 PCHCTRL27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL28

Peripheral Clock Control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL28 PCHCTRL28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL29

Peripheral Clock Control
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL29 PCHCTRL29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL30

Peripheral Clock Control
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL30 PCHCTRL30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)


PCHCTRL31

Peripheral Clock Control
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCHCTRL31 PCHCTRL31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GEN CHEN WRTLOCK

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)



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