\n
address_offset : 0x0 Bytes (0x0)
size : 0x31C byte (0x0)
mem_usage : registers
protection :
Interrupt Set Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt set enable bits
bits : 0 - 25 (26 bit)
Interrupt Set Pending Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt set-pending bits
bits : 0 - 25 (26 bit)
Interrupt Clear Pending Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Interrupt clear-pending bits
bits : 0 - 25 (26 bit)
Interrupt Priority Register n
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)
PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)
PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)
PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)
Interrupt Priority Register n
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)
PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)
PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)
PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)
Interrupt Priority Register n
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)
PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)
PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)
PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)
Interrupt Priority Register n
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)
PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)
PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)
PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)
Interrupt Priority Register n
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)
PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)
PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)
PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)
Interrupt Priority Register n
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)
PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)
PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)
PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)
Interrupt Priority Register n
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)
PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)
PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)
PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)
Interrupt Clear Enable Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Interrupt clear-enable bits
bits : 0 - 25 (26 bit)
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