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NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x31C byte (0x0)
mem_usage : registers
protection :

Registers

ISER

ISPR

ICPR

IPR0

IPR1

IPR2

IPR3

IPR4

IPR5

IPR6

ICER


ISER

Interrupt Set Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISER ISER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set enable bits
bits : 0 - 25 (26 bit)


ISPR

Interrupt Set Pending Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPR ISPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits
bits : 0 - 25 (26 bit)


ICPR

Interrupt Clear Pending Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICPR ICPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt clear-pending bits
bits : 0 - 25 (26 bit)


IPR0

Interrupt Priority Register n
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR0 IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3

PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)

PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)

PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)

PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)


IPR1

Interrupt Priority Register n
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR1 IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3

PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)

PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)

PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)

PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)


IPR2

Interrupt Priority Register n
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR2 IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3

PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)

PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)

PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)

PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)


IPR3

Interrupt Priority Register n
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR3 IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3

PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)

PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)

PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)

PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)


IPR4

Interrupt Priority Register n
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR4 IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3

PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)

PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)

PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)

PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)


IPR5

Interrupt Priority Register n
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR5 IPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3

PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)

PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)

PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)

PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)


IPR6

Interrupt Priority Register n
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPR6 IPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI0 PRI1 PRI2 PRI3

PRI0 : Priority of interrupt n
bits : 0 - 1 (2 bit)

PRI1 : Priority of interrupt n
bits : 8 - 9 (2 bit)

PRI2 : Priority of interrupt n
bits : 16 - 17 (2 bit)

PRI3 : Priority of interrupt n
bits : 24 - 25 (2 bit)


ICER

Interrupt Clear Enable Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICER ICER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits
bits : 0 - 25 (26 bit)



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