Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xD34 byte (0x0)
mem_usage : registers
protection :
CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Minor revision number
bits : 0 - 3 (4 bit)
PARTNO : Processor Part Number, 0xC60=Cortex-M0+
bits : 4 - 15 (12 bit)
ARCHITECTURE : Processor Architecture, 0xC=ARMv6-M
bits : 16 - 19 (4 bit)
VARIANT : Major revision number
bits : 20 - 23 (4 bit)
IMPLEMENTER : Implementer code, ARM=0x41
bits : 24 - 31 (8 bit)
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Debug: Exception number of currently executing exception, or 0 if thread mode
bits : 0 - 8 (9 bit)
VECTPENDING : Exception number of the highest priority pending enabled exception
bits : 12 - 20 (9 bit)
ISRPENDING : Debug: NVIC interrupt pending
bits : 22 - 22 (1 bit)
ISRPREEMPT : Debug: Pending exception serviced on exit from debug halt
bits : 23 - 23 (1 bit)
PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 25 (1 bit)
Enumeration: PENDSTCLRSelect
0 : VALUE_0
No effect
1 : VALUE_1
Removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick exception set-pending bit
bits : 26 - 26 (1 bit)
Enumeration: PENDSTSETSelect
0 : VALUE_0
Write: no effect read: SysTick exception is not pending
1 : VALUE_1
Write: changes SysTick exception state to pending read: SysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV clear-pending bit
bits : 27 - 27 (1 bit)
Enumeration: PENDSVCLRSelect
0 : VALUE_0
No effect
1 : VALUE_1
Removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV set-pending bit
bits : 28 - 28 (1 bit)
Enumeration: PENDSVSETSelect
0 : VALUE_0
Write: no effect read: PendSV exception is not pending
1 : VALUE_1
Write: changes PendSV exception state to pending read: PendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI set-pending bit
bits : 31 - 31 (1 bit)
Enumeration: NMIPENDSETSelect
0 : VALUE_0
Write: no effect read: NMI exception is not pending
1 : VALUE_1
Write: changes NMI exception state to pending read: NMI exception is pending
End of enumeration elements list.
Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector table base offset
bits : 7 - 31 (25 bit)
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Debug: Clear state information
bits : 1 - 1 (1 bit)
SYSRESETREQ : System Reset Request
bits : 2 - 2 (1 bit)
Enumeration: SYSRESETREQSelect
0 : VALUE_0
No system reset request
1 : VALUE_1
Asserts a signal to the outer system that requests a reset
End of enumeration elements list.
ENDIANNESS : Data Endianness, 0=little, 1=big
bits : 15 - 15 (1 bit)
Enumeration: ENDIANNESSSelect
0 : VALUE_0
Little-endian
1 : VALUE_1
Big-endian
End of enumeration elements list.
VECTKEY : Register key (0x05FA)
bits : 16 - 31 (16 bit)
System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep-On-Exit when exiting Handler mode
bits : 1 - 1 (1 bit)
Enumeration: SLEEPONEXITSelect
0 : VALUE_0
O not sleep when returning to Thread mode
1 : VALUE_1
Enter sleep, or deep sleep, on return from an ISR
End of enumeration elements list.
SLEEPDEEP : Uses Deep Sleep as low power mode
bits : 2 - 2 (1 bit)
Enumeration: SLEEPDEEPSelect
0 : VALUE_0
Sleep
1 : VALUE_1
Deep sleep
End of enumeration elements list.
SEVONPEND : Send Event on Pending bit
bits : 4 - 4 (1 bit)
Enumeration: SEVONPENDSelect
0 : VALUE_0
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1 : VALUE_1
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
End of enumeration elements list.
Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UNALIGN_TRP : Unaligned accesses generates a Hard Fault
bits : 3 - 3 (1 bit)
Enumeration: UNALIGN_TRPSelect
0 : VALUE_0
Do not trap unaligned halfword and word accesses
1 : VALUE_1
Trap unaligned halfword and word accesses
End of enumeration elements list.
STKALIGN : Stack 8-byte aligned on exception entry
bits : 9 - 9 (1 bit)
Enumeration: STKALIGNSelect
0 : VALUE_0
4-byte aligned
1 : VALUE_1
8-byte aligned
End of enumeration elements list.
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of system handler 11, SVCall
bits : 24 - 31 (8 bit)
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of system handler 14, PendSV
bits : 16 - 23 (8 bit)
PRI_15 : Priority of system handler 15, SysTick exception
bits : 24 - 31 (8 bit)
System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SVCALLPENDED :
bits : 15 - 15 (1 bit)
Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED : Halt request debug event active
bits : 0 - 0 (1 bit)
BKPT : Breakpoint debug event
bits : 1 - 1 (1 bit)
DWTTRAP : DWT debug event
bits : 2 - 2 (1 bit)
VCATCH : Vector catch debug event
bits : 3 - 3 (1 bit)
EXTERNAL : EDBGRQ debug event
bits : 4 - 4 (1 bit)
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