\n

DMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x360 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

CHCTRLA

SWTRIGCTRL

CHCTRLA12

CHCTRLB12

CHPRILVL12

CHEVCTRL12

CHINTENCLR12

CHINTENSET12

CHINTFLAG12

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS12

CHCTRLA13

CHCTRLB13

CHPRILVL13

CHEVCTRL13

CHINTENCLR13

CHINTENSET13

CHINTFLAG13

CHSTATUS13

CHCTRLA14

CHCTRLB14

CHPRILVL14

CHEVCTRL14

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR14

CHINTENSET14

CHINTFLAG14

CHSTATUS14

CHCTRLA15

CHCTRLB15

CHPRILVL15

CHEVCTRL15

CHINTENCLR15

CHINTENSET15

CHINTFLAG15

CHSTATUS15

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

PRICTRL0

CHCTRLA16

CHCTRLB16

CHPRILVL16

CHEVCTRL16

CHINTENCLR16

CHINTENSET16

CHINTFLAG16

CHSTATUS16

CHCTRLA17

CHCTRLB17

CHPRILVL17

CHEVCTRL17

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR17

CHINTENSET17

CHINTFLAG17

CHSTATUS17

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHCTRLA18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHCTRLB18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHPRILVL18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHEVCTRL18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHINTENCLR18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHINTENSET18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHINTFLAG18

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS18

CHCTRLA19

CHCTRLB19

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHPRILVL19

CHEVCTRL19

CHINTENCLR19

CHINTENSET19

CHINTFLAG19

CHSTATUS19

CHCTRLA20

CHCTRLB20

CHPRILVL20

CHEVCTRL20

CHINTENCLR20

CHINTENSET20

CHINTFLAG20

CHSTATUS20

CHCTRLA21

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHCTRLB21

CHPRILVL21

CHEVCTRL21

CHINTENCLR21

CHINTENSET21

CHINTFLAG21

CHSTATUS21

CHCTRLA22

CHCTRLB22

CHPRILVL22

CHEVCTRL22

CHINTENCLR22

CHINTENSET22

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTFLAG22

CHSTATUS22

CHCTRLA23

CHCTRLB23

CHPRILVL23

CHEVCTRL23

CHINTENCLR23

CHINTENSET23

CHINTFLAG23

CHSTATUS23

CHCTRLA24

CHCTRLB24

CHPRILVL24

CHEVCTRL24

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR24

CHINTENSET24

CHINTFLAG24

CHSTATUS24

CHCTRLA25

CHCTRLB25

CHPRILVL25

CHEVCTRL25

CHINTENCLR25

CHINTENSET25

CHINTFLAG25

CHSTATUS25

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHCTRLA26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHCTRLB26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHPRILVL26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHEVCTRL26

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHINTENCLR26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHINTENSET26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHINTFLAG26

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS26

CHCTRLA27

CHCTRLB27

CHPRILVL27

CHEVCTRL27

CHINTENCLR27

CHINTENSET27

CHINTFLAG27

CHSTATUS27

CRCCTRL

INTPEND

CHCTRLA28

CHCTRLB28

CHPRILVL28

CHEVCTRL28

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR28

CHINTENSET28

CHINTFLAG28

CHSTATUS28

CHCTRLA29

CHCTRLB29

CHPRILVL29

CHEVCTRL29

CHINTENCLR29

CHINTENSET29

CHINTFLAG29

CHSTATUS29

CHCTRLA30

CHCTRLB30

CHPRILVL30

CHEVCTRL30

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR30

CHINTENSET30

CHINTFLAG30

CHSTATUS30

CHCTRLA31

CHCTRLB31

CHPRILVL31

CHEVCTRL31

CHINTENCLR31

CHINTENSET31

CHINTFLAG31

CHSTATUS31

INTSTATUS

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

BUSYCH

PENDCH

ACTIVE

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

BASEADDR

WRBADDR

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CRCDATAIN

CHCTRLB

CHANNEL[0]-CHCTRLA

CHCTRLA0

CHANNEL[0]-CHCTRLB

CHCTRLB0

CHANNEL[0]-CHPRILVL

CHPRILVL0

CHANNEL[0]-CHEVCTRL

CHEVCTRL0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL[0]-CHINTENCLR

CHINTENCLR0

CHANNEL[0]-CHINTENSET

CHINTENSET0

CHANNEL[0]-CHINTFLAG

CHINTFLAG0

CHANNEL[0]-CHSTATUS

CHSTATUS0

CHPRILVL

CHCTRLA1

CHCTRLB1

CHPRILVL1

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHEVCTRL1

CHINTENCLR1

CHINTENSET1

CHINTFLAG1

CHSTATUS1

CHEVCTRL

CHCTRLA2

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHCTRLB2

CHPRILVL2

CHEVCTRL2

CHINTENCLR2

CHINTENSET2

CHINTFLAG2

CHSTATUS2

CHCTRLA3

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHCTRLB3

CHPRILVL3

CHEVCTRL3

CHINTENCLR3

CHINTENSET3

CHINTFLAG3

CHSTATUS3

CRCCHKSUM

CHCTRLA4

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHCTRLB4

CHPRILVL4

CHEVCTRL4

CHINTENCLR4

CHINTENSET4

CHINTFLAG4

CHSTATUS4

CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHCTRLA5

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHCTRLB5

CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHPRILVL5

CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHEVCTRL5

CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHINTENCLR5

CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHINTENSET5

CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHINTFLAG5

CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS5

CHCTRLA6

CHCTRLB6

CHPRILVL6

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHEVCTRL6

CHINTENCLR6

CHINTENSET6

CHINTFLAG6

CHSTATUS6

CHCTRLA7

CHCTRLB7

CHPRILVL7

CHEVCTRL7

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENCLR7

CHINTENSET7

CHINTFLAG7

CHSTATUS7

CRCSTATUS

CHINTENCLR

CHCTRLA8

CHCTRLB8

CHPRILVL8

CHEVCTRL8

CHINTENCLR8

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENSET8

CHINTFLAG8

CHSTATUS8

DBGCTRL

CHINTENSET

CHCTRLA9

CHCTRLB9

CHPRILVL9

CHEVCTRL9

CHINTENCLR9

CHINTENSET9

CHINTFLAG9

CHSTATUS9

CHINTFLAG

CHCTRLA10

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHCTRLB10

CHPRILVL10

CHEVCTRL10

CHINTENCLR10

CHINTENSET10

CHINTFLAG10

CHSTATUS10

CHSTATUS

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHCTRLA11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHCTRLB11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHPRILVL11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHEVCTRL11

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHINTENCLR11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHINTENSET11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHINTFLAG11

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHSTATUS11


CTRL

Control
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST DMAENABLE LVLEN0 LVLEN1 LVLEN2 LVLEN3

SWRST : Software Reset
bits : 0 - 0 (1 bit)

DMAENABLE : DMA Enable
bits : 1 - 1 (1 bit)

LVLEN0 : Priority Level 0 Enable
bits : 8 - 8 (1 bit)

LVLEN1 : Priority Level 1 Enable
bits : 9 - 9 (1 bit)

LVLEN2 : Priority Level 2 Enable
bits : 10 - 10 (1 bit)

LVLEN3 : Priority Level 3 Enable
bits : 11 - 11 (1 bit)


CHCTRLA

Channel n Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


SWTRIGCTRL

Software Trigger Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWTRIGCTRL SWTRIGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRIG0 SWTRIG1 SWTRIG2 SWTRIG3 SWTRIG4 SWTRIG5 SWTRIG6 SWTRIG7 SWTRIG8 SWTRIG9 SWTRIG10 SWTRIG11 SWTRIG12 SWTRIG13 SWTRIG14 SWTRIG15 SWTRIG16 SWTRIG17 SWTRIG18 SWTRIG19 SWTRIG20 SWTRIG21 SWTRIG22 SWTRIG23 SWTRIG24 SWTRIG25 SWTRIG26 SWTRIG27 SWTRIG28 SWTRIG29 SWTRIG30 SWTRIG31

SWTRIG0 : Channel 0 Software Trigger
bits : 0 - 0 (1 bit)

SWTRIG1 : Channel 1 Software Trigger
bits : 1 - 1 (1 bit)

SWTRIG2 : Channel 2 Software Trigger
bits : 2 - 2 (1 bit)

SWTRIG3 : Channel 3 Software Trigger
bits : 3 - 3 (1 bit)

SWTRIG4 : Channel 4 Software Trigger
bits : 4 - 4 (1 bit)

SWTRIG5 : Channel 5 Software Trigger
bits : 5 - 5 (1 bit)

SWTRIG6 : Channel 6 Software Trigger
bits : 6 - 6 (1 bit)

SWTRIG7 : Channel 7 Software Trigger
bits : 7 - 7 (1 bit)

SWTRIG8 : Channel 8 Software Trigger
bits : 8 - 8 (1 bit)

SWTRIG9 : Channel 9 Software Trigger
bits : 9 - 9 (1 bit)

SWTRIG10 : Channel 10 Software Trigger
bits : 10 - 10 (1 bit)

SWTRIG11 : Channel 11 Software Trigger
bits : 11 - 11 (1 bit)

SWTRIG12 : Channel 12 Software Trigger
bits : 12 - 12 (1 bit)

SWTRIG13 : Channel 13 Software Trigger
bits : 13 - 13 (1 bit)

SWTRIG14 : Channel 14 Software Trigger
bits : 14 - 14 (1 bit)

SWTRIG15 : Channel 15 Software Trigger
bits : 15 - 15 (1 bit)

SWTRIG16 : Channel 16 Software Trigger
bits : 16 - 16 (1 bit)

SWTRIG17 : Channel 17 Software Trigger
bits : 17 - 17 (1 bit)

SWTRIG18 : Channel 18 Software Trigger
bits : 18 - 18 (1 bit)

SWTRIG19 : Channel 19 Software Trigger
bits : 19 - 19 (1 bit)

SWTRIG20 : Channel 20 Software Trigger
bits : 20 - 20 (1 bit)

SWTRIG21 : Channel 21 Software Trigger
bits : 21 - 21 (1 bit)

SWTRIG22 : Channel 22 Software Trigger
bits : 22 - 22 (1 bit)

SWTRIG23 : Channel 23 Software Trigger
bits : 23 - 23 (1 bit)

SWTRIG24 : Channel 24 Software Trigger
bits : 24 - 24 (1 bit)

SWTRIG25 : Channel 25 Software Trigger
bits : 25 - 25 (1 bit)

SWTRIG26 : Channel 26 Software Trigger
bits : 26 - 26 (1 bit)

SWTRIG27 : Channel 27 Software Trigger
bits : 27 - 27 (1 bit)

SWTRIG28 : Channel 28 Software Trigger
bits : 28 - 28 (1 bit)

SWTRIG29 : Channel 29 Software Trigger
bits : 29 - 29 (1 bit)

SWTRIG30 : Channel 30 Software Trigger
bits : 30 - 30 (1 bit)

SWTRIG31 : Channel 31 Software Trigger
bits : 31 - 31 (1 bit)


CHCTRLA12

Channel n Control A
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA12 CHCTRLA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB12

Channel n Control B
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB12 CHCTRLB12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL12

Channel n Priority Level
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL12 CHPRILVL12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL12

Channel n Event Control
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL12 CHEVCTRL12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR12

Channel n Interrupt Enable Clear
address_offset : 0x10C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR12 CHINTENCLR12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET12

Channel n Interrupt Enable Set
address_offset : 0x10D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET12 CHINTENSET12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG12

Channel n Interrupt Flag Status and Clear
address_offset : 0x10E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG12 CHINTFLAG12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x10E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x10E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x10E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x10EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x10ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x10EE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x10EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHSTATUS12

Channel n Status
address_offset : 0x10F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS12 CHSTATUS12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA13

Channel n Control A
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA13 CHCTRLA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB13

Channel n Control B
address_offset : 0x114 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB13 CHCTRLB13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL13

Channel n Priority Level
address_offset : 0x115 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL13 CHPRILVL13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL13

Channel n Event Control
address_offset : 0x116 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL13 CHEVCTRL13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR13

Channel n Interrupt Enable Clear
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR13 CHINTENCLR13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET13

Channel n Interrupt Enable Set
address_offset : 0x11D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET13 CHINTENSET13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG13

Channel n Interrupt Flag Status and Clear
address_offset : 0x11E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG13 CHINTFLAG13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS13

Channel n Status
address_offset : 0x11F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS13 CHSTATUS13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA14

Channel n Control A
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA14 CHCTRLA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB14

Channel n Control B
address_offset : 0x124 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB14 CHCTRLB14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL14

Channel n Priority Level
address_offset : 0x125 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL14 CHPRILVL14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL14

Channel n Event Control
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL14 CHEVCTRL14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x1260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x1264 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x1265 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x1266 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x126C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x126D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x126E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x126F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTENCLR14

Channel n Interrupt Enable Clear
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR14 CHINTENCLR14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET14

Channel n Interrupt Enable Set
address_offset : 0x12D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET14 CHINTENSET14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG14

Channel n Interrupt Flag Status and Clear
address_offset : 0x12E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG14 CHINTFLAG14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS14

Channel n Status
address_offset : 0x12F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS14 CHSTATUS14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA15

Channel n Control A
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA15 CHCTRLA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB15

Channel n Control B
address_offset : 0x134 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB15 CHCTRLB15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL15

Channel n Priority Level
address_offset : 0x135 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL15 CHPRILVL15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL15

Channel n Event Control
address_offset : 0x136 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL15 CHEVCTRL15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR15

Channel n Interrupt Enable Clear
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR15 CHINTENCLR15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET15

Channel n Interrupt Enable Set
address_offset : 0x13D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET15 CHINTENSET15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG15

Channel n Interrupt Flag Status and Clear
address_offset : 0x13E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG15 CHINTFLAG15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS15

Channel n Status
address_offset : 0x13F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS15 CHSTATUS15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x13F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x13F4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x13F5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x13F6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x13FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x13FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x13FE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x13FF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


PRICTRL0

Priority Control 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRICTRL0 PRICTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVLPRI0 QOS0 RRLVLEN0 LVLPRI1 QOS1 RRLVLEN1 LVLPRI2 QOS2 RRLVLEN2 LVLPRI3 QOS3 RRLVLEN3

LVLPRI0 : Level 0 Channel Priority Number
bits : 0 - 4 (5 bit)

QOS0 : Level 0 Quality of Service
bits : 5 - 6 (2 bit)

Enumeration: QOS0Select

0 : REGULAR

Regular delivery

1 : SHORTAGE

Bandwidth shortage

2 : SENSITIVE

Latency sensitive

3 : CRITICAL

Latency critical

End of enumeration elements list.

RRLVLEN0 : Level 0 Round-Robin Scheduling Enable
bits : 7 - 7 (1 bit)

LVLPRI1 : Level 1 Channel Priority Number
bits : 8 - 12 (5 bit)

QOS1 : Level 1 Quality of Service
bits : 13 - 14 (2 bit)

Enumeration: QOS1Select

0 : REGULAR

Regular delivery

1 : SHORTAGE

Bandwidth shortage

2 : SENSITIVE

Latency sensitive

3 : CRITICAL

Latency critical

End of enumeration elements list.

RRLVLEN1 : Level 1 Round-Robin Scheduling Enable
bits : 15 - 15 (1 bit)

LVLPRI2 : Level 2 Channel Priority Number
bits : 16 - 20 (5 bit)

QOS2 : Level 2 Quality of Service
bits : 21 - 22 (2 bit)

Enumeration: QOS2Select

0 : REGULAR

Regular delivery

1 : SHORTAGE

Bandwidth shortage

2 : SENSITIVE

Latency sensitive

3 : CRITICAL

Latency critical

End of enumeration elements list.

RRLVLEN2 : Level 2 Round-Robin Scheduling Enable
bits : 23 - 23 (1 bit)

LVLPRI3 : Level 3 Channel Priority Number
bits : 24 - 28 (5 bit)

QOS3 : Level 3 Quality of Service
bits : 29 - 30 (2 bit)

Enumeration: QOS3Select

0 : REGULAR

Regular delivery

1 : SHORTAGE

Bandwidth shortage

2 : SENSITIVE

Latency sensitive

3 : CRITICAL

Latency critical

End of enumeration elements list.

RRLVLEN3 : Level 3 Round-Robin Scheduling Enable
bits : 31 - 31 (1 bit)


CHCTRLA16

Channel n Control A
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA16 CHCTRLA16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB16

Channel n Control B
address_offset : 0x144 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB16 CHCTRLB16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL16

Channel n Priority Level
address_offset : 0x145 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL16 CHPRILVL16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL16

Channel n Event Control
address_offset : 0x146 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL16 CHEVCTRL16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR16

Channel n Interrupt Enable Clear
address_offset : 0x14C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR16 CHINTENCLR16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET16

Channel n Interrupt Enable Set
address_offset : 0x14D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET16 CHINTENSET16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG16

Channel n Interrupt Flag Status and Clear
address_offset : 0x14E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG16 CHINTFLAG16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS16

Channel n Status
address_offset : 0x14F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS16 CHSTATUS16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA17

Channel n Control A
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA17 CHCTRLA17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB17

Channel n Control B
address_offset : 0x154 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB17 CHCTRLB17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL17

Channel n Priority Level
address_offset : 0x155 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL17 CHPRILVL17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL17

Channel n Event Control
address_offset : 0x156 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL17 CHEVCTRL17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x1590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x1594 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x1595 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x1596 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x159C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x159D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x159E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x159F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTENCLR17

Channel n Interrupt Enable Clear
address_offset : 0x15C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR17 CHINTENCLR17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET17

Channel n Interrupt Enable Set
address_offset : 0x15D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET17 CHINTENSET17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG17

Channel n Interrupt Flag Status and Clear
address_offset : 0x15E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG17 CHINTFLAG17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS17

Channel n Status
address_offset : 0x15F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS17 CHSTATUS17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLA18

Channel n Control A
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA18 CHCTRLA18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHCTRLB18

Channel n Control B
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB18 CHCTRLB18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x165 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHPRILVL18

Channel n Priority Level
address_offset : 0x165 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL18 CHPRILVL18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHEVCTRL18

Channel n Event Control
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL18 CHEVCTRL18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENCLR18

Channel n Interrupt Enable Clear
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR18 CHINTENCLR18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x16D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET18

Channel n Interrupt Enable Set
address_offset : 0x16D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET18 CHINTENSET18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x16E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHINTFLAG18

Channel n Interrupt Flag Status and Clear
address_offset : 0x16E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG18 CHINTFLAG18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x16F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHSTATUS18

Channel n Status
address_offset : 0x16F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS18 CHSTATUS18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA19

Channel n Control A
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA19 CHCTRLA19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB19

Channel n Control B
address_offset : 0x174 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB19 CHCTRLB19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x1740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x1744 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x1745 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x1746 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x174C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x174D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x174E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x174F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHPRILVL19

Channel n Priority Level
address_offset : 0x175 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL19 CHPRILVL19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL19

Channel n Event Control
address_offset : 0x176 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL19 CHEVCTRL19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR19

Channel n Interrupt Enable Clear
address_offset : 0x17C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR19 CHINTENCLR19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET19

Channel n Interrupt Enable Set
address_offset : 0x17D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET19 CHINTENSET19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG19

Channel n Interrupt Flag Status and Clear
address_offset : 0x17E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG19 CHINTFLAG19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS19

Channel n Status
address_offset : 0x17F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS19 CHSTATUS19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA20

Channel n Control A
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA20 CHCTRLA20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB20

Channel n Control B
address_offset : 0x184 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB20 CHCTRLB20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL20

Channel n Priority Level
address_offset : 0x185 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL20 CHPRILVL20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL20

Channel n Event Control
address_offset : 0x186 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL20 CHEVCTRL20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR20

Channel n Interrupt Enable Clear
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR20 CHINTENCLR20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET20

Channel n Interrupt Enable Set
address_offset : 0x18D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET20 CHINTENSET20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG20

Channel n Interrupt Flag Status and Clear
address_offset : 0x18E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG20 CHINTFLAG20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS20

Channel n Status
address_offset : 0x18F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS20 CHSTATUS20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA21

Channel n Control A
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA21 CHCTRLA21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x1900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x1904 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x1905 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x1906 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x190C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x190D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x190E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x190F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLB21

Channel n Control B
address_offset : 0x194 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB21 CHCTRLB21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL21

Channel n Priority Level
address_offset : 0x195 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL21 CHPRILVL21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL21

Channel n Event Control
address_offset : 0x196 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL21 CHEVCTRL21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR21

Channel n Interrupt Enable Clear
address_offset : 0x19C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR21 CHINTENCLR21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET21

Channel n Interrupt Enable Set
address_offset : 0x19D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET21 CHINTENSET21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG21

Channel n Interrupt Flag Status and Clear
address_offset : 0x19E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG21 CHINTFLAG21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS21

Channel n Status
address_offset : 0x19F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS21 CHSTATUS21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA22

Channel n Control A
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA22 CHCTRLA22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB22

Channel n Control B
address_offset : 0x1A4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB22 CHCTRLB22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL22

Channel n Priority Level
address_offset : 0x1A5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL22 CHPRILVL22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL22

Channel n Event Control
address_offset : 0x1A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL22 CHEVCTRL22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR22

Channel n Interrupt Enable Clear
address_offset : 0x1AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR22 CHINTENCLR22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET22

Channel n Interrupt Enable Set
address_offset : 0x1AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET22 CHINTENSET22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x1AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x1AD4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x1AD5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x1AD6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x1ADC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x1ADD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x1ADE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x1ADF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTFLAG22

Channel n Interrupt Flag Status and Clear
address_offset : 0x1AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG22 CHINTFLAG22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS22

Channel n Status
address_offset : 0x1AF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS22 CHSTATUS22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA23

Channel n Control A
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA23 CHCTRLA23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB23

Channel n Control B
address_offset : 0x1B4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB23 CHCTRLB23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL23

Channel n Priority Level
address_offset : 0x1B5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL23 CHPRILVL23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL23

Channel n Event Control
address_offset : 0x1B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL23 CHEVCTRL23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR23

Channel n Interrupt Enable Clear
address_offset : 0x1BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR23 CHINTENCLR23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET23

Channel n Interrupt Enable Set
address_offset : 0x1BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET23 CHINTENSET23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG23

Channel n Interrupt Flag Status and Clear
address_offset : 0x1BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG23 CHINTFLAG23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS23

Channel n Status
address_offset : 0x1BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS23 CHSTATUS23 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA24

Channel n Control A
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA24 CHCTRLA24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB24

Channel n Control B
address_offset : 0x1C4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB24 CHCTRLB24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL24

Channel n Priority Level
address_offset : 0x1C5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL24 CHPRILVL24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL24

Channel n Event Control
address_offset : 0x1C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL24 CHEVCTRL24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x1CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x1CB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x1CB5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x1CB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x1CBC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x1CBD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x1CBE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x1CBF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTENCLR24

Channel n Interrupt Enable Clear
address_offset : 0x1CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR24 CHINTENCLR24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET24

Channel n Interrupt Enable Set
address_offset : 0x1CD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET24 CHINTENSET24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG24

Channel n Interrupt Flag Status and Clear
address_offset : 0x1CE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG24 CHINTFLAG24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS24

Channel n Status
address_offset : 0x1CF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS24 CHSTATUS24 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA25

Channel n Control A
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA25 CHCTRLA25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB25

Channel n Control B
address_offset : 0x1D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB25 CHCTRLB25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL25

Channel n Priority Level
address_offset : 0x1D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL25 CHPRILVL25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL25

Channel n Event Control
address_offset : 0x1D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL25 CHEVCTRL25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR25

Channel n Interrupt Enable Clear
address_offset : 0x1DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR25 CHINTENCLR25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET25

Channel n Interrupt Enable Set
address_offset : 0x1DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET25 CHINTENSET25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG25

Channel n Interrupt Flag Status and Clear
address_offset : 0x1DE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG25 CHINTFLAG25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS25

Channel n Status
address_offset : 0x1DF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS25 CHSTATUS25 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLA26

Channel n Control A
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA26 CHCTRLA26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHCTRLB26

Channel n Control B
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB26 CHCTRLB26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHPRILVL26

Channel n Priority Level
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL26 CHPRILVL26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHEVCTRL26

Channel n Event Control
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL26 CHEVCTRL26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x1EA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x1EA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x1EA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x1EA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x1EAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x1EAD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x1EAE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x1EAF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x1EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENCLR26

Channel n Interrupt Enable Clear
address_offset : 0x1EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR26 CHINTENCLR26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x1ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET26

Channel n Interrupt Enable Set
address_offset : 0x1ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET26 CHINTENSET26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x1EE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHINTFLAG26

Channel n Interrupt Flag Status and Clear
address_offset : 0x1EE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG26 CHINTFLAG26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x1EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHSTATUS26

Channel n Status
address_offset : 0x1EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS26 CHSTATUS26 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA27

Channel n Control A
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA27 CHCTRLA27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB27

Channel n Control B
address_offset : 0x1F4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB27 CHCTRLB27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL27

Channel n Priority Level
address_offset : 0x1F5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL27 CHPRILVL27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL27

Channel n Event Control
address_offset : 0x1F6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL27 CHEVCTRL27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR27

Channel n Interrupt Enable Clear
address_offset : 0x1FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR27 CHINTENCLR27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET27

Channel n Interrupt Enable Set
address_offset : 0x1FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET27 CHINTENSET27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG27

Channel n Interrupt Flag Status and Clear
address_offset : 0x1FE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG27 CHINTFLAG27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS27

Channel n Status
address_offset : 0x1FF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS27 CHSTATUS27 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CRCCTRL

CRC Control
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCCTRL CRCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCBEATSIZE CRCPOLY CRCSRC CRCMODE

CRCBEATSIZE : CRC Beat Size
bits : 0 - 1 (2 bit)

Enumeration: CRCBEATSIZESelect

0x0 : BYTE

8-bit bus transfer

0x1 : HWORD

16-bit bus transfer

0x2 : WORD

32-bit bus transfer

End of enumeration elements list.

CRCPOLY : CRC Polynomial Type
bits : 2 - 3 (2 bit)

Enumeration: CRCPOLYSelect

0x0 : CRC16

CRC-16 (CRC-CCITT)

0x1 : CRC32

CRC32 (IEEE 802.3)

End of enumeration elements list.

CRCSRC : CRC Input Source
bits : 8 - 13 (6 bit)

Enumeration: CRCSRCSelect

0x00 : DISABLE

CRC Disabled

0x01 : IO

I/O interface

End of enumeration elements list.

CRCMODE : CRC Operating Mode
bits : 14 - 15 (2 bit)

Enumeration: CRCMODESelect

0 : DEFAULT

Default operating mode

2 : CRCMON

Memory CRC monitor operating mode

3 : CRCGEN

Memory CRC generation operating mode

End of enumeration elements list.


INTPEND

Interrupt Pending
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTPEND INTPEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID TERR TCMPL SUSP CRCERR FERR BUSY PEND

ID : Channel ID
bits : 0 - 4 (5 bit)

TERR : Transfer Error
bits : 8 - 8 (1 bit)

TCMPL : Transfer Complete
bits : 9 - 9 (1 bit)

SUSP : Channel Suspend
bits : 10 - 10 (1 bit)

CRCERR : CRC Error
bits : 12 - 12 (1 bit)

FERR : Fetch Error
bits : 13 - 13 (1 bit)

BUSY : Busy
bits : 14 - 14 (1 bit)

PEND : Pending
bits : 15 - 15 (1 bit)


CHCTRLA28

Channel n Control A
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA28 CHCTRLA28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB28

Channel n Control B
address_offset : 0x204 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB28 CHCTRLB28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL28

Channel n Priority Level
address_offset : 0x205 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL28 CHPRILVL28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL28

Channel n Event Control
address_offset : 0x206 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL28 CHEVCTRL28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x20A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x20A4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x20A5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x20A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x20AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x20AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x20AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x20AF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTENCLR28

Channel n Interrupt Enable Clear
address_offset : 0x20C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR28 CHINTENCLR28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET28

Channel n Interrupt Enable Set
address_offset : 0x20D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET28 CHINTENSET28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG28

Channel n Interrupt Flag Status and Clear
address_offset : 0x20E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG28 CHINTFLAG28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS28

Channel n Status
address_offset : 0x20F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS28 CHSTATUS28 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA29

Channel n Control A
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA29 CHCTRLA29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB29

Channel n Control B
address_offset : 0x214 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB29 CHCTRLB29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL29

Channel n Priority Level
address_offset : 0x215 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL29 CHPRILVL29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL29

Channel n Event Control
address_offset : 0x216 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL29 CHEVCTRL29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR29

Channel n Interrupt Enable Clear
address_offset : 0x21C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR29 CHINTENCLR29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET29

Channel n Interrupt Enable Set
address_offset : 0x21D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET29 CHINTENSET29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG29

Channel n Interrupt Flag Status and Clear
address_offset : 0x21E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG29 CHINTFLAG29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS29

Channel n Status
address_offset : 0x21F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS29 CHSTATUS29 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA30

Channel n Control A
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA30 CHCTRLA30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB30

Channel n Control B
address_offset : 0x224 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB30 CHCTRLB30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL30

Channel n Priority Level
address_offset : 0x225 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL30 CHPRILVL30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL30

Channel n Event Control
address_offset : 0x226 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL30 CHEVCTRL30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x22B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x22B4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x22B5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x22B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x22BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x22BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x22BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x22BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTENCLR30

Channel n Interrupt Enable Clear
address_offset : 0x22C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR30 CHINTENCLR30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET30

Channel n Interrupt Enable Set
address_offset : 0x22D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET30 CHINTENSET30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG30

Channel n Interrupt Flag Status and Clear
address_offset : 0x22E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG30 CHINTFLAG30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS30

Channel n Status
address_offset : 0x22F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS30 CHSTATUS30 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA31

Channel n Control A
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA31 CHCTRLA31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB31

Channel n Control B
address_offset : 0x234 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB31 CHCTRLB31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL31

Channel n Priority Level
address_offset : 0x235 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL31 CHPRILVL31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL31

Channel n Event Control
address_offset : 0x236 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL31 CHEVCTRL31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR31

Channel n Interrupt Enable Clear
address_offset : 0x23C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR31 CHINTENCLR31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET31

Channel n Interrupt Enable Set
address_offset : 0x23D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET31 CHINTENSET31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG31

Channel n Interrupt Flag Status and Clear
address_offset : 0x23E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG31 CHINTFLAG31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS31

Channel n Status
address_offset : 0x23F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS31 CHSTATUS31 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


INTSTATUS

Interrupt Status
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS INTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHINT0 CHINT1 CHINT2 CHINT3 CHINT4 CHINT5 CHINT6 CHINT7 CHINT8 CHINT9 CHINT10 CHINT11 CHINT12 CHINT13 CHINT14 CHINT15 CHINT16 CHINT17 CHINT18 CHINT19 CHINT20 CHINT21 CHINT22 CHINT23 CHINT24 CHINT25 CHINT26 CHINT27 CHINT28 CHINT29 CHINT30 CHINT31

CHINT0 : Channel 0 Pending Interrupt
bits : 0 - 0 (1 bit)

CHINT1 : Channel 1 Pending Interrupt
bits : 1 - 1 (1 bit)

CHINT2 : Channel 2 Pending Interrupt
bits : 2 - 2 (1 bit)

CHINT3 : Channel 3 Pending Interrupt
bits : 3 - 3 (1 bit)

CHINT4 : Channel 4 Pending Interrupt
bits : 4 - 4 (1 bit)

CHINT5 : Channel 5 Pending Interrupt
bits : 5 - 5 (1 bit)

CHINT6 : Channel 6 Pending Interrupt
bits : 6 - 6 (1 bit)

CHINT7 : Channel 7 Pending Interrupt
bits : 7 - 7 (1 bit)

CHINT8 : Channel 8 Pending Interrupt
bits : 8 - 8 (1 bit)

CHINT9 : Channel 9 Pending Interrupt
bits : 9 - 9 (1 bit)

CHINT10 : Channel 10 Pending Interrupt
bits : 10 - 10 (1 bit)

CHINT11 : Channel 11 Pending Interrupt
bits : 11 - 11 (1 bit)

CHINT12 : Channel 12 Pending Interrupt
bits : 12 - 12 (1 bit)

CHINT13 : Channel 13 Pending Interrupt
bits : 13 - 13 (1 bit)

CHINT14 : Channel 14 Pending Interrupt
bits : 14 - 14 (1 bit)

CHINT15 : Channel 15 Pending Interrupt
bits : 15 - 15 (1 bit)

CHINT16 : Channel 16 Pending Interrupt
bits : 16 - 16 (1 bit)

CHINT17 : Channel 17 Pending Interrupt
bits : 17 - 17 (1 bit)

CHINT18 : Channel 18 Pending Interrupt
bits : 18 - 18 (1 bit)

CHINT19 : Channel 19 Pending Interrupt
bits : 19 - 19 (1 bit)

CHINT20 : Channel 20 Pending Interrupt
bits : 20 - 20 (1 bit)

CHINT21 : Channel 21 Pending Interrupt
bits : 21 - 21 (1 bit)

CHINT22 : Channel 22 Pending Interrupt
bits : 22 - 22 (1 bit)

CHINT23 : Channel 23 Pending Interrupt
bits : 23 - 23 (1 bit)

CHINT24 : Channel 24 Pending Interrupt
bits : 24 - 24 (1 bit)

CHINT25 : Channel 25 Pending Interrupt
bits : 25 - 25 (1 bit)

CHINT26 : Channel 26 Pending Interrupt
bits : 26 - 26 (1 bit)

CHINT27 : Channel 27 Pending Interrupt
bits : 27 - 27 (1 bit)

CHINT28 : Channel 28 Pending Interrupt
bits : 28 - 28 (1 bit)

CHINT29 : Channel 29 Pending Interrupt
bits : 29 - 29 (1 bit)

CHINT30 : Channel 30 Pending Interrupt
bits : 30 - 30 (1 bit)

CHINT31 : Channel 31 Pending Interrupt
bits : 31 - 31 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x24D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x24D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x24D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x24D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x24DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x24DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x24DE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x24DF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x2700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x2704 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x2705 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x2706 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x270C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x270D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x270E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x270F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x274 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x275 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x276 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x27C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x27D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x27E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x27F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


BUSYCH

Busy Channels
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSYCH BUSYCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSYCH0 BUSYCH1 BUSYCH2 BUSYCH3 BUSYCH4 BUSYCH5 BUSYCH6 BUSYCH7 BUSYCH8 BUSYCH9 BUSYCH10 BUSYCH11 BUSYCH12 BUSYCH13 BUSYCH14 BUSYCH15 BUSYCH16 BUSYCH17 BUSYCH18 BUSYCH19 BUSYCH20 BUSYCH21 BUSYCH22 BUSYCH23 BUSYCH24 BUSYCH25 BUSYCH26 BUSYCH27 BUSYCH28 BUSYCH29 BUSYCH30 BUSYCH31

BUSYCH0 : Busy Channel 0
bits : 0 - 0 (1 bit)

BUSYCH1 : Busy Channel 1
bits : 1 - 1 (1 bit)

BUSYCH2 : Busy Channel 2
bits : 2 - 2 (1 bit)

BUSYCH3 : Busy Channel 3
bits : 3 - 3 (1 bit)

BUSYCH4 : Busy Channel 4
bits : 4 - 4 (1 bit)

BUSYCH5 : Busy Channel 5
bits : 5 - 5 (1 bit)

BUSYCH6 : Busy Channel 6
bits : 6 - 6 (1 bit)

BUSYCH7 : Busy Channel 7
bits : 7 - 7 (1 bit)

BUSYCH8 : Busy Channel 8
bits : 8 - 8 (1 bit)

BUSYCH9 : Busy Channel 9
bits : 9 - 9 (1 bit)

BUSYCH10 : Busy Channel 10
bits : 10 - 10 (1 bit)

BUSYCH11 : Busy Channel 11
bits : 11 - 11 (1 bit)

BUSYCH12 : Busy Channel 12
bits : 12 - 12 (1 bit)

BUSYCH13 : Busy Channel 13
bits : 13 - 13 (1 bit)

BUSYCH14 : Busy Channel 14
bits : 14 - 14 (1 bit)

BUSYCH15 : Busy Channel 15
bits : 15 - 15 (1 bit)

BUSYCH16 : Busy Channel 16
bits : 16 - 16 (1 bit)

BUSYCH17 : Busy Channel 17
bits : 17 - 17 (1 bit)

BUSYCH18 : Busy Channel 18
bits : 18 - 18 (1 bit)

BUSYCH19 : Busy Channel 19
bits : 19 - 19 (1 bit)

BUSYCH20 : Busy Channel 20
bits : 20 - 20 (1 bit)

BUSYCH21 : Busy Channel 21
bits : 21 - 21 (1 bit)

BUSYCH22 : Busy Channel 22
bits : 22 - 22 (1 bit)

BUSYCH23 : Busy Channel 23
bits : 23 - 23 (1 bit)

BUSYCH24 : Busy Channel 24
bits : 24 - 24 (1 bit)

BUSYCH25 : Busy Channel 25
bits : 25 - 25 (1 bit)

BUSYCH26 : Busy Channel 26
bits : 26 - 26 (1 bit)

BUSYCH27 : Busy Channel 27
bits : 27 - 27 (1 bit)

BUSYCH28 : Busy Channel 28
bits : 28 - 28 (1 bit)

BUSYCH29 : Busy Channel 29
bits : 29 - 29 (1 bit)

BUSYCH30 : Busy Channel 30
bits : 30 - 30 (1 bit)

BUSYCH31 : Busy Channel 31
bits : 31 - 31 (1 bit)


PENDCH

Pending Channels
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PENDCH PENDCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PENDCH0 PENDCH1 PENDCH2 PENDCH3 PENDCH4 PENDCH5 PENDCH6 PENDCH7 PENDCH8 PENDCH9 PENDCH10 PENDCH11 PENDCH12 PENDCH13 PENDCH14 PENDCH15 PENDCH16 PENDCH17 PENDCH18 PENDCH19 PENDCH20 PENDCH21 PENDCH22 PENDCH23 PENDCH24 PENDCH25 PENDCH26 PENDCH27 PENDCH28 PENDCH29 PENDCH30 PENDCH31

PENDCH0 : Pending Channel 0
bits : 0 - 0 (1 bit)

PENDCH1 : Pending Channel 1
bits : 1 - 1 (1 bit)

PENDCH2 : Pending Channel 2
bits : 2 - 2 (1 bit)

PENDCH3 : Pending Channel 3
bits : 3 - 3 (1 bit)

PENDCH4 : Pending Channel 4
bits : 4 - 4 (1 bit)

PENDCH5 : Pending Channel 5
bits : 5 - 5 (1 bit)

PENDCH6 : Pending Channel 6
bits : 6 - 6 (1 bit)

PENDCH7 : Pending Channel 7
bits : 7 - 7 (1 bit)

PENDCH8 : Pending Channel 8
bits : 8 - 8 (1 bit)

PENDCH9 : Pending Channel 9
bits : 9 - 9 (1 bit)

PENDCH10 : Pending Channel 10
bits : 10 - 10 (1 bit)

PENDCH11 : Pending Channel 11
bits : 11 - 11 (1 bit)

PENDCH12 : Pending Channel 12
bits : 12 - 12 (1 bit)

PENDCH13 : Pending Channel 13
bits : 13 - 13 (1 bit)

PENDCH14 : Pending Channel 14
bits : 14 - 14 (1 bit)

PENDCH15 : Pending Channel 15
bits : 15 - 15 (1 bit)

PENDCH16 : Pending Channel 16
bits : 16 - 16 (1 bit)

PENDCH17 : Pending Channel 17
bits : 17 - 17 (1 bit)

PENDCH18 : Pending Channel 18
bits : 18 - 18 (1 bit)

PENDCH19 : Pending Channel 19
bits : 19 - 19 (1 bit)

PENDCH20 : Pending Channel 20
bits : 20 - 20 (1 bit)

PENDCH21 : Pending Channel 21
bits : 21 - 21 (1 bit)

PENDCH22 : Pending Channel 22
bits : 22 - 22 (1 bit)

PENDCH23 : Pending Channel 23
bits : 23 - 23 (1 bit)

PENDCH24 : Pending Channel 24
bits : 24 - 24 (1 bit)

PENDCH25 : Pending Channel 25
bits : 25 - 25 (1 bit)

PENDCH26 : Pending Channel 26
bits : 26 - 26 (1 bit)

PENDCH27 : Pending Channel 27
bits : 27 - 27 (1 bit)

PENDCH28 : Pending Channel 28
bits : 28 - 28 (1 bit)

PENDCH29 : Pending Channel 29
bits : 29 - 29 (1 bit)

PENDCH30 : Pending Channel 30
bits : 30 - 30 (1 bit)

PENDCH31 : Pending Channel 31
bits : 31 - 31 (1 bit)


ACTIVE

Active Channel and Levels
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ACTIVE ACTIVE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVLEX0 LVLEX1 LVLEX2 LVLEX3 ID ABUSY BTCNT

LVLEX0 : Level 0 Channel Trigger Request Executing
bits : 0 - 0 (1 bit)

LVLEX1 : Level 1 Channel Trigger Request Executing
bits : 1 - 1 (1 bit)

LVLEX2 : Level 2 Channel Trigger Request Executing
bits : 2 - 2 (1 bit)

LVLEX3 : Level 3 Channel Trigger Request Executing
bits : 3 - 3 (1 bit)

ID : Active Channel ID
bits : 8 - 12 (5 bit)

ABUSY : Active Channel Busy
bits : 15 - 15 (1 bit)

BTCNT : Active Channel Block Transfer Count
bits : 16 - 31 (16 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x314 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x315 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x316 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x31C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x31D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x31E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x31F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


BASEADDR

Descriptor Memory Section Base Address
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASEADDR BASEADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASEADDR

BASEADDR : Descriptor Memory Base Address
bits : 0 - 31 (32 bit)


WRBADDR

Write-Back Memory Section Base Address
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRBADDR WRBADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRBADDR

WRBADDR : Write-Back Memory Base Address
bits : 0 - 31 (32 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x3C4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x3C5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x3C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x3CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x3CD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x3CE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x3CF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CRCDATAIN

CRC Data Input
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCDATAIN CRCDATAIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDATAIN

CRCDATAIN : CRC Data Input
bits : 0 - 31 (32 bit)


CHCTRLB

Channel n Control B
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHCTRLA CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLA0

Channel n Control A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA0 CHCTRLA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHCTRLB CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHCTRLB0

Channel n Control B
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB0 CHCTRLB0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHPRILVL CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHPRILVL0

Channel n Priority Level
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL0 CHPRILVL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHEVCTRL CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHEVCTRL0

Channel n Event Control
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL0 CHEVCTRL0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x484 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x485 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x486 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x48C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x48D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x48E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x48F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTENCLR CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENCLR0

Channel n Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR0 CHINTENCLR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTENSET CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET0

Channel n Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET0 CHINTENSET0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTFLAG CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHINTFLAG0

Channel n Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG0 CHINTFLAG0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHSTATUS CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHSTATUS0

Channel n Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS0 CHSTATUS0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHPRILVL

Channel n Priority Level
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHCTRLA1

Channel n Control A
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA1 CHCTRLA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB1

Channel n Control B
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB1 CHCTRLB1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL1

Channel n Priority Level
address_offset : 0x55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL1 CHPRILVL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x554 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x555 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x556 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x55C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x55D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x55E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x55F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHEVCTRL1

Channel n Event Control
address_offset : 0x56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL1 CHEVCTRL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR1

Channel n Interrupt Enable Clear
address_offset : 0x5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR1 CHINTENCLR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET1

Channel n Interrupt Enable Set
address_offset : 0x5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET1 CHINTENSET1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG1

Channel n Interrupt Flag Status and Clear
address_offset : 0x5E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG1 CHINTFLAG1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS1

Channel n Status
address_offset : 0x5F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS1 CHSTATUS1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHEVCTRL

Channel n Event Control
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHCTRLA2

Channel n Control A
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA2 CHCTRLA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x634 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x635 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x636 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x63C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x63D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x63E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x63F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLB2

Channel n Control B
address_offset : 0x64 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB2 CHCTRLB2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL2

Channel n Priority Level
address_offset : 0x65 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL2 CHPRILVL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL2

Channel n Event Control
address_offset : 0x66 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL2 CHEVCTRL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR2

Channel n Interrupt Enable Clear
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR2 CHINTENCLR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET2

Channel n Interrupt Enable Set
address_offset : 0x6D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET2 CHINTENSET2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG2

Channel n Interrupt Flag Status and Clear
address_offset : 0x6E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG2 CHINTFLAG2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS2

Channel n Status
address_offset : 0x6F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS2 CHSTATUS2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA3

Channel n Control A
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA3 CHCTRLA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x724 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x725 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x726 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x72C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x72D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x72E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x72F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLB3

Channel n Control B
address_offset : 0x74 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB3 CHCTRLB3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL3

Channel n Priority Level
address_offset : 0x75 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL3 CHPRILVL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL3

Channel n Event Control
address_offset : 0x76 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL3 CHEVCTRL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR3

Channel n Interrupt Enable Clear
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR3 CHINTENCLR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET3

Channel n Interrupt Enable Set
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET3 CHINTENSET3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG3

Channel n Interrupt Flag Status and Clear
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG3 CHINTFLAG3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS3

Channel n Status
address_offset : 0x7F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS3 CHSTATUS3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CRCCHKSUM

CRC Checksum
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCCHKSUM CRCCHKSUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCCHKSUM

CRCCHKSUM : CRC Checksum
bits : 0 - 31 (32 bit)


CHCTRLA4

Channel n Control A
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA4 CHCTRLA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x824 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x825 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x826 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x82C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x82D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x82E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x82F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLB4

Channel n Control B
address_offset : 0x84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB4 CHCTRLB4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL4

Channel n Priority Level
address_offset : 0x85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL4 CHPRILVL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL4

Channel n Event Control
address_offset : 0x86 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL4 CHEVCTRL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR4

Channel n Interrupt Enable Clear
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR4 CHINTENCLR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET4

Channel n Interrupt Enable Set
address_offset : 0x8D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET4 CHINTENSET4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG4

Channel n Interrupt Flag Status and Clear
address_offset : 0x8E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG4 CHINTFLAG4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS4

Channel n Status
address_offset : 0x8F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS4 CHSTATUS4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLA5

Channel n Control A
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA5 CHCTRLA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x934 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x935 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x936 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x93C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x93D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x93E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x93F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHCTRLB5

Channel n Control B
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB5 CHCTRLB5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0x95 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHPRILVL5

Channel n Priority Level
address_offset : 0x95 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL5 CHPRILVL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0x96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHEVCTRL5

Channel n Event Control
address_offset : 0x96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL5 CHEVCTRL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENCLR5

Channel n Interrupt Enable Clear
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR5 CHINTENCLR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x9D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET5

Channel n Interrupt Enable Set
address_offset : 0x9D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET5 CHINTENSET5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x9E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHINTFLAG5

Channel n Interrupt Flag Status and Clear
address_offset : 0x9E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG5 CHINTFLAG5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHSTATUS5

Channel n Status
address_offset : 0x9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS5 CHSTATUS5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA6

Channel n Control A
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA6 CHCTRLA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB6

Channel n Control B
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB6 CHCTRLB6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL6

Channel n Priority Level
address_offset : 0xA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL6 CHPRILVL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0xA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0xA54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0xA55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0xA56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xA5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xA5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xA5E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xA5F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHEVCTRL6

Channel n Event Control
address_offset : 0xA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL6 CHEVCTRL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR6

Channel n Interrupt Enable Clear
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR6 CHINTENCLR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET6

Channel n Interrupt Enable Set
address_offset : 0xAD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET6 CHINTENSET6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG6

Channel n Interrupt Flag Status and Clear
address_offset : 0xAE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG6 CHINTFLAG6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS6

Channel n Status
address_offset : 0xAF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS6 CHSTATUS6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLA7

Channel n Control A
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA7 CHCTRLA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB7

Channel n Control B
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB7 CHCTRLB7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL7

Channel n Priority Level
address_offset : 0xB5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL7 CHPRILVL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL7

Channel n Event Control
address_offset : 0xB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL7 CHEVCTRL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0xB84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0xB85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0xB86 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xB8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xB8D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xB8E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xB8F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTENCLR7

Channel n Interrupt Enable Clear
address_offset : 0xBC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR7 CHINTENCLR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET7

Channel n Interrupt Enable Set
address_offset : 0xBD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET7 CHINTENSET7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG7

Channel n Interrupt Flag Status and Clear
address_offset : 0xBE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG7 CHINTFLAG7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS7

Channel n Status
address_offset : 0xBF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS7 CHSTATUS7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CRCSTATUS

CRC Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCSTATUS CRCSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CRCBUSY CRCZERO CRCERR

CRCBUSY : CRC Module Busy
bits : 0 - 0 (1 bit)

CRCZERO : CRC Zero
bits : 1 - 1 (1 bit)

CRCERR : CRC Error
bits : 2 - 2 (1 bit)


CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHCTRLA8

Channel n Control A
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA8 CHCTRLA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB8

Channel n Control B
address_offset : 0xC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB8 CHCTRLB8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL8

Channel n Priority Level
address_offset : 0xC5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL8 CHPRILVL8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL8

Channel n Event Control
address_offset : 0xC6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL8 CHEVCTRL8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR8

Channel n Interrupt Enable Clear
address_offset : 0xCC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR8 CHINTENCLR8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0xCC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0xCC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0xCC5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0xCC6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xCCC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xCCD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xCCE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xCCF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTENSET8

Channel n Interrupt Enable Set
address_offset : 0xCD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET8 CHINTENSET8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG8

Channel n Interrupt Flag Status and Clear
address_offset : 0xCE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG8 CHINTFLAG8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS8

Channel n Status
address_offset : 0xCF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS8 CHSTATUS8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


DBGCTRL

Debug Control
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run
bits : 0 - 0 (1 bit)


CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHCTRLA9

Channel n Control A
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA9 CHCTRLA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLB9

Channel n Control B
address_offset : 0xD4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB9 CHCTRLB9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL9

Channel n Priority Level
address_offset : 0xD5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL9 CHPRILVL9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL9

Channel n Event Control
address_offset : 0xD6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL9 CHEVCTRL9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR9

Channel n Interrupt Enable Clear
address_offset : 0xDC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR9 CHINTENCLR9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET9

Channel n Interrupt Enable Set
address_offset : 0xDD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET9 CHINTENSET9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG9

Channel n Interrupt Flag Status and Clear
address_offset : 0xDE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG9 CHINTFLAG9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS9

Channel n Status
address_offset : 0xDF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS9 CHSTATUS9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHCTRLA10

Channel n Control A
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA10 CHCTRLA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0xE10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0xE14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0xE15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0xE16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xE1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xE1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xE1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xE1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHCTRLB10

Channel n Control B
address_offset : 0xE4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB10 CHCTRLB10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHPRILVL10

Channel n Priority Level
address_offset : 0xE5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL10 CHPRILVL10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHEVCTRL10

Channel n Event Control
address_offset : 0xE6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL10 CHEVCTRL10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHINTENCLR10

Channel n Interrupt Enable Clear
address_offset : 0xEC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR10 CHINTENCLR10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET10

Channel n Interrupt Enable Set
address_offset : 0xED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET10 CHINTENSET10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTFLAG10

Channel n Interrupt Flag Status and Clear
address_offset : 0xEE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG10 CHINTFLAG10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHSTATUS10

Channel n Status
address_offset : 0xEF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS10 CHSTATUS10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHSTATUS

Channel n Status
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHCTRLA11

Channel n Control A
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLA11 CHCTRLA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0x0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0x0 : BLOCK

One trigger required for each block transfer

0x2 : BURST

One trigger required for each burst transfer

0x3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0x0 : SINGLE

Single-beat burst length

0x1 : 2BEAT

2-beats burst length

0x2 : 3BEAT

3-beats burst length

0x3 : 4BEAT

4-beats burst length

0x4 : 5BEAT

5-beats burst length

0x5 : 6BEAT

6-beats burst length

0x6 : 7BEAT

7-beats burst length

0x7 : 8BEAT

8-beats burst length

0x8 : 9BEAT

9-beats burst length

0x9 : 10BEAT

10-beats burst length

0xa : 11BEAT

11-beats burst length

0xb : 12BEAT

12-beats burst length

0xc : 13BEAT

13-beats burst length

0xd : 14BEAT

14-beats burst length

0xe : 15BEAT

15-beats burst length

0xf : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0x0 : 1BEAT

Destination write starts after each beat source address read

0x1 : 2BEATS

Destination write starts after 2-beats source address read

0x2 : 4BEATS

Destination write starts after 4-beats source address read

0x3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHCTRLB11

Channel n Control B
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTRLB11 CHCTRLB11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0xF5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHPRILVL11

Channel n Priority Level
address_offset : 0xF5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHPRILVL11 CHPRILVL11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0x0 : LVL0

Channel Priority Level 0 (Lowest Level)

0x1 : LVL1

Channel Priority Level 1

0x2 : LVL2

Channel Priority Level 2

0x3 : LVL3

Channel Priority Level 3

0x4 : LVL4

Channel Priority Level 4

0x5 : LVL5

Channel Priority Level 5

0x6 : LVL6

Channel Priority Level 6

0x7 : LVL7

Channel Priority Level 7 (Highest Level)

End of enumeration elements list.


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHEVCTRL11

Channel n Event Control
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEVCTRL11 CHEVCTRL11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0x0 : NOACT

No action

0x1 : TRIG

Transfer and periodic transfer trigger

0x2 : CTRIG

Conditional transfer trigger

0x3 : CBLOCK

Conditional block transfer

0x4 : SUSPEND

Channel suspend operation

0x5 : RESUME

Channel resume operation

0x6 : SSKIP

Skip next block suspend action

0x7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0x0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

0x1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA

Channel n Control A
address_offset : 0xF70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE RUNSTDBY TRIGSRC TRIGACT BURSTLEN THRESHOLD

SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Channel Enable
bits : 1 - 1 (1 bit)

RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)

TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)

Enumeration: TRIGSRCSelect

0 : DISABLE

Only software/event triggers

End of enumeration elements list.

TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)

Enumeration: TRIGACTSelect

0 : BLOCK

One trigger required for each block transfer

2 : BURST

One trigger required for each burst transfer

3 : TRANSACTION

One trigger required for each transaction

End of enumeration elements list.

BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)

Enumeration: BURSTLENSelect

0 : SINGLE

Single-beat burst length

1 : 2BEAT

2-beats burst length

2 : 3BEAT

3-beats burst length

3 : 4BEAT

4-beats burst length

4 : 5BEAT

5-beats burst length

5 : 6BEAT

6-beats burst length

6 : 7BEAT

7-beats burst length

7 : 8BEAT

8-beats burst length

8 : 9BEAT

9-beats burst length

9 : 10BEAT

10-beats burst length

10 : 11BEAT

11-beats burst length

11 : 12BEAT

12-beats burst length

12 : 13BEAT

13-beats burst length

13 : 14BEAT

14-beats burst length

14 : 15BEAT

15-beats burst length

15 : 16BEAT

16-beats burst length

End of enumeration elements list.

THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)

Enumeration: THRESHOLDSelect

0 : 1BEAT

Destination write starts after each beat source address read

1 : 2BEATS

Destination write starts after 2-beats source address read

2 : 4BEATS

Destination write starts after 4-beats source address read

3 : 8BEATS

Destination write starts after 8-beats source address read

End of enumeration elements list.


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB

Channel n Control B
address_offset : 0xF74 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CMD

CMD : Software Command
bits : 0 - 1 (2 bit)

Enumeration: CMDSelect

0x0 : NOACT

No action

0x1 : SUSPEND

Channel suspend operation

0x2 : RESUME

Channel resume operation

End of enumeration elements list.


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL

Channel n Priority Level
address_offset : 0xF75 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRILVL

PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)

Enumeration: PRILVLSelect

0 : LVL0

Channel Priority Level 0 (Lowest Level)

1 : LVL1

Channel Priority Level 1

2 : LVL2

Channel Priority Level 2

3 : LVL3

Channel Priority Level 3 (Highest Level)

End of enumeration elements list.


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL

Channel n Event Control
address_offset : 0xF76 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EVACT EVOMODE EVIE EVOE

EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)

Enumeration: EVACTSelect

0 : NOACT

No action

1 : TRIG

Transfer and periodic transfer trigger

2 : CTRIG

Conditional transfer trigger

3 : CBLOCK

Conditional block transfer

4 : SUSPEND

Channel suspend operation

5 : RESUME

Channel resume operation

6 : SSKIP

Skip next block suspend action

7 : INCPRI

Increase priority

End of enumeration elements list.

EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)

Enumeration: EVOMODESelect

0 : DEFAULT

Block event output selection. Refer to BTCTRL.EVOSEL for available selections.

1 : TRIGACT

Ongoing trigger action

End of enumeration elements list.

EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)

EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xF7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xF7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xF7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xF7F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xFC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENCLR11

Channel n Interrupt Enable Clear
address_offset : 0xFC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR11 CHINTENCLR11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xFD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHINTENSET11

Channel n Interrupt Enable Set
address_offset : 0xFD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET11 CHINTENSET11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xFE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHINTFLAG11

Channel n Interrupt Flag Status and Clear
address_offset : 0xFE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG11 CHINTFLAG11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TERR TCMPL SUSP

TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)

TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)

SUSP : Channel Suspend
bits : 2 - 2 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xFF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)

BUSY : Channel Busy
bits : 1 - 1 (1 bit)

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)


CHSTATUS11

Channel n Status
address_offset : 0xFF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS11 CHSTATUS11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PEND BUSY FERR CRCERR

PEND : Channel Pending
bits : 0 - 0 (1 bit)
access : read-only

BUSY : Channel Busy
bits : 1 - 1 (1 bit)
access : read-only

FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
access : read-only

CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)



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