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ITM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PORT_WORD_MODE[0]

PORT_BYTE_MODE[0]

PORT_HWORD_MODE[0]

PORT_BYTE_MODE0

PORT_HWORD_MODE0

PORT_WORD_MODE0

PORT_BYTE_MODE4

PORT_HWORD_MODE4

PORT_WORD_MODE4

PORT_WORD_MODE[11]

PORT_BYTE_MODE[11]

PORT_HWORD_MODE[11]

PORT_WORD_MODE[12]

PORT_BYTE_MODE[12]

PORT_HWORD_MODE[12]

PORT_BYTE_MODE5

PORT_HWORD_MODE5

PORT_WORD_MODE5

PORT_WORD_MODE[13]

PORT_BYTE_MODE[13]

PORT_HWORD_MODE[13]

PORT_WORD_MODE[3]

PORT_BYTE_MODE[3]

PORT_HWORD_MODE[3]

PORT_BYTE_MODE6

PORT_HWORD_MODE6

PORT_WORD_MODE6

PORT_WORD_MODE[14]

PORT_BYTE_MODE[14]

PORT_HWORD_MODE[14]

PORT_BYTE_MODE7

PORT_HWORD_MODE7

PORT_WORD_MODE7

PORT_WORD_MODE[15]

PORT_BYTE_MODE[15]

PORT_HWORD_MODE[15]

PORT_BYTE_MODE8

PORT_HWORD_MODE8

PORT_WORD_MODE8

PORT_WORD_MODE[16]

PORT_BYTE_MODE[16]

PORT_HWORD_MODE[16]

PORT_BYTE_MODE9

PORT_HWORD_MODE9

PORT_WORD_MODE9

PORT_WORD_MODE[17]

PORT_BYTE_MODE[17]

PORT_HWORD_MODE[17]

PORT_WORD_MODE[4]

PORT_BYTE_MODE[4]

PORT_HWORD_MODE[4]

PORT_BYTE_MODE10

PORT_HWORD_MODE10

PORT_WORD_MODE10

PORT_WORD_MODE[18]

PORT_BYTE_MODE[18]

PORT_HWORD_MODE[18]

PORT_BYTE_MODE11

PORT_HWORD_MODE11

PORT_WORD_MODE11

PORT_WORD_MODE[19]

PORT_BYTE_MODE[19]

PORT_HWORD_MODE[19]

PORT_BYTE_MODE12

PORT_HWORD_MODE12

PORT_WORD_MODE12

PORT_BYTE_MODE13

PORT_HWORD_MODE13

PORT_WORD_MODE13

PORT_WORD_MODE[20]

PORT_BYTE_MODE[20]

PORT_HWORD_MODE[20]

PORT_BYTE_MODE14

PORT_HWORD_MODE14

PORT_WORD_MODE14

PORT_WORD_MODE[21]

PORT_BYTE_MODE[21]

PORT_HWORD_MODE[21]

PORT_WORD_MODE[5]

PORT_BYTE_MODE[5]

PORT_HWORD_MODE[5]

PORT_BYTE_MODE15

PORT_HWORD_MODE15

PORT_WORD_MODE15

PORT_WORD_MODE[22]

PORT_BYTE_MODE[22]

PORT_HWORD_MODE[22]

PORT_WORD_MODE[1]

PORT_BYTE_MODE[1]

PORT_HWORD_MODE[1]

PORT_BYTE_MODE1

PORT_HWORD_MODE1

PORT_WORD_MODE1

PORT_BYTE_MODE16

PORT_HWORD_MODE16

PORT_WORD_MODE16

PORT_BYTE_MODE17

PORT_HWORD_MODE17

PORT_WORD_MODE17

PORT_WORD_MODE[23]

PORT_BYTE_MODE[23]

PORT_HWORD_MODE[23]

PORT_BYTE_MODE18

PORT_HWORD_MODE18

PORT_WORD_MODE18

PORT_WORD_MODE[24]

PORT_BYTE_MODE[24]

PORT_HWORD_MODE[24]

PORT_BYTE_MODE19

PORT_HWORD_MODE19

PORT_WORD_MODE19

PORT_BYTE_MODE20

PORT_HWORD_MODE20

PORT_WORD_MODE20

PORT_WORD_MODE[25]

PORT_BYTE_MODE[25]

PORT_HWORD_MODE[25]

PORT_WORD_MODE[6]

PORT_BYTE_MODE[6]

PORT_HWORD_MODE[6]

PORT_BYTE_MODE21

PORT_HWORD_MODE21

PORT_WORD_MODE21

PORT_WORD_MODE[26]

PORT_BYTE_MODE[26]

PORT_HWORD_MODE[26]

PORT_BYTE_MODE22

PORT_HWORD_MODE22

PORT_WORD_MODE22

PORT_BYTE_MODE23

PORT_HWORD_MODE23

PORT_WORD_MODE23

PORT_WORD_MODE[27]

PORT_BYTE_MODE[27]

PORT_HWORD_MODE[27]

PORT_BYTE_MODE24

PORT_HWORD_MODE24

PORT_WORD_MODE24

PORT_BYTE_MODE25

PORT_HWORD_MODE25

PORT_WORD_MODE25

PORT_WORD_MODE[28]

PORT_BYTE_MODE[28]

PORT_HWORD_MODE[28]

PORT_BYTE_MODE26

PORT_HWORD_MODE26

PORT_WORD_MODE26

PORT_BYTE_MODE27

PORT_HWORD_MODE27

PORT_WORD_MODE27

PORT_WORD_MODE[29]

PORT_BYTE_MODE[29]

PORT_HWORD_MODE[29]

PORT_WORD_MODE[7]

PORT_BYTE_MODE[7]

PORT_HWORD_MODE[7]

PORT_BYTE_MODE28

PORT_HWORD_MODE28

PORT_WORD_MODE28

PORT_BYTE_MODE29

PORT_HWORD_MODE29

PORT_WORD_MODE29

PORT_WORD_MODE[30]

PORT_BYTE_MODE[30]

PORT_HWORD_MODE[30]

PORT_BYTE_MODE30

PORT_HWORD_MODE30

PORT_WORD_MODE30

PORT_BYTE_MODE31

PORT_HWORD_MODE31

PORT_WORD_MODE31

PORT_WORD_MODE[31]

PORT_BYTE_MODE[31]

PORT_HWORD_MODE[31]

PORT_BYTE_MODE2

PORT_HWORD_MODE2

PORT_WORD_MODE2

PORT_WORD_MODE[8]

PORT_BYTE_MODE[8]

PORT_HWORD_MODE[8]

PORT_WORD_MODE[9]

PORT_BYTE_MODE[9]

PORT_HWORD_MODE[9]

PORT_WORD_MODE[2]

PORT_BYTE_MODE[2]

PORT_HWORD_MODE[2]

PORT_BYTE_MODE3

PORT_HWORD_MODE3

PORT_WORD_MODE3

PORT_WORD_MODE[10]

PORT_BYTE_MODE[10]

PORT_HWORD_MODE[10]

TER

TPR

TCR

IWR

IRR

PID4

PID5

PID6

PID7

PID0

PID1

PID2

PID3

CID0

CID1

CID2

CID3


PORT_WORD_MODE[0]

ITM Stimulus Port Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[0] PORT_WORD_MODE[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[0]

ITM Stimulus Port Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[0] PORT_BYTE_MODE[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[0]

ITM Stimulus Port Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[0] PORT_HWORD_MODE[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE0

ITM Stimulus Port Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE0 PORT_BYTE_MODE0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE0

ITM Stimulus Port Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE0 PORT_HWORD_MODE0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE0

ITM Stimulus Port Registers
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE0 PORT_WORD_MODE0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE4

ITM Stimulus Port Registers
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE4 PORT_BYTE_MODE4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE4

ITM Stimulus Port Registers
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE4 PORT_HWORD_MODE4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE4

ITM Stimulus Port Registers
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE4 PORT_WORD_MODE4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[11]

ITM Stimulus Port Registers
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[11] PORT_WORD_MODE[11] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[11]

ITM Stimulus Port Registers
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[11] PORT_BYTE_MODE[11] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[11]

ITM Stimulus Port Registers
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[11] PORT_HWORD_MODE[11] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[12]

ITM Stimulus Port Registers
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[12] PORT_WORD_MODE[12] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[12]

ITM Stimulus Port Registers
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[12] PORT_BYTE_MODE[12] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[12]

ITM Stimulus Port Registers
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[12] PORT_HWORD_MODE[12] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE5

ITM Stimulus Port Registers
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE5 PORT_BYTE_MODE5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE5

ITM Stimulus Port Registers
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE5 PORT_HWORD_MODE5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE5

ITM Stimulus Port Registers
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE5 PORT_WORD_MODE5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[13]

ITM Stimulus Port Registers
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[13] PORT_WORD_MODE[13] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[13]

ITM Stimulus Port Registers
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[13] PORT_BYTE_MODE[13] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[13]

ITM Stimulus Port Registers
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[13] PORT_HWORD_MODE[13] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[3]

ITM Stimulus Port Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[3] PORT_WORD_MODE[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[3]

ITM Stimulus Port Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[3] PORT_BYTE_MODE[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[3]

ITM Stimulus Port Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[3] PORT_HWORD_MODE[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE6

ITM Stimulus Port Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE6 PORT_BYTE_MODE6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE6

ITM Stimulus Port Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE6 PORT_HWORD_MODE6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE6

ITM Stimulus Port Registers
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE6 PORT_WORD_MODE6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[14]

ITM Stimulus Port Registers
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[14] PORT_WORD_MODE[14] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[14]

ITM Stimulus Port Registers
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[14] PORT_BYTE_MODE[14] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[14]

ITM Stimulus Port Registers
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[14] PORT_HWORD_MODE[14] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE7

ITM Stimulus Port Registers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE7 PORT_BYTE_MODE7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE7

ITM Stimulus Port Registers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE7 PORT_HWORD_MODE7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE7

ITM Stimulus Port Registers
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE7 PORT_WORD_MODE7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[15]

ITM Stimulus Port Registers
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[15] PORT_WORD_MODE[15] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[15]

ITM Stimulus Port Registers
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[15] PORT_BYTE_MODE[15] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[15]

ITM Stimulus Port Registers
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[15] PORT_HWORD_MODE[15] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE8

ITM Stimulus Port Registers
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE8 PORT_BYTE_MODE8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE8

ITM Stimulus Port Registers
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE8 PORT_HWORD_MODE8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE8

ITM Stimulus Port Registers
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE8 PORT_WORD_MODE8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[16]

ITM Stimulus Port Registers
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[16] PORT_WORD_MODE[16] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[16]

ITM Stimulus Port Registers
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[16] PORT_BYTE_MODE[16] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[16]

ITM Stimulus Port Registers
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[16] PORT_HWORD_MODE[16] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE9

ITM Stimulus Port Registers
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE9 PORT_BYTE_MODE9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE9

ITM Stimulus Port Registers
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE9 PORT_HWORD_MODE9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE9

ITM Stimulus Port Registers
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE9 PORT_WORD_MODE9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[17]

ITM Stimulus Port Registers
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[17] PORT_WORD_MODE[17] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[17]

ITM Stimulus Port Registers
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[17] PORT_BYTE_MODE[17] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[17]

ITM Stimulus Port Registers
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[17] PORT_HWORD_MODE[17] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[4]

ITM Stimulus Port Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[4] PORT_WORD_MODE[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[4]

ITM Stimulus Port Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[4] PORT_BYTE_MODE[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[4]

ITM Stimulus Port Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[4] PORT_HWORD_MODE[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE10

ITM Stimulus Port Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE10 PORT_BYTE_MODE10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE10

ITM Stimulus Port Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE10 PORT_HWORD_MODE10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE10

ITM Stimulus Port Registers
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE10 PORT_WORD_MODE10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[18]

ITM Stimulus Port Registers
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[18] PORT_WORD_MODE[18] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[18]

ITM Stimulus Port Registers
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[18] PORT_BYTE_MODE[18] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[18]

ITM Stimulus Port Registers
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[18] PORT_HWORD_MODE[18] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE11

ITM Stimulus Port Registers
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE11 PORT_BYTE_MODE11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE11

ITM Stimulus Port Registers
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE11 PORT_HWORD_MODE11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE11

ITM Stimulus Port Registers
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE11 PORT_WORD_MODE11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[19]

ITM Stimulus Port Registers
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[19] PORT_WORD_MODE[19] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[19]

ITM Stimulus Port Registers
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[19] PORT_BYTE_MODE[19] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[19]

ITM Stimulus Port Registers
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[19] PORT_HWORD_MODE[19] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE12

ITM Stimulus Port Registers
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE12 PORT_BYTE_MODE12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE12

ITM Stimulus Port Registers
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE12 PORT_HWORD_MODE12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE12

ITM Stimulus Port Registers
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE12 PORT_WORD_MODE12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE13

ITM Stimulus Port Registers
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE13 PORT_BYTE_MODE13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE13

ITM Stimulus Port Registers
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE13 PORT_HWORD_MODE13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE13

ITM Stimulus Port Registers
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE13 PORT_WORD_MODE13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[20]

ITM Stimulus Port Registers
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[20] PORT_WORD_MODE[20] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[20]

ITM Stimulus Port Registers
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[20] PORT_BYTE_MODE[20] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[20]

ITM Stimulus Port Registers
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[20] PORT_HWORD_MODE[20] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE14

ITM Stimulus Port Registers
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE14 PORT_BYTE_MODE14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE14

ITM Stimulus Port Registers
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE14 PORT_HWORD_MODE14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE14

ITM Stimulus Port Registers
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE14 PORT_WORD_MODE14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[21]

ITM Stimulus Port Registers
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[21] PORT_WORD_MODE[21] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[21]

ITM Stimulus Port Registers
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[21] PORT_BYTE_MODE[21] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[21]

ITM Stimulus Port Registers
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[21] PORT_HWORD_MODE[21] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[5]

ITM Stimulus Port Registers
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[5] PORT_WORD_MODE[5] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[5]

ITM Stimulus Port Registers
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[5] PORT_BYTE_MODE[5] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[5]

ITM Stimulus Port Registers
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[5] PORT_HWORD_MODE[5] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE15

ITM Stimulus Port Registers
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE15 PORT_BYTE_MODE15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE15

ITM Stimulus Port Registers
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE15 PORT_HWORD_MODE15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE15

ITM Stimulus Port Registers
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE15 PORT_WORD_MODE15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[22]

ITM Stimulus Port Registers
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[22] PORT_WORD_MODE[22] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[22]

ITM Stimulus Port Registers
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[22] PORT_BYTE_MODE[22] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[22]

ITM Stimulus Port Registers
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[22] PORT_HWORD_MODE[22] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[1]

ITM Stimulus Port Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[1] PORT_WORD_MODE[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[1]

ITM Stimulus Port Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[1] PORT_BYTE_MODE[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[1]

ITM Stimulus Port Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[1] PORT_HWORD_MODE[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE1

ITM Stimulus Port Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE1 PORT_BYTE_MODE1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE1

ITM Stimulus Port Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE1 PORT_HWORD_MODE1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE1

ITM Stimulus Port Registers
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE1 PORT_WORD_MODE1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE16

ITM Stimulus Port Registers
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE16 PORT_BYTE_MODE16 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE16

ITM Stimulus Port Registers
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE16 PORT_HWORD_MODE16 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE16

ITM Stimulus Port Registers
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE16 PORT_WORD_MODE16 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE17

ITM Stimulus Port Registers
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE17 PORT_BYTE_MODE17 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE17

ITM Stimulus Port Registers
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE17 PORT_HWORD_MODE17 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE17

ITM Stimulus Port Registers
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE17 PORT_WORD_MODE17 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[23]

ITM Stimulus Port Registers
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[23] PORT_WORD_MODE[23] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[23]

ITM Stimulus Port Registers
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[23] PORT_BYTE_MODE[23] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[23]

ITM Stimulus Port Registers
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[23] PORT_HWORD_MODE[23] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE18

ITM Stimulus Port Registers
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE18 PORT_BYTE_MODE18 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE18

ITM Stimulus Port Registers
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE18 PORT_HWORD_MODE18 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE18

ITM Stimulus Port Registers
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE18 PORT_WORD_MODE18 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[24]

ITM Stimulus Port Registers
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[24] PORT_WORD_MODE[24] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[24]

ITM Stimulus Port Registers
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[24] PORT_BYTE_MODE[24] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[24]

ITM Stimulus Port Registers
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[24] PORT_HWORD_MODE[24] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE19

ITM Stimulus Port Registers
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE19 PORT_BYTE_MODE19 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE19

ITM Stimulus Port Registers
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE19 PORT_HWORD_MODE19 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE19

ITM Stimulus Port Registers
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE19 PORT_WORD_MODE19 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE20

ITM Stimulus Port Registers
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE20 PORT_BYTE_MODE20 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE20

ITM Stimulus Port Registers
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE20 PORT_HWORD_MODE20 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE20

ITM Stimulus Port Registers
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE20 PORT_WORD_MODE20 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[25]

ITM Stimulus Port Registers
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[25] PORT_WORD_MODE[25] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[25]

ITM Stimulus Port Registers
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[25] PORT_BYTE_MODE[25] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[25]

ITM Stimulus Port Registers
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[25] PORT_HWORD_MODE[25] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[6]

ITM Stimulus Port Registers
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[6] PORT_WORD_MODE[6] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[6]

ITM Stimulus Port Registers
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[6] PORT_BYTE_MODE[6] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[6]

ITM Stimulus Port Registers
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[6] PORT_HWORD_MODE[6] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE21

ITM Stimulus Port Registers
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE21 PORT_BYTE_MODE21 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE21

ITM Stimulus Port Registers
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE21 PORT_HWORD_MODE21 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE21

ITM Stimulus Port Registers
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE21 PORT_WORD_MODE21 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[26]

ITM Stimulus Port Registers
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[26] PORT_WORD_MODE[26] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[26]

ITM Stimulus Port Registers
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[26] PORT_BYTE_MODE[26] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[26]

ITM Stimulus Port Registers
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[26] PORT_HWORD_MODE[26] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE22

ITM Stimulus Port Registers
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE22 PORT_BYTE_MODE22 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE22

ITM Stimulus Port Registers
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE22 PORT_HWORD_MODE22 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE22

ITM Stimulus Port Registers
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE22 PORT_WORD_MODE22 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE23

ITM Stimulus Port Registers
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE23 PORT_BYTE_MODE23 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE23

ITM Stimulus Port Registers
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE23 PORT_HWORD_MODE23 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE23

ITM Stimulus Port Registers
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE23 PORT_WORD_MODE23 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[27]

ITM Stimulus Port Registers
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[27] PORT_WORD_MODE[27] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[27]

ITM Stimulus Port Registers
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[27] PORT_BYTE_MODE[27] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[27]

ITM Stimulus Port Registers
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[27] PORT_HWORD_MODE[27] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE24

ITM Stimulus Port Registers
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE24 PORT_BYTE_MODE24 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE24

ITM Stimulus Port Registers
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE24 PORT_HWORD_MODE24 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE24

ITM Stimulus Port Registers
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE24 PORT_WORD_MODE24 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE25

ITM Stimulus Port Registers
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE25 PORT_BYTE_MODE25 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE25

ITM Stimulus Port Registers
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE25 PORT_HWORD_MODE25 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE25

ITM Stimulus Port Registers
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE25 PORT_WORD_MODE25 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[28]

ITM Stimulus Port Registers
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[28] PORT_WORD_MODE[28] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[28]

ITM Stimulus Port Registers
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[28] PORT_BYTE_MODE[28] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[28]

ITM Stimulus Port Registers
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[28] PORT_HWORD_MODE[28] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE26

ITM Stimulus Port Registers
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE26 PORT_BYTE_MODE26 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE26

ITM Stimulus Port Registers
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE26 PORT_HWORD_MODE26 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE26

ITM Stimulus Port Registers
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE26 PORT_WORD_MODE26 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE27

ITM Stimulus Port Registers
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE27 PORT_BYTE_MODE27 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE27

ITM Stimulus Port Registers
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE27 PORT_HWORD_MODE27 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE27

ITM Stimulus Port Registers
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE27 PORT_WORD_MODE27 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[29]

ITM Stimulus Port Registers
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[29] PORT_WORD_MODE[29] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[29]

ITM Stimulus Port Registers
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[29] PORT_BYTE_MODE[29] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[29]

ITM Stimulus Port Registers
address_offset : 0x6CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[29] PORT_HWORD_MODE[29] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[7]

ITM Stimulus Port Registers
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[7] PORT_WORD_MODE[7] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[7]

ITM Stimulus Port Registers
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[7] PORT_BYTE_MODE[7] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[7]

ITM Stimulus Port Registers
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[7] PORT_HWORD_MODE[7] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE28

ITM Stimulus Port Registers
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE28 PORT_BYTE_MODE28 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE28

ITM Stimulus Port Registers
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE28 PORT_HWORD_MODE28 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE28

ITM Stimulus Port Registers
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE28 PORT_WORD_MODE28 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE29

ITM Stimulus Port Registers
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE29 PORT_BYTE_MODE29 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE29

ITM Stimulus Port Registers
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE29 PORT_HWORD_MODE29 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE29

ITM Stimulus Port Registers
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE29 PORT_WORD_MODE29 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[30]

ITM Stimulus Port Registers
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[30] PORT_WORD_MODE[30] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[30]

ITM Stimulus Port Registers
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[30] PORT_BYTE_MODE[30] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[30]

ITM Stimulus Port Registers
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[30] PORT_HWORD_MODE[30] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE30

ITM Stimulus Port Registers
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE30 PORT_BYTE_MODE30 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE30

ITM Stimulus Port Registers
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE30 PORT_HWORD_MODE30 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE30

ITM Stimulus Port Registers
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE30 PORT_WORD_MODE30 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE31

ITM Stimulus Port Registers
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE31 PORT_BYTE_MODE31 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE31

ITM Stimulus Port Registers
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE31 PORT_HWORD_MODE31 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE31

ITM Stimulus Port Registers
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE31 PORT_WORD_MODE31 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[31]

ITM Stimulus Port Registers
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[31] PORT_WORD_MODE[31] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[31]

ITM Stimulus Port Registers
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[31] PORT_BYTE_MODE[31] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[31]

ITM Stimulus Port Registers
address_offset : 0x7C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[31] PORT_HWORD_MODE[31] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE2

ITM Stimulus Port Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE2 PORT_BYTE_MODE2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE2

ITM Stimulus Port Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE2 PORT_HWORD_MODE2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE2

ITM Stimulus Port Registers
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE2 PORT_WORD_MODE2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[8]

ITM Stimulus Port Registers
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[8] PORT_WORD_MODE[8] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[8]

ITM Stimulus Port Registers
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[8] PORT_BYTE_MODE[8] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[8]

ITM Stimulus Port Registers
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[8] PORT_HWORD_MODE[8] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[9]

ITM Stimulus Port Registers
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[9] PORT_WORD_MODE[9] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[9]

ITM Stimulus Port Registers
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[9] PORT_BYTE_MODE[9] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[9]

ITM Stimulus Port Registers
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[9] PORT_HWORD_MODE[9] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE[2]

ITM Stimulus Port Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[2] PORT_WORD_MODE[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[2]

ITM Stimulus Port Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[2] PORT_BYTE_MODE[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[2]

ITM Stimulus Port Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[2] PORT_HWORD_MODE[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_BYTE_MODE3

ITM Stimulus Port Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_BYTE_MODE3 PORT_BYTE_MODE3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE3

ITM Stimulus Port Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE3 PORT_HWORD_MODE3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


PORT_WORD_MODE3

ITM Stimulus Port Registers
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_BYTE_MODE[%s]
reset_Mask : 0x0

PORT_WORD_MODE3 PORT_WORD_MODE3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_WORD_MODE[10]

ITM Stimulus Port Registers
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PORT_WORD_MODE[10] PORT_WORD_MODE[10] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 31 (32 bit)


PORT_BYTE_MODE[10]

ITM Stimulus Port Registers
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_BYTE_MODE[10] PORT_BYTE_MODE[10] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 7 (8 bit)


PORT_HWORD_MODE[10]

ITM Stimulus Port Registers
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : PORT_WORD_MODE[%s]
reset_Mask : 0x0

PORT_HWORD_MODE[10] PORT_HWORD_MODE[10] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT

PORT :
bits : 0 - 15 (16 bit)


TER

ITM Trace Enable Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TER TER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TPR

ITM Trace Privilege Register
address_offset : 0xE40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIVMASK

PRIVMASK :
bits : 0 - 3 (4 bit)


TCR

ITM Trace Control Register
address_offset : 0xE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITMENA TSENA SYNCENA DWTENA SWOENA STALLENA TSPrescale GTSFREQ TraceBusID BUSY

ITMENA :
bits : 0 - 0 (1 bit)

TSENA :
bits : 1 - 1 (1 bit)

SYNCENA :
bits : 2 - 2 (1 bit)

DWTENA :
bits : 3 - 3 (1 bit)

SWOENA :
bits : 4 - 4 (1 bit)

STALLENA :
bits : 5 - 5 (1 bit)

TSPrescale :
bits : 8 - 9 (2 bit)

GTSFREQ :
bits : 10 - 11 (2 bit)

TraceBusID :
bits : 16 - 22 (7 bit)

BUSY :
bits : 23 - 23 (1 bit)


IWR

ITM Integration Write Register
address_offset : 0xEF8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IWR IWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATVALIDM

ATVALIDM :
bits : 0 - 0 (1 bit)


IRR

ITM Integration Read Register
address_offset : 0xEFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRR IRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATREADYM

ATREADYM :
bits : 0 - 0 (1 bit)


PID4

ITM Peripheral Identification Register #4
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID4 PID4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID5

ITM Peripheral Identification Register #5
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID5 PID5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID6

ITM Peripheral Identification Register #6
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID6 PID6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID7

ITM Peripheral Identification Register #7
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID7 PID7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID0

ITM Peripheral Identification Register #0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID0 PID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID1

ITM Peripheral Identification Register #1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID1 PID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID2

ITM Peripheral Identification Register #2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID2 PID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PID3

ITM Peripheral Identification Register #3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PID3 PID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CID0

ITM Component Identification Register #0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID0 CID0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CID1

ITM Component Identification Register #1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID1 CID1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CID2

ITM Component Identification Register #2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID2 CID2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CID3

ITM Component Identification Register #3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CID3 CID3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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