GCLK

Registers

CTRLA

PCHCTRL[0]

PCHCTRL32

CTRLA

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWRST : Software Reset
bits : 0 - 0 (1 bit)

PCHCTRL[0]

Peripheral Clock Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL32

Peripheral Clock Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL33

Peripheral Clock Control
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL34

Peripheral Clock Control
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL35

Peripheral Clock Control
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[23]

Peripheral Clock Control
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL36

Peripheral Clock Control
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL37

Peripheral Clock Control
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL38

Peripheral Clock Control
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[24]

Peripheral Clock Control
address_offset : 0x11B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[5]

Generic Clock Generator Control
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL39

Peripheral Clock Control
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL40

Peripheral Clock Control
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL41

Peripheral Clock Control
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL42

Peripheral Clock Control
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[25]

Peripheral Clock Control
address_offset : 0x1294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL43

Peripheral Clock Control
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL44

Peripheral Clock Control
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL45

Peripheral Clock Control
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[26]

Peripheral Clock Control
address_offset : 0x137C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL46

Peripheral Clock Control
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL47

Peripheral Clock Control
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[27]

Peripheral Clock Control
address_offset : 0x1468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[6]

Generic Clock Generator Control
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[28]

Peripheral Clock Control
address_offset : 0x1558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[29]

Peripheral Clock Control
address_offset : 0x164C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[30]

Peripheral Clock Control
address_offset : 0x1744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[1]

Peripheral Clock Control
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[31]

Peripheral Clock Control
address_offset : 0x1840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[7]

Generic Clock Generator Control
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[32]

Peripheral Clock Control
address_offset : 0x1940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[33]

Peripheral Clock Control
address_offset : 0x1A44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[34]

Peripheral Clock Control
address_offset : 0x1B4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[35]

Peripheral Clock Control
address_offset : 0x1C58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[8]

Generic Clock Generator Control
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[36]

Peripheral Clock Control
address_offset : 0x1D68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[37]

Peripheral Clock Control
address_offset : 0x1E7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[38]

Peripheral Clock Control
address_offset : 0x1F94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL0

Generic Clock Generator Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[39]

Peripheral Clock Control
address_offset : 0x20B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[2]

Peripheral Clock Control
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[9]

Generic Clock Generator Control
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[40]

Peripheral Clock Control
address_offset : 0x21D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[41]

Peripheral Clock Control
address_offset : 0x22F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL1

Generic Clock Generator Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[42]

Peripheral Clock Control
address_offset : 0x241C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[43]

Peripheral Clock Control
address_offset : 0x2548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[10]

Generic Clock Generator Control
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[44]

Peripheral Clock Control
address_offset : 0x2678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[45]

Peripheral Clock Control
address_offset : 0x27AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL2

Generic Clock Generator Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[46]

Peripheral Clock Control
address_offset : 0x28E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[3]

Peripheral Clock Control
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[47]

Peripheral Clock Control
address_offset : 0x2A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[11]

Generic Clock Generator Control
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

GENCTRL3

Generic Clock Generator Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

GENCTRL4

Generic Clock Generator Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[4]

Peripheral Clock Control
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL5

Generic Clock Generator Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

GENCTRL6

Generic Clock Generator Control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[5]

Peripheral Clock Control
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL7

Generic Clock Generator Control
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

SYNCBUSY

Synchronization Busy
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SWRST : Software Reset Synchroniation Busy bit
bits : 0 - 0 (1 bit)

GENCTRL : Generic Clock Generator Control n Synchronization Busy bits
bits : 2 - 13 (12 bit)

Enumeration: GENCTRLSelect

0x0001 : GCLK0

Generic clock generator 0

0x0002 : GCLK1

Generic clock generator 1

0x0004 : GCLK2

Generic clock generator 2

0x0008 : GCLK3

Generic clock generator 3

0x0010 : GCLK4

Generic clock generator 4

0x0020 : GCLK5

Generic clock generator 5

0x0040 : GCLK6

Generic clock generator 6

0x0080 : GCLK7

Generic clock generator 7

0x0100 : GCLK8

Generic clock generator 8

0x0200 : GCLK9

Generic clock generator 9

0x0400 : GCLK10

Generic clock generator 10

0x0800 : GCLK11

Generic clock generator 11

End of enumeration elements list.

GENCTRL[0]

Generic Clock Generator Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

GENCTRL8

Generic Clock Generator Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

GENCTRL9

Generic Clock Generator Control
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[6]

Peripheral Clock Control
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL10

Generic Clock Generator Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

GENCTRL11

Generic Clock Generator Control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[7]

Peripheral Clock Control
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[8]

Peripheral Clock Control
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[9]

Peripheral Clock Control
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[1]

Generic Clock Generator Control
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL[10]

Peripheral Clock Control
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[11]

Peripheral Clock Control
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL0

Peripheral Clock Control
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[12]

Peripheral Clock Control
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL1

Peripheral Clock Control
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL2

Peripheral Clock Control
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[2]

Generic Clock Generator Control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL3

Peripheral Clock Control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[13]

Peripheral Clock Control
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL4

Peripheral Clock Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL5

Peripheral Clock Control
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL6

Peripheral Clock Control
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[14]

Peripheral Clock Control
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL7

Peripheral Clock Control
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL8

Peripheral Clock Control
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL9

Peripheral Clock Control
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[15]

Peripheral Clock Control
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL10

Peripheral Clock Control
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL11

Peripheral Clock Control
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL12

Peripheral Clock Control
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[16]

Peripheral Clock Control
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL13

Peripheral Clock Control
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[3]

Generic Clock Generator Control
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL14

Peripheral Clock Control
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL15

Peripheral Clock Control
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[17]

Peripheral Clock Control
address_offset : 0xBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL16

Peripheral Clock Control
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL17

Peripheral Clock Control
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL18

Peripheral Clock Control
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[18]

Peripheral Clock Control
address_offset : 0xCAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL19

Peripheral Clock Control
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL20

Peripheral Clock Control
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL21

Peripheral Clock Control
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[19]

Peripheral Clock Control
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL22

Peripheral Clock Control
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL23

Peripheral Clock Control
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL24

Peripheral Clock Control
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL25

Peripheral Clock Control
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[20]

Peripheral Clock Control
address_offset : 0xE48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

GENCTRL[4]

Generic Clock Generator Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC : Source Select
bits : 0 - 3 (4 bit)

Enumeration: SRCSelect

0 : XOSC0

XOSC0 oscillator output

1 : XOSC1

XOSC1 oscillator output

2 : GCLKIN

Generator input pad

3 : GCLKGEN1

Generic clock generator 1 output

4 : OSCULP32K

OSCULP32K oscillator output

5 : XOSC32K

XOSC32K oscillator output

6 : DFLL

DFLL output

7 : DPLL0

DPLL0 output

8 : DPLL1

DPLL1 output

End of enumeration elements list.

GENEN : Generic Clock Generator Enable
bits : 8 - 8 (1 bit)

IDC : Improve Duty Cycle
bits : 9 - 9 (1 bit)

OOV : Output Off Value
bits : 10 - 10 (1 bit)

OE : Output Enable
bits : 11 - 11 (1 bit)

DIVSEL : Divide Selection
bits : 12 - 12 (1 bit)

Enumeration: DIVSELSelect

0x0 : DIV1

Divide input directly by divider factor

0x1 : DIV2

Divide input by 2^(divider factor+ 1)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 13 - 13 (1 bit)

DIV : Division Factor
bits : 16 - 31 (16 bit)

PCHCTRL26

Peripheral Clock Control
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL27

Peripheral Clock Control
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL28

Peripheral Clock Control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[21]

Peripheral Clock Control
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL29

Peripheral Clock Control
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL30

Peripheral Clock Control
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL31

Peripheral Clock Control
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

PCHCTRL[22]

Peripheral Clock Control
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GEN : Generic Clock Generator
bits : 0 - 3 (4 bit)

Enumeration: GENSelect

0x0 : GCLK0

Generic clock generator 0

0x1 : GCLK1

Generic clock generator 1

0x2 : GCLK2

Generic clock generator 2

0x3 : GCLK3

Generic clock generator 3

0x4 : GCLK4

Generic clock generator 4

0x5 : GCLK5

Generic clock generator 5

0x6 : GCLK6

Generic clock generator 6

0x7 : GCLK7

Generic clock generator 7

0x8 : GCLK8

Generic clock generator 8

0x9 : GCLK9

Generic clock generator 9

0xA : GCLK10

Generic clock generator 10

0xB : GCLK11

Generic clock generator 11

End of enumeration elements list.

CHEN : Channel Enable
bits : 6 - 6 (1 bit)

WRTLOCK : Write Lock
bits : 7 - 7 (1 bit)

Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by

Embeetle, an IDE designed from scratch for embedded software developers.

ChipSelect

GCLK

Peripheral Memory Blocks

Registers

CTRLA

PCHCTRL[0]

PCHCTRL32

PCHCTRL33

PCHCTRL34

PCHCTRL35

PCHCTRL[23]

PCHCTRL36

PCHCTRL37

PCHCTRL38

PCHCTRL[24]

GENCTRL[5]

PCHCTRL39

PCHCTRL40

PCHCTRL41

PCHCTRL42

PCHCTRL[25]

PCHCTRL43

PCHCTRL44

PCHCTRL45

PCHCTRL[26]

PCHCTRL46

PCHCTRL47

PCHCTRL[27]

GENCTRL[6]

PCHCTRL[28]

PCHCTRL[29]

PCHCTRL[30]

PCHCTRL[1]

PCHCTRL[31]

GENCTRL[7]

PCHCTRL[32]

PCHCTRL[33]

PCHCTRL[34]

PCHCTRL[35]

GENCTRL[8]

PCHCTRL[36]

PCHCTRL[37]

PCHCTRL[38]

GENCTRL0

PCHCTRL[39]

PCHCTRL[2]

GENCTRL[9]

PCHCTRL[40]

PCHCTRL[41]

GENCTRL1

PCHCTRL[42]

PCHCTRL[43]

GENCTRL[10]

PCHCTRL[44]

PCHCTRL[45]

GENCTRL2

PCHCTRL[46]

PCHCTRL[3]

PCHCTRL[47]

GENCTRL[11]

GENCTRL3

GENCTRL4

PCHCTRL[4]

GENCTRL5

GENCTRL6

PCHCTRL[5]

GENCTRL7

SYNCBUSY

GENCTRL[0]

GENCTRL8

GENCTRL9

PCHCTRL[6]

GENCTRL10

GENCTRL11

PCHCTRL[7]

PCHCTRL[8]

PCHCTRL[9]

GENCTRL[1]

PCHCTRL[10]

PCHCTRL[11]