Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :
Event Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFDEO0 : Clock 0 Failure Detector Event Output Enable
bits : 0 - 0 (1 bit)
CFDEO1 : Clock 1 Failure Detector Event Output Enable
bits : 1 - 1 (1 bit)
DPLL Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XOSCRDY0 : XOSC 0 Ready
bits : 0 - 0 (1 bit)
XOSCRDY1 : XOSC 1 Ready
bits : 1 - 1 (1 bit)
XOSCFAIL0 : XOSC 0 Clock Failure Detector
bits : 2 - 2 (1 bit)
XOSCFAIL1 : XOSC 1 Clock Failure Detector
bits : 3 - 3 (1 bit)
XOSCCKSW0 : XOSC 0 Clock Switch
bits : 4 - 4 (1 bit)
XOSCCKSW1 : XOSC 1 Clock Switch
bits : 5 - 5 (1 bit)
DFLLRDY : DFLL Ready
bits : 8 - 8 (1 bit)
DFLLOOB : DFLL Out Of Bounds
bits : 9 - 9 (1 bit)
DFLLLCKF : DFLL Lock Fine
bits : 10 - 10 (1 bit)
DFLLLCKC : DFLL Lock Coarse
bits : 11 - 11 (1 bit)
DFLLRCS : DFLL Reference Clock Stopped
bits : 12 - 12 (1 bit)
DPLL0LCKR : DPLL0 Lock Rise
bits : 16 - 16 (1 bit)
DPLL0LCKF : DPLL0 Lock Fall
bits : 17 - 17 (1 bit)
DPLL0TO : DPLL0 Timeout
bits : 18 - 18 (1 bit)
DPLL0LDRTO : DPLL0 Loop Divider Ratio Update Complete
bits : 19 - 19 (1 bit)
DPLL1LCKR : DPLL1 Lock Rise
bits : 24 - 24 (1 bit)
DPLL1LCKF : DPLL1 Lock Fall
bits : 25 - 25 (1 bit)
DPLL1TO : DPLL1 Timeout
bits : 26 - 26 (1 bit)
DPLL1LDRTO : DPLL1 Loop Divider Ratio Update Complete
bits : 27 - 27 (1 bit)
DPLL Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCK : DPLL Lock Status
bits : 0 - 0 (1 bit)
CLKRDY : DPLL Clock Ready
bits : 1 - 1 (1 bit)
External Multipurpose Crystal Oscillator Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)
XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
LOWBUFGAIN : Low Buffer Gain Enable
bits : 8 - 8 (1 bit)
IPTAT : Oscillator Current Reference
bits : 9 - 10 (2 bit)
IMULT : Oscillator Current Multiplier
bits : 11 - 14 (4 bit)
ENALC : Automatic Loop Control Enable
bits : 15 - 15 (1 bit)
CFDEN : Clock Failure Detector Enable
bits : 16 - 16 (1 bit)
SWBEN : Xosc Clock Switch Enable
bits : 17 - 17 (1 bit)
STARTUP : Start-Up Time
bits : 20 - 23 (4 bit)
Enumeration: STARTUPSelect
0 : CYCLE1
31 us
1 : CYCLE2
61 us
2 : CYCLE4
122 us
3 : CYCLE8
244 us
4 : CYCLE16
488 us
5 : CYCLE32
977 us
6 : CYCLE64
1953 us
7 : CYCLE128
3906 us
8 : CYCLE256
7813 us
9 : CYCLE512
15625 us
10 : CYCLE1024
31250 us
11 : CYCLE2048
62500 us
12 : CYCLE4096
125000 us
13 : CYCLE8192
250000 us
14 : CYCLE16384
500000 us
15 : CYCLE32768
1000000 us
End of enumeration elements list.
CFDPRESC : Clock Failure Detector Prescaler
bits : 24 - 27 (4 bit)
Enumeration: CFDPRESCSelect
0 : DIV1
48 MHz
1 : DIV2
24 MHz
2 : DIV4
12 MHz
3 : DIV8
6 MHz
4 : DIV16
3 MHz
5 : DIV32
1.5 MHz
6 : DIV64
0.75 MHz
7 : DIV128
0.3125 MHz
End of enumeration elements list.
External Multipurpose Crystal Oscillator Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)
XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
LOWBUFGAIN : Low Buffer Gain Enable
bits : 8 - 8 (1 bit)
IPTAT : Oscillator Current Reference
bits : 9 - 10 (2 bit)
IMULT : Oscillator Current Multiplier
bits : 11 - 14 (4 bit)
ENALC : Automatic Loop Control Enable
bits : 15 - 15 (1 bit)
CFDEN : Clock Failure Detector Enable
bits : 16 - 16 (1 bit)
SWBEN : Xosc Clock Switch Enable
bits : 17 - 17 (1 bit)
STARTUP : Start-Up Time
bits : 20 - 23 (4 bit)
Enumeration: STARTUPSelect
0 : CYCLE1
31 us
1 : CYCLE2
61 us
2 : CYCLE4
122 us
3 : CYCLE8
244 us
4 : CYCLE16
488 us
5 : CYCLE32
977 us
6 : CYCLE64
1953 us
7 : CYCLE128
3906 us
8 : CYCLE256
7813 us
9 : CYCLE512
15625 us
10 : CYCLE1024
31250 us
11 : CYCLE2048
62500 us
12 : CYCLE4096
125000 us
13 : CYCLE8192
250000 us
14 : CYCLE16384
500000 us
15 : CYCLE32768
1000000 us
End of enumeration elements list.
CFDPRESC : Clock Failure Detector Prescaler
bits : 24 - 27 (4 bit)
Enumeration: CFDPRESCSelect
0 : DIV1
48 MHz
1 : DIV2
24 MHz
2 : DIV4
12 MHz
3 : DIV8
6 MHz
4 : DIV16
3 MHz
5 : DIV32
1.5 MHz
6 : DIV64
0.75 MHz
7 : DIV128
0.3125 MHz
End of enumeration elements list.
DFLL48M Control A
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DFLL Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
DFLL48M Control B
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Operating Mode Selection
bits : 0 - 0 (1 bit)
STABLE : Stable DFLL Frequency
bits : 1 - 1 (1 bit)
LLAW : Lose Lock After Wake
bits : 2 - 2 (1 bit)
USBCRM : USB Clock Recovery Mode
bits : 3 - 3 (1 bit)
CCDIS : Chill Cycle Disable
bits : 4 - 4 (1 bit)
QLDIS : Quick Lock Disable
bits : 5 - 5 (1 bit)
BPLCKC : Bypass Coarse Lock
bits : 6 - 6 (1 bit)
WAITLOCK : Wait Lock
bits : 7 - 7 (1 bit)
DFLL48M Value
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINE : Fine Value
bits : 0 - 7 (8 bit)
COARSE : Coarse Value
bits : 10 - 15 (6 bit)
DIFF : Multiplication Ratio Difference
bits : 16 - 31 (16 bit)
External Multipurpose Crystal Oscillator Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)
XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
LOWBUFGAIN : Low Buffer Gain Enable
bits : 8 - 8 (1 bit)
IPTAT : Oscillator Current Reference
bits : 9 - 10 (2 bit)
IMULT : Oscillator Current Multiplier
bits : 11 - 14 (4 bit)
ENALC : Automatic Loop Control Enable
bits : 15 - 15 (1 bit)
CFDEN : Clock Failure Detector Enable
bits : 16 - 16 (1 bit)
SWBEN : Xosc Clock Switch Enable
bits : 17 - 17 (1 bit)
STARTUP : Start-Up Time
bits : 20 - 23 (4 bit)
Enumeration: STARTUPSelect
0 : CYCLE1
31 us
1 : CYCLE2
61 us
2 : CYCLE4
122 us
3 : CYCLE8
244 us
4 : CYCLE16
488 us
5 : CYCLE32
977 us
6 : CYCLE64
1953 us
7 : CYCLE128
3906 us
8 : CYCLE256
7813 us
9 : CYCLE512
15625 us
10 : CYCLE1024
31250 us
11 : CYCLE2048
62500 us
12 : CYCLE4096
125000 us
13 : CYCLE8192
250000 us
14 : CYCLE16384
500000 us
15 : CYCLE32768
1000000 us
End of enumeration elements list.
CFDPRESC : Clock Failure Detector Prescaler
bits : 24 - 27 (4 bit)
Enumeration: CFDPRESCSelect
0 : DIV1
48 MHz
1 : DIV2
24 MHz
2 : DIV4
12 MHz
3 : DIV8
6 MHz
4 : DIV16
3 MHz
5 : DIV32
1.5 MHz
6 : DIV64
0.75 MHz
7 : DIV128
0.3125 MHz
End of enumeration elements list.
DFLL48M Multiplier
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUL : DFLL Multiply Factor
bits : 0 - 15 (16 bit)
FSTEP : Fine Maximum Step
bits : 16 - 23 (8 bit)
CSTEP : Coarse Maximum Step
bits : 26 - 31 (6 bit)
DFLL48M Synchronization
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : ENABLE Synchronization Busy
bits : 1 - 1 (1 bit)
DFLLCTRLB : DFLLCTRLB Synchronization Busy
bits : 2 - 2 (1 bit)
DFLLVAL : DFLLVAL Synchronization Busy
bits : 3 - 3 (1 bit)
DFLLMUL : DFLLMUL Synchronization Busy
bits : 4 - 4 (1 bit)
DPLL Control A
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
DPLL Control A
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
DPLL Ratio Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDR : Loop Divider Ratio
bits : 0 - 12 (13 bit)
LDRFRAC : Loop Divider Ratio Fractional Part
bits : 16 - 20 (5 bit)
DPLL Ratio Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDR : Loop Divider Ratio
bits : 0 - 12 (13 bit)
LDRFRAC : Loop Divider Ratio Fractional Part
bits : 16 - 20 (5 bit)
DPLL Control B
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Proportional Integral Filter Selection
bits : 0 - 3 (4 bit)
Enumeration: FILTERSelect
0 : FILTER1
Bandwidth = 92.7Khz and Damping Factor = 0.76
1 : FILTER2
Bandwidth = 131Khz and Damping Factor = 1.08
2 : FILTER3
Bandwidth = 46.4Khz and Damping Factor = 0.38
3 : FILTER4
Bandwidth = 65.6Khz and Damping Factor = 0.54
4 : FILTER5
Bandwidth = 131Khz and Damping Factor = 0.56
5 : FILTER6
Bandwidth = 185Khz and Damping Factor = 0.79
6 : FILTER7
Bandwidth = 65.6Khz and Damping Factor = 0.28
7 : FILTER8
Bandwidth = 92.7Khz and Damping Factor = 0.39
8 : FILTER9
Bandwidth = 46.4Khz and Damping Factor = 1.49
9 : FILTER10
Bandwidth = 65.6Khz and Damping Factor = 2.11
10 : FILTER11
Bandwidth = 23.2Khz and Damping Factor = 0.75
11 : FILTER12
Bandwidth = 32.8Khz and Damping Factor = 1.06
12 : FILTER13
Bandwidth = 65.6Khz and Damping Factor = 1.07
13 : FILTER14
Bandwidth = 92.7Khz and Damping Factor = 1.51
14 : FILTER15
Bandwidth = 32.8Khz and Damping Factor = 0.53
15 : FILTER16
Bandwidth = 46.4Khz and Damping Factor = 0.75
End of enumeration elements list.
WUF : Wake Up Fast
bits : 4 - 4 (1 bit)
REFCLK : Reference Clock Selection
bits : 5 - 7 (3 bit)
Enumeration: REFCLKSelect
0x0 : GCLK
Dedicated GCLK clock reference
0x1 : XOSC32
XOSC32K clock reference
0x2 : XOSC0
XOSC0 clock reference
0x3 : XOSC1
XOSC1 clock reference
End of enumeration elements list.
LTIME : Lock Time
bits : 8 - 10 (3 bit)
Enumeration: LTIMESelect
0x0 : DEFAULT
No time-out. Automatic lock
0x4 : 800US
Time-out if no lock within 800us
0x5 : 900US
Time-out if no lock within 900us
0x6 : 1MS
Time-out if no lock within 1ms
0x7 : 1P1MS
Time-out if no lock within 1.1ms
End of enumeration elements list.
LBYPASS : Lock Bypass
bits : 11 - 11 (1 bit)
DCOFILTER : Sigma-Delta DCO Filter Selection
bits : 12 - 14 (3 bit)
Enumeration: DCOFILTERSelect
0 : FILTER1
Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21
1 : FILTER2
Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6
2 : FILTER3
Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1
3 : FILTER4
Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8
4 : FILTER5
Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64
5 : FILTER6
Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55
6 : FILTER7
Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45
7 : FILTER8
Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4
End of enumeration elements list.
DCOEN : DCO Filter Enable
bits : 15 - 15 (1 bit)
DIV : Clock Divider
bits : 16 - 26 (11 bit)
DPLL Control B
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Proportional Integral Filter Selection
bits : 0 - 3 (4 bit)
WUF : Wake Up Fast
bits : 4 - 4 (1 bit)
REFCLK : Reference Clock Selection
bits : 5 - 7 (3 bit)
Enumeration: REFCLKSelect
0x0 : GCLK
Dedicated GCLK clock reference
0x1 : XOSC32
XOSC32K clock reference
0x2 : XOSC0
XOSC0 clock reference
0x3 : XOSC1
XOSC1 clock reference
End of enumeration elements list.
LTIME : Lock Time
bits : 8 - 10 (3 bit)
Enumeration: LTIMESelect
0x0 : DEFAULT
No time-out. Automatic lock
0x4 : 800US
Time-out if no lock within 800us
0x5 : 900US
Time-out if no lock within 900us
0x6 : 1MS
Time-out if no lock within 1ms
0x7 : 1P1MS
Time-out if no lock within 1.1ms
End of enumeration elements list.
LBYPASS : Lock Bypass
bits : 11 - 11 (1 bit)
DCOFILTER : Sigma-Delta DCO Filter Selection
bits : 12 - 14 (3 bit)
DCOEN : DCO Filter Enable
bits : 15 - 15 (1 bit)
DIV : Clock Divider
bits : 16 - 26 (11 bit)
DPLL Synchronization Busy
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable Synchronization Status
bits : 1 - 1 (1 bit)
DPLLRATIO : DPLL Loop Divider Ratio Synchronization Status
bits : 2 - 2 (1 bit)
DPLL Synchronization Busy
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable Synchronization Status
bits : 1 - 1 (1 bit)
access : read-only
DPLLRATIO : DPLL Loop Divider Ratio Synchronization Status
bits : 2 - 2 (1 bit)
access : read-only
Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOSCRDY0 : XOSC 0 Ready Interrupt Enable
bits : 0 - 0 (1 bit)
XOSCRDY1 : XOSC 1 Ready Interrupt Enable
bits : 1 - 1 (1 bit)
XOSCFAIL0 : XOSC 0 Clock Failure Detector Interrupt Enable
bits : 2 - 2 (1 bit)
XOSCFAIL1 : XOSC 1 Clock Failure Detector Interrupt Enable
bits : 3 - 3 (1 bit)
DFLLRDY : DFLL Ready Interrupt Enable
bits : 8 - 8 (1 bit)
DFLLOOB : DFLL Out Of Bounds Interrupt Enable
bits : 9 - 9 (1 bit)
DFLLLCKF : DFLL Lock Fine Interrupt Enable
bits : 10 - 10 (1 bit)
DFLLLCKC : DFLL Lock Coarse Interrupt Enable
bits : 11 - 11 (1 bit)
DFLLRCS : DFLL Reference Clock Stopped Interrupt Enable
bits : 12 - 12 (1 bit)
DPLL0LCKR : DPLL0 Lock Rise Interrupt Enable
bits : 16 - 16 (1 bit)
DPLL0LCKF : DPLL0 Lock Fall Interrupt Enable
bits : 17 - 17 (1 bit)
DPLL0LTO : DPLL0 Lock Timeout Interrupt Enable
bits : 18 - 18 (1 bit)
DPLL0LDRTO : DPLL0 Loop Divider Ratio Update Complete Interrupt Enable
bits : 19 - 19 (1 bit)
DPLL1LCKR : DPLL1 Lock Rise Interrupt Enable
bits : 24 - 24 (1 bit)
DPLL1LCKF : DPLL1 Lock Fall Interrupt Enable
bits : 25 - 25 (1 bit)
DPLL1LTO : DPLL1 Lock Timeout Interrupt Enable
bits : 26 - 26 (1 bit)
DPLL1LDRTO : DPLL1 Loop Divider Ratio Update Complete Interrupt Enable
bits : 27 - 27 (1 bit)
DPLL Ratio Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDR : Loop Divider Ratio
bits : 0 - 12 (13 bit)
LDRFRAC : Loop Divider Ratio Fractional Part
bits : 16 - 20 (5 bit)
External Multipurpose Crystal Oscillator Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Oscillator Enable
bits : 1 - 1 (1 bit)
XTALEN : Crystal Oscillator Enable
bits : 2 - 2 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
LOWBUFGAIN : Low Buffer Gain Enable
bits : 8 - 8 (1 bit)
IPTAT : Oscillator Current Reference
bits : 9 - 10 (2 bit)
IMULT : Oscillator Current Multiplier
bits : 11 - 14 (4 bit)
ENALC : Automatic Loop Control Enable
bits : 15 - 15 (1 bit)
CFDEN : Clock Failure Detector Enable
bits : 16 - 16 (1 bit)
SWBEN : Xosc Clock Switch Enable
bits : 17 - 17 (1 bit)
STARTUP : Start-Up Time
bits : 20 - 23 (4 bit)
Enumeration: STARTUPSelect
0 : CYCLE1
31 us
1 : CYCLE2
61 us
2 : CYCLE4
122 us
3 : CYCLE8
244 us
4 : CYCLE16
488 us
5 : CYCLE32
977 us
6 : CYCLE64
1953 us
7 : CYCLE128
3906 us
8 : CYCLE256
7813 us
9 : CYCLE512
15625 us
10 : CYCLE1024
31250 us
11 : CYCLE2048
62500 us
12 : CYCLE4096
125000 us
13 : CYCLE8192
250000 us
14 : CYCLE16384
500000 us
15 : CYCLE32768
1000000 us
End of enumeration elements list.
CFDPRESC : Clock Failure Detector Prescaler
bits : 24 - 27 (4 bit)
Enumeration: CFDPRESCSelect
0 : DIV1
48 MHz
1 : DIV2
24 MHz
2 : DIV4
12 MHz
3 : DIV8
6 MHz
4 : DIV16
3 MHz
5 : DIV32
1.5 MHz
6 : DIV64
0.75 MHz
7 : DIV128
0.3125 MHz
End of enumeration elements list.
DPLL Status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCK : DPLL Lock Status
bits : 0 - 0 (1 bit)
CLKRDY : DPLL Clock Ready
bits : 1 - 1 (1 bit)
DPLL Status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCK : DPLL Lock Status
bits : 0 - 0 (1 bit)
access : read-only
CLKRDY : DPLL Clock Ready
bits : 1 - 1 (1 bit)
access : read-only
DPLL Control A
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
DPLL Ratio Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDR : Loop Divider Ratio
bits : 0 - 12 (13 bit)
LDRFRAC : Loop Divider Ratio Fractional Part
bits : 16 - 20 (5 bit)
DPLL Control B
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Proportional Integral Filter Selection
bits : 0 - 3 (4 bit)
WUF : Wake Up Fast
bits : 4 - 4 (1 bit)
REFCLK : Reference Clock Selection
bits : 5 - 7 (3 bit)
Enumeration: REFCLKSelect
0x0 : GCLK
Dedicated GCLK clock reference
0x1 : XOSC32
XOSC32K clock reference
0x2 : XOSC0
XOSC0 clock reference
0x3 : XOSC1
XOSC1 clock reference
End of enumeration elements list.
LTIME : Lock Time
bits : 8 - 10 (3 bit)
Enumeration: LTIMESelect
0x0 : DEFAULT
No time-out. Automatic lock
0x4 : 800US
Time-out if no lock within 800us
0x5 : 900US
Time-out if no lock within 900us
0x6 : 1MS
Time-out if no lock within 1ms
0x7 : 1P1MS
Time-out if no lock within 1.1ms
End of enumeration elements list.
LBYPASS : Lock Bypass
bits : 11 - 11 (1 bit)
DCOFILTER : Sigma-Delta DCO Filter Selection
bits : 12 - 14 (3 bit)
DCOEN : DCO Filter Enable
bits : 15 - 15 (1 bit)
DIV : Clock Divider
bits : 16 - 26 (11 bit)
DPLL Synchronization Busy
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable Synchronization Status
bits : 1 - 1 (1 bit)
access : read-only
DPLLRATIO : DPLL Loop Divider Ratio Synchronization Status
bits : 2 - 2 (1 bit)
access : read-only
DPLL Status
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCK : DPLL Lock Status
bits : 0 - 0 (1 bit)
access : read-only
CLKRDY : DPLL Clock Ready
bits : 1 - 1 (1 bit)
access : read-only
DPLL Control A
address_offset : 0x74 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
DPLL Ratio Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LDR : Loop Divider Ratio
bits : 0 - 12 (13 bit)
LDRFRAC : Loop Divider Ratio Fractional Part
bits : 16 - 20 (5 bit)
DPLL Control B
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Proportional Integral Filter Selection
bits : 0 - 3 (4 bit)
Enumeration: FILTERSelect
0 : FILTER1
Bandwidth = 92.7Khz and Damping Factor = 0.76
1 : FILTER2
Bandwidth = 131Khz and Damping Factor = 1.08
2 : FILTER3
Bandwidth = 46.4Khz and Damping Factor = 0.38
3 : FILTER4
Bandwidth = 65.6Khz and Damping Factor = 0.54
4 : FILTER5
Bandwidth = 131Khz and Damping Factor = 0.56
5 : FILTER6
Bandwidth = 185Khz and Damping Factor = 0.79
6 : FILTER7
Bandwidth = 65.6Khz and Damping Factor = 0.28
7 : FILTER8
Bandwidth = 92.7Khz and Damping Factor = 0.39
8 : FILTER9
Bandwidth = 46.4Khz and Damping Factor = 1.49
9 : FILTER10
Bandwidth = 65.6Khz and Damping Factor = 2.11
10 : FILTER11
Bandwidth = 23.2Khz and Damping Factor = 0.75
11 : FILTER12
Bandwidth = 32.8Khz and Damping Factor = 1.06
12 : FILTER13
Bandwidth = 65.6Khz and Damping Factor = 1.07
13 : FILTER14
Bandwidth = 92.7Khz and Damping Factor = 1.51
14 : FILTER15
Bandwidth = 32.8Khz and Damping Factor = 0.53
15 : FILTER16
Bandwidth = 46.4Khz and Damping Factor = 0.75
End of enumeration elements list.
WUF : Wake Up Fast
bits : 4 - 4 (1 bit)
REFCLK : Reference Clock Selection
bits : 5 - 7 (3 bit)
Enumeration: REFCLKSelect
0x0 : GCLK
Dedicated GCLK clock reference
0x1 : XOSC32
XOSC32K clock reference
0x2 : XOSC0
XOSC0 clock reference
0x3 : XOSC1
XOSC1 clock reference
End of enumeration elements list.
LTIME : Lock Time
bits : 8 - 10 (3 bit)
Enumeration: LTIMESelect
0x0 : DEFAULT
No time-out. Automatic lock
0x4 : 800US
Time-out if no lock within 800us
0x5 : 900US
Time-out if no lock within 900us
0x6 : 1MS
Time-out if no lock within 1ms
0x7 : 1P1MS
Time-out if no lock within 1.1ms
End of enumeration elements list.
LBYPASS : Lock Bypass
bits : 11 - 11 (1 bit)
DCOFILTER : Sigma-Delta DCO Filter Selection
bits : 12 - 14 (3 bit)
Enumeration: DCOFILTERSelect
0 : FILTER1
Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21
1 : FILTER2
Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6
2 : FILTER3
Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1
3 : FILTER4
Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8
4 : FILTER5
Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64
5 : FILTER6
Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55
6 : FILTER7
Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45
7 : FILTER8
Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4
End of enumeration elements list.
DCOEN : DCO Filter Enable
bits : 15 - 15 (1 bit)
DIV : Clock Divider
bits : 16 - 26 (11 bit)
Interrupt Enable Set
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOSCRDY0 : XOSC 0 Ready Interrupt Enable
bits : 0 - 0 (1 bit)
XOSCRDY1 : XOSC 1 Ready Interrupt Enable
bits : 1 - 1 (1 bit)
XOSCFAIL0 : XOSC 0 Clock Failure Detector Interrupt Enable
bits : 2 - 2 (1 bit)
XOSCFAIL1 : XOSC 1 Clock Failure Detector Interrupt Enable
bits : 3 - 3 (1 bit)
DFLLRDY : DFLL Ready Interrupt Enable
bits : 8 - 8 (1 bit)
DFLLOOB : DFLL Out Of Bounds Interrupt Enable
bits : 9 - 9 (1 bit)
DFLLLCKF : DFLL Lock Fine Interrupt Enable
bits : 10 - 10 (1 bit)
DFLLLCKC : DFLL Lock Coarse Interrupt Enable
bits : 11 - 11 (1 bit)
DFLLRCS : DFLL Reference Clock Stopped Interrupt Enable
bits : 12 - 12 (1 bit)
DPLL0LCKR : DPLL0 Lock Rise Interrupt Enable
bits : 16 - 16 (1 bit)
DPLL0LCKF : DPLL0 Lock Fall Interrupt Enable
bits : 17 - 17 (1 bit)
DPLL0LTO : DPLL0 Lock Timeout Interrupt Enable
bits : 18 - 18 (1 bit)
DPLL0LDRTO : DPLL0 Loop Divider Ratio Update Complete Interrupt Enable
bits : 19 - 19 (1 bit)
DPLL1LCKR : DPLL1 Lock Rise Interrupt Enable
bits : 24 - 24 (1 bit)
DPLL1LCKF : DPLL1 Lock Fall Interrupt Enable
bits : 25 - 25 (1 bit)
DPLL1LTO : DPLL1 Lock Timeout Interrupt Enable
bits : 26 - 26 (1 bit)
DPLL1LDRTO : DPLL1 Loop Divider Ratio Update Complete Interrupt Enable
bits : 27 - 27 (1 bit)
DPLL Control B
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER : Proportional Integral Filter Selection
bits : 0 - 3 (4 bit)
Enumeration: FILTERSelect
0 : FILTER1
Bandwidth = 92.7Khz and Damping Factor = 0.76
1 : FILTER2
Bandwidth = 131Khz and Damping Factor = 1.08
2 : FILTER3
Bandwidth = 46.4Khz and Damping Factor = 0.38
3 : FILTER4
Bandwidth = 65.6Khz and Damping Factor = 0.54
4 : FILTER5
Bandwidth = 131Khz and Damping Factor = 0.56
5 : FILTER6
Bandwidth = 185Khz and Damping Factor = 0.79
6 : FILTER7
Bandwidth = 65.6Khz and Damping Factor = 0.28
7 : FILTER8
Bandwidth = 92.7Khz and Damping Factor = 0.39
8 : FILTER9
Bandwidth = 46.4Khz and Damping Factor = 1.49
9 : FILTER10
Bandwidth = 65.6Khz and Damping Factor = 2.11
10 : FILTER11
Bandwidth = 23.2Khz and Damping Factor = 0.75
11 : FILTER12
Bandwidth = 32.8Khz and Damping Factor = 1.06
12 : FILTER13
Bandwidth = 65.6Khz and Damping Factor = 1.07
13 : FILTER14
Bandwidth = 92.7Khz and Damping Factor = 1.51
14 : FILTER15
Bandwidth = 32.8Khz and Damping Factor = 0.53
15 : FILTER16
Bandwidth = 46.4Khz and Damping Factor = 0.75
End of enumeration elements list.
WUF : Wake Up Fast
bits : 4 - 4 (1 bit)
REFCLK : Reference Clock Selection
bits : 5 - 7 (3 bit)
Enumeration: REFCLKSelect
0x0 : GCLK
Dedicated GCLK clock reference
0x1 : XOSC32
XOSC32K clock reference
0x2 : XOSC0
XOSC0 clock reference
0x3 : XOSC1
XOSC1 clock reference
End of enumeration elements list.
LTIME : Lock Time
bits : 8 - 10 (3 bit)
Enumeration: LTIMESelect
0x0 : DEFAULT
No time-out. Automatic lock
0x4 : 800US
Time-out if no lock within 800us
0x5 : 900US
Time-out if no lock within 900us
0x6 : 1MS
Time-out if no lock within 1ms
0x7 : 1P1MS
Time-out if no lock within 1.1ms
End of enumeration elements list.
LBYPASS : Lock Bypass
bits : 11 - 11 (1 bit)
DCOFILTER : Sigma-Delta DCO Filter Selection
bits : 12 - 14 (3 bit)
Enumeration: DCOFILTERSelect
0 : FILTER1
Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21
1 : FILTER2
Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6
2 : FILTER3
Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1
3 : FILTER4
Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8
4 : FILTER5
Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64
5 : FILTER6
Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55
6 : FILTER7
Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45
7 : FILTER8
Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4
End of enumeration elements list.
DCOEN : DCO Filter Enable
bits : 15 - 15 (1 bit)
DIV : Clock Divider
bits : 16 - 26 (11 bit)
DPLL Synchronization Busy
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable Synchronization Status
bits : 1 - 1 (1 bit)
DPLLRATIO : DPLL Loop Divider Ratio Synchronization Status
bits : 2 - 2 (1 bit)
DPLL Status
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCK : DPLL Lock Status
bits : 0 - 0 (1 bit)
CLKRDY : DPLL Clock Ready
bits : 1 - 1 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XOSCRDY0 : XOSC 0 Ready
bits : 0 - 0 (1 bit)
XOSCRDY1 : XOSC 1 Ready
bits : 1 - 1 (1 bit)
XOSCFAIL0 : XOSC 0 Clock Failure Detector
bits : 2 - 2 (1 bit)
XOSCFAIL1 : XOSC 1 Clock Failure Detector
bits : 3 - 3 (1 bit)
DFLLRDY : DFLL Ready
bits : 8 - 8 (1 bit)
DFLLOOB : DFLL Out Of Bounds
bits : 9 - 9 (1 bit)
DFLLLCKF : DFLL Lock Fine
bits : 10 - 10 (1 bit)
DFLLLCKC : DFLL Lock Coarse
bits : 11 - 11 (1 bit)
DFLLRCS : DFLL Reference Clock Stopped
bits : 12 - 12 (1 bit)
DPLL0LCKR : DPLL0 Lock Rise
bits : 16 - 16 (1 bit)
DPLL0LCKF : DPLL0 Lock Fall
bits : 17 - 17 (1 bit)
DPLL0LTO : DPLL0 Lock Timeout
bits : 18 - 18 (1 bit)
DPLL0LDRTO : DPLL0 Loop Divider Ratio Update Complete
bits : 19 - 19 (1 bit)
DPLL1LCKR : DPLL1 Lock Rise
bits : 24 - 24 (1 bit)
DPLL1LCKF : DPLL1 Lock Fall
bits : 25 - 25 (1 bit)
DPLL1LTO : DPLL1 Lock Timeout
bits : 26 - 26 (1 bit)
DPLL1LDRTO : DPLL1 Loop Divider Ratio Update Complete
bits : 27 - 27 (1 bit)
DPLL Synchronization Busy
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : DPLL Enable Synchronization Status
bits : 1 - 1 (1 bit)
DPLLRATIO : DPLL Loop Divider Ratio Synchronization Status
bits : 2 - 2 (1 bit)
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