Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x31 byte (0x0)
mem_usage : registers
protection : not protected
SERCOM_USART_EXT - BAUD_FRAC_MODE
SERCOM_USART_EXT - BAUD_FRACFP_MODE
SERCOM_USART_EXT - BAUD_USARTFP_MODE
SERCOM_USART_INT - BAUD_FRAC_MODE
SERCOM_USART_INT - BAUD_FRACFP_MODE
SERCOM_USART_INT - BAUD_USARTFP_MODE
I2C Master Mode - - I2CM Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Operating Mode
bits : 2 - 4 (3 bit)
Enumeration: MODESelect
0 : USART_EXT_CLK
USART with external clock
1 : USART_INT_CLK
USART with internal clock
2 : SPI_SLAVE
SPI in slave operation
3 : SPI_MASTER
SPI in master operation
4 : I2C_SLAVE
I2C slave operation
5 : I2C_MASTER
I2C master operation
End of enumeration elements list.
RUNSTDBY : Run in Standby
bits : 7 - 7 (1 bit)
PINOUT : Pin Usage
bits : 16 - 16 (1 bit)
SDAHOLD : SDA Hold Time
bits : 20 - 21 (2 bit)
Enumeration: SDAHOLDSelect
0 : DISABLE
Disabled
1 : 75NS
50-100ns hold time
2 : 450NS
300-600ns hold time
3 : 600NS
400-800ns hold time
End of enumeration elements list.
MEXTTOEN : Master SCL Low Extend Timeout
bits : 22 - 22 (1 bit)
SEXTTOEN : Slave SCL Low Extend Timeout
bits : 23 - 23 (1 bit)
SPEED : Transfer Speed
bits : 24 - 25 (2 bit)
Enumeration: SPEEDSelect
0 : STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
1 : FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
2 : HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
End of enumeration elements list.
SCLSM : SCL Clock Stretch Mode
bits : 27 - 27 (1 bit)
INACTOUT : Inactive Time-Out
bits : 28 - 29 (2 bit)
Enumeration: INACTOUTSelect
0 : DISABLE
Disabled
1 : 55US
5-6 SCL Time-Out(50-60us)
2 : 105US
10-11 SCL Time-Out(100-110us)
3 : 205US
20-21 SCL Time-Out(200-210us)
End of enumeration elements list.
LOWTOUTEN : SCL Low Timeout Enable
bits : 30 - 30 (1 bit)
I2C Slave Mode - - I2CS Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Operating Mode
bits : 2 - 4 (3 bit)
Enumeration: MODESelect
0 : USART_EXT_CLK
USART with external clock
1 : USART_INT_CLK
USART with internal clock
2 : SPI_SLAVE
SPI in slave operation
3 : SPI_MASTER
SPI in master operation
4 : I2C_SLAVE
I2C slave operation
5 : I2C_MASTER
I2C master operation
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 7 - 7 (1 bit)
PINOUT : Pin Usage
bits : 16 - 16 (1 bit)
SDAHOLD : SDA Hold Time
bits : 20 - 21 (2 bit)
Enumeration: SDAHOLDSelect
0 : DISABLE
Disabled
1 : 75NS
50-100ns hold time
2 : 450NS
300-600ns hold time
3 : 600NS
400-800ns hold time
End of enumeration elements list.
SEXTTOEN : Slave SCL Low Extend Timeout
bits : 23 - 23 (1 bit)
SPEED : Transfer Speed
bits : 24 - 25 (2 bit)
Enumeration: SPEEDSelect
0 : STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
1 : FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
2 : HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
End of enumeration elements list.
SCLSM : SCL Clock Stretch Mode
bits : 27 - 27 (1 bit)
LOWTOUTEN : SCL Low Timeout Enable
bits : 30 - 30 (1 bit)
SPI Slave Mode - - SPIS Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Operating Mode
bits : 2 - 4 (3 bit)
Enumeration: MODESelect
0 : USART_EXT_CLK
USART with external clock
1 : USART_INT_CLK
USART with internal clock
2 : SPI_SLAVE
SPI in slave operation
3 : SPI_MASTER
SPI in master operation
4 : I2C_SLAVE
I2C slave operation
5 : I2C_MASTER
I2C master operation
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 7 - 7 (1 bit)
IBON : Immediate Buffer Overflow Notification
bits : 8 - 8 (1 bit)
DOPO : Data Out Pinout
bits : 16 - 17 (2 bit)
Enumeration: DOPOSelect
0 : PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
2 : PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
End of enumeration elements list.
DIPO : Data In Pinout
bits : 20 - 21 (2 bit)
Enumeration: DIPOSelect
0 : PAD0
SERCOM PAD[0] is used as data input
1 : PAD1
SERCOM PAD[1] is used as data input
2 : PAD2
SERCOM PAD[2] is used as data input
3 : PAD3
SERCOM PAD[3] is used as data input
End of enumeration elements list.
FORM : Frame Format
bits : 24 - 27 (4 bit)
Enumeration: FORMSelect
0 : SPI_FRAME
SPI Frame
2 : SPI_FRAME_WITH_ADDR
SPI Frame with Addr
End of enumeration elements list.
CPHA : Clock Phase
bits : 28 - 28 (1 bit)
Enumeration: CPHASelect
0 : LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
1 : TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
End of enumeration elements list.
CPOL : Clock Polarity
bits : 29 - 29 (1 bit)
Enumeration: CPOLSelect
0 : IDLE_LOW
SCK is low when idle
1 : IDLE_HIGH
SCK is high when idle
End of enumeration elements list.
DORD : Data Order
bits : 30 - 30 (1 bit)
Enumeration: DORDSelect
0 : MSB
MSB is transferred first
1 : LSB
LSB is transferred first
End of enumeration elements list.
SPI Master Mode - - SPIM Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Operating Mode
bits : 2 - 4 (3 bit)
Enumeration: MODESelect
0 : USART_EXT_CLK
USART with external clock
1 : USART_INT_CLK
USART with internal clock
2 : SPI_SLAVE
SPI in slave operation
3 : SPI_MASTER
SPI in master operation
4 : I2C_SLAVE
I2C slave operation
5 : I2C_MASTER
I2C master operation
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 7 - 7 (1 bit)
IBON : Immediate Buffer Overflow Notification
bits : 8 - 8 (1 bit)
DOPO : Data Out Pinout
bits : 16 - 17 (2 bit)
Enumeration: DOPOSelect
0 : PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
2 : PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
End of enumeration elements list.
DIPO : Data In Pinout
bits : 20 - 21 (2 bit)
Enumeration: DIPOSelect
0 : PAD0
SERCOM PAD[0] is used as data input
1 : PAD1
SERCOM PAD[1] is used as data input
2 : PAD2
SERCOM PAD[2] is used as data input
3 : PAD3
SERCOM PAD[3] is used as data input
End of enumeration elements list.
FORM : Frame Format
bits : 24 - 27 (4 bit)
Enumeration: FORMSelect
0 : SPI_FRAME
SPI Frame
2 : SPI_FRAME_WITH_ADDR
SPI Frame with Addr
End of enumeration elements list.
CPHA : Clock Phase
bits : 28 - 28 (1 bit)
Enumeration: CPHASelect
0 : LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
1 : TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
End of enumeration elements list.
CPOL : Clock Polarity
bits : 29 - 29 (1 bit)
Enumeration: CPOLSelect
0 : IDLE_LOW
SCK is low when idle
1 : IDLE_HIGH
SCK is high when idle
End of enumeration elements list.
DORD : Data Order
bits : 30 - 30 (1 bit)
Enumeration: DORDSelect
0 : MSB
MSB is transferred first
1 : LSB
LSB is transferred first
End of enumeration elements list.
USART EXTERNAL CLOCK Mode - - USART_EXT Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Operating Mode
bits : 2 - 4 (3 bit)
Enumeration: MODESelect
0 : USART_EXT_CLK
USART with external clock
1 : USART_INT_CLK
USART with internal clock
2 : SPI_SLAVE
SPI in slave operation
3 : SPI_MASTER
SPI in master operation
4 : I2C_SLAVE
I2C slave operation
5 : I2C_MASTER
I2C master operation
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 7 - 7 (1 bit)
IBON : Immediate Buffer Overflow Notification
bits : 8 - 8 (1 bit)
TXINV : Transmit Data Invert
bits : 9 - 9 (1 bit)
RXINV : Receive Data Invert
bits : 10 - 10 (1 bit)
SAMPR : Sample
bits : 13 - 15 (3 bit)
Enumeration: SAMPRSelect
0 : 16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
1 : 16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
2 : 8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
3 : 8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
4 : 3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
End of enumeration elements list.
TXPO : Transmit Data Pinout
bits : 16 - 17 (2 bit)
Enumeration: TXPOSelect
0 : PAD0
SERCOM PAD[0] is used for data transmission
3 : PAD3
SERCOM_PAD[0] is used for data transmission
End of enumeration elements list.
RXPO : Receive Data Pinout
bits : 20 - 21 (2 bit)
Enumeration: RXPOSelect
0 : PAD0
SERCOM PAD[0] is used for data reception
1 : PAD1
SERCOM PAD[1] is used for data reception
2 : PAD2
SERCOM PAD[2] is used for data reception
3 : PAD3
SERCOM PAD[3] is used for data reception
End of enumeration elements list.
SAMPA : Sample Adjustment
bits : 22 - 23 (2 bit)
FORM : Frame Format
bits : 24 - 27 (4 bit)
Enumeration: FORMSelect
0 : USART_FRAME_NO_PARITY
USART frame
1 : USART_FRAME_WITH_PARITY
USART frame with parity
2 : USART_FRAME_LIN_MASTER_MODE
LIN Master - Break and sync generation
4 : USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud - break detection and auto-baud
5 : USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
7 : USART_FRAME_ISO_7816
ISO 7816
End of enumeration elements list.
CMODE : Communication Mode
bits : 28 - 28 (1 bit)
Enumeration: CMODESelect
0 : ASYNC
Asynchronous Communication
1 : SYNC
Synchronous Communication
End of enumeration elements list.
CPOL : Clock Polarity
bits : 29 - 29 (1 bit)
Enumeration: CPOLSelect
0 : IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
1 : IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
End of enumeration elements list.
DORD : Data Order
bits : 30 - 30 (1 bit)
Enumeration: DORDSelect
0 : MSB
MSB is transmitted first
1 : LSB
LSB is transmitted first
End of enumeration elements list.
USART INTERNAL CLOCK Mode - - USART_INT Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Operating Mode
bits : 2 - 4 (3 bit)
Enumeration: MODESelect
0 : USART_EXT_CLK
USART with external clock
1 : USART_INT_CLK
USART with internal clock
2 : SPI_SLAVE
SPI in slave operation
3 : SPI_MASTER
SPI in master operation
4 : I2C_SLAVE
I2C slave operation
5 : I2C_MASTER
I2C master operation
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 7 - 7 (1 bit)
IBON : Immediate Buffer Overflow Notification
bits : 8 - 8 (1 bit)
TXINV : Transmit Data Invert
bits : 9 - 9 (1 bit)
RXINV : Receive Data Invert
bits : 10 - 10 (1 bit)
SAMPR : Sample
bits : 13 - 15 (3 bit)
Enumeration: SAMPRSelect
0 : 16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
1 : 16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
2 : 8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
3 : 8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
4 : 3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
End of enumeration elements list.
TXPO : Transmit Data Pinout
bits : 16 - 17 (2 bit)
Enumeration: TXPOSelect
0 : PAD0
SERCOM PAD[0] is used for data transmission
3 : PAD3
SERCOM_PAD[0] is used for data transmission
End of enumeration elements list.
RXPO : Receive Data Pinout
bits : 20 - 21 (2 bit)
Enumeration: RXPOSelect
0 : PAD0
SERCOM PAD[0] is used for data reception
1 : PAD1
SERCOM PAD[1] is used for data reception
2 : PAD2
SERCOM PAD[2] is used for data reception
3 : PAD3
SERCOM PAD[3] is used for data reception
End of enumeration elements list.
SAMPA : Sample Adjustment
bits : 22 - 23 (2 bit)
FORM : Frame Format
bits : 24 - 27 (4 bit)
Enumeration: FORMSelect
0 : USART_FRAME_NO_PARITY
USART frame
1 : USART_FRAME_WITH_PARITY
USART frame with parity
2 : USART_FRAME_LIN_MASTER_MODE
LIN Master - Break and sync generation
4 : USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud - break detection and auto-baud
5 : USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
7 : USART_FRAME_ISO_7816
ISO 7816
End of enumeration elements list.
CMODE : Communication Mode
bits : 28 - 28 (1 bit)
Enumeration: CMODESelect
0 : ASYNC
Asynchronous Communication
1 : SYNC
Synchronous Communication
End of enumeration elements list.
CPOL : Clock Polarity
bits : 29 - 29 (1 bit)
Enumeration: CPOLSelect
0 : IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
1 : IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
End of enumeration elements list.
DORD : Data Order
bits : 30 - 30 (1 bit)
Enumeration: DORDSelect
0 : MSB
MSB is transmitted first
1 : LSB
LSB is transmitted first
End of enumeration elements list.
USART_INT Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Operating Mode
bits : 2 - 4 (3 bit)
Enumeration: MODESelect
0x0 : USART_EXT_CLK
USART with external clock
0x1 : USART_INT_CLK
USART with internal clock
0x2 : SPI_SLAVE
SPI in slave operation
0x3 : SPI_MASTER
SPI in master operation
0x4 : I2C_SLAVE
I2C slave operation
0x5 : I2C_MASTER
I2C master operation
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 7 - 7 (1 bit)
IBON : Immediate Buffer Overflow Notification
bits : 8 - 8 (1 bit)
TXINV : Transmit Data Invert
bits : 9 - 9 (1 bit)
RXINV : Receive Data Invert
bits : 10 - 10 (1 bit)
SAMPR : Sample
bits : 13 - 15 (3 bit)
Enumeration: SAMPRSelect
0x0 : 16X_ARITHMETIC
16x over-sampling using arithmetic baudrate generation
0x1 : 16X_FRACTIONAL
16x over-sampling using fractional baudrate generation
0x2 : 8X_ARITHMETIC
8x over-sampling using arithmetic baudrate generation
0x3 : 8X_FRACTIONAL
8x over-sampling using fractional baudrate generation
0x4 : 3X_ARITHMETIC
3x over-sampling using arithmetic baudrate generation
End of enumeration elements list.
PINOUT : Pin Usage
bits : 16 - 16 (1 bit)
DOPO : Data Out Pinout
bits : 16 - 17 (2 bit)
Enumeration: DOPOSelect
0x0 : PAD0
DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
0x2 : PAD2
DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
End of enumeration elements list.
TXPO : Transmit Data Pinout
bits : 16 - 17 (2 bit)
Enumeration: TXPOSelect
0x0 : PAD0
PAD[0] = TxD PAD[1] = XCK
0x2 : PAD2
PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS
0x3 : PAD3
PAD[0] = TxD PAD[1] = XCK PAD[2] = TE
End of enumeration elements list.
SDAHOLD : SDA Hold Time
bits : 20 - 21 (2 bit)
Enumeration: SDAHOLDSelect
0x0 : DISABLE
Disabled
0x1 : 75NS
50-100ns hold time
0x2 : 450NS
300-600ns hold time
0x3 : 600NS
400-800ns hold time
End of enumeration elements list.
DIPO : Data In Pinout
bits : 20 - 21 (2 bit)
Enumeration: DIPOSelect
0x0 : PAD0
SERCOM PAD[0] is used as data input
0x1 : PAD1
SERCOM PAD[1] is used as data input
0x2 : PAD2
SERCOM PAD[2] is used as data input
0x3 : PAD3
SERCOM PAD[3] is used as data input
End of enumeration elements list.
RXPO : Receive Data Pinout
bits : 20 - 21 (2 bit)
Enumeration: RXPOSelect
0x0 : PAD0
SERCOM PAD[0] is used for data reception
0x1 : PAD1
SERCOM PAD[1] is used for data reception
0x2 : PAD2
SERCOM PAD[2] is used for data reception
0x3 : PAD3
SERCOM PAD[3] is used for data reception
End of enumeration elements list.
MEXTTOEN : Master SCL Low Extend Timeout
bits : 22 - 22 (1 bit)
SAMPA : Sample Adjustment
bits : 22 - 23 (2 bit)
Enumeration: SAMPASelect
0x0 : ADJ0
16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5
0x1 : ADJ1
16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6
0x2 : ADJ2
16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7
0x3 : ADJ3
16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8
End of enumeration elements list.
SEXTTOEN : Slave SCL Low Extend Timeout
bits : 23 - 23 (1 bit)
SPEED : Transfer Speed
bits : 24 - 25 (2 bit)
Enumeration: SPEEDSelect
0x0 : STANDARD_AND_FAST_MODE
Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
0x1 : FASTPLUS_MODE
Fast-mode Plus Upto 1MHz
0x2 : HIGH_SPEED_MODE
High-speed mode Upto 3.4MHz
End of enumeration elements list.
FORM : Frame Format
bits : 24 - 27 (4 bit)
Enumeration: FORMSelect
0x0 : SPI_FRAME
SPI Frame
0x2 : SPI_FRAME_WITH_ADDR
SPI Frame with Addr
0x0 : USART_FRAME_NO_PARITY
USART frame
0x1 : USART_FRAME_WITH_PARITY
USART frame with parity
0x2 : USART_FRAME_LIN_MASTER_MODE
LIN Master - Break and sync generation
0x4 : USART_FRAME_AUTO_BAUD_NO_PARITY
Auto-baud (LIN Slave) - break detection and auto-baud
0x5 : USART_FRAME_AUTO_BAUD_WITH_PARITY
Auto-baud - break detection and auto-baud with parity
0x7 : USART_FRAME_ISO_7816
ISO 7816
End of enumeration elements list.
SCLSM : SCL Clock Stretch Mode
bits : 27 - 27 (1 bit)
INACTOUT : Inactive Time-Out
bits : 28 - 29 (2 bit)
Enumeration: INACTOUTSelect
0x0 : DISABLE
Disabled
0x1 : 55US
5-6 SCL Time-Out(50-60us)
0x2 : 105US
10-11 SCL Time-Out(100-110us)
0x3 : 205US
20-21 SCL Time-Out(200-210us)
End of enumeration elements list.
CPHA : Clock Phase
bits : 28 - 28 (1 bit)
Enumeration: CPHASelect
0x0 : LEADING_EDGE
The data is sampled on a leading SCK edge and changed on a trailing SCK edge
0x1 : TRAILING_EDGE
The data is sampled on a trailing SCK edge and changed on a leading SCK edge
End of enumeration elements list.
CMODE : Communication Mode
bits : 28 - 28 (1 bit)
Enumeration: CMODESelect
0x0 : ASYNC
Asynchronous Communication
0x1 : SYNC
Synchronous Communication
End of enumeration elements list.
CPOL : Clock Polarity
bits : 29 - 29 (1 bit)
Enumeration: CPOLSelect
0x0 : IDLE_LOW
TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
0x1 : IDLE_HIGH
TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
End of enumeration elements list.
LOWTOUTEN : SCL Low Timeout Enable
bits : 30 - 30 (1 bit)
DORD : Data Order
bits : 30 - 30 (1 bit)
Enumeration: DORDSelect
0x0 : MSB
MSB is transmitted first
0x1 : LSB
LSB is transmitted first
End of enumeration elements list.
I2C Master Mode - - I2CM Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : Master On Bus Interrupt Disable
bits : 0 - 0 (1 bit)
SB : Slave On Bus Interrupt Disable
bits : 1 - 1 (1 bit)
ERROR : Combined Error Interrupt Disable
bits : 7 - 7 (1 bit)
I2C Slave Mode - - I2CS Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREC : Stop Received Interrupt Disable
bits : 0 - 0 (1 bit)
AMATCH : Address Match Interrupt Disable
bits : 1 - 1 (1 bit)
DRDY : Data Interrupt Disable
bits : 2 - 2 (1 bit)
ERROR : Combined Error Interrupt Disable
bits : 7 - 7 (1 bit)
SPI Slave Mode - - SPIS Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt Disable
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt Disable
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt Disable
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Disable
bits : 3 - 3 (1 bit)
ERROR : Combined Error Interrupt Disable
bits : 7 - 7 (1 bit)
SPI Master Mode - - SPIM Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt Disable
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt Disable
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt Disable
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Disable
bits : 3 - 3 (1 bit)
ERROR : Combined Error Interrupt Disable
bits : 7 - 7 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt Disable
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt Disable
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt Disable
bits : 2 - 2 (1 bit)
RXS : Receive Start Interrupt Disable
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt Disable
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt Disable
bits : 7 - 7 (1 bit)
USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt Disable
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt Disable
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt Disable
bits : 2 - 2 (1 bit)
RXS : Receive Start Interrupt Disable
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt Disable
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt Disable
bits : 7 - 7 (1 bit)
USART_INT Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : Master On Bus Interrupt Disable
bits : 0 - 0 (1 bit)
PREC : Stop Received Interrupt Disable
bits : 0 - 0 (1 bit)
DRE : Data Register Empty Interrupt Disable
bits : 0 - 0 (1 bit)
SB : Slave On Bus Interrupt Disable
bits : 1 - 1 (1 bit)
AMATCH : Address Match Interrupt Disable
bits : 1 - 1 (1 bit)
TXC : Transmit Complete Interrupt Disable
bits : 1 - 1 (1 bit)
DRDY : Data Interrupt Disable
bits : 2 - 2 (1 bit)
RXC : Receive Complete Interrupt Disable
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Disable
bits : 3 - 3 (1 bit)
RXS : Receive Start Interrupt Disable
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt Disable
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt Disable
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt Disable
bits : 7 - 7 (1 bit)
I2C Master Mode - - I2CM Interrupt Enable Set
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : Master On Bus Interrupt Enable
bits : 0 - 0 (1 bit)
SB : Slave On Bus Interrupt Enable
bits : 1 - 1 (1 bit)
ERROR : Combined Error Interrupt Enable
bits : 7 - 7 (1 bit)
I2C Slave Mode - - I2CS Interrupt Enable Set
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREC : Stop Received Interrupt Enable
bits : 0 - 0 (1 bit)
AMATCH : Address Match Interrupt Enable
bits : 1 - 1 (1 bit)
DRDY : Data Interrupt Enable
bits : 2 - 2 (1 bit)
ERROR : Combined Error Interrupt Enable
bits : 7 - 7 (1 bit)
SPI Slave Mode - - SPIS Interrupt Enable Set
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt Enable
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt Enable
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt Enable
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Enable
bits : 3 - 3 (1 bit)
ERROR : Combined Error Interrupt Enable
bits : 7 - 7 (1 bit)
SPI Master Mode - - SPIM Interrupt Enable Set
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt Enable
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt Enable
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt Enable
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Enable
bits : 3 - 3 (1 bit)
ERROR : Combined Error Interrupt Enable
bits : 7 - 7 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Set
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt Enable
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt Enable
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt Enable
bits : 2 - 2 (1 bit)
RXS : Receive Start Interrupt Enable
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt Enable
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt Enable
bits : 7 - 7 (1 bit)
USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Set
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt Enable
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt Enable
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt Enable
bits : 2 - 2 (1 bit)
RXS : Receive Start Interrupt Enable
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt Enable
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt Enable
bits : 7 - 7 (1 bit)
USART_INT Interrupt Enable Set
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : Master On Bus Interrupt Enable
bits : 0 - 0 (1 bit)
PREC : Stop Received Interrupt Enable
bits : 0 - 0 (1 bit)
DRE : Data Register Empty Interrupt Enable
bits : 0 - 0 (1 bit)
SB : Slave On Bus Interrupt Enable
bits : 1 - 1 (1 bit)
AMATCH : Address Match Interrupt Enable
bits : 1 - 1 (1 bit)
TXC : Transmit Complete Interrupt Enable
bits : 1 - 1 (1 bit)
DRDY : Data Interrupt Enable
bits : 2 - 2 (1 bit)
RXC : Receive Complete Interrupt Enable
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Enable
bits : 3 - 3 (1 bit)
RXS : Receive Start Interrupt Enable
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt Enable
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt Enable
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt Enable
bits : 7 - 7 (1 bit)
I2C Master Mode - - I2CM Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : Master On Bus Interrupt
bits : 0 - 0 (1 bit)
SB : Slave On Bus Interrupt
bits : 1 - 1 (1 bit)
ERROR : Combined Error Interrupt
bits : 7 - 7 (1 bit)
I2C Slave Mode - - I2CS Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREC : Stop Received Interrupt
bits : 0 - 0 (1 bit)
AMATCH : Address Match Interrupt
bits : 1 - 1 (1 bit)
DRDY : Data Interrupt
bits : 2 - 2 (1 bit)
ERROR : Combined Error Interrupt
bits : 7 - 7 (1 bit)
SPI Slave Mode - - SPIS Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Flag
bits : 3 - 3 (1 bit)
ERROR : Combined Error Interrupt
bits : 7 - 7 (1 bit)
SPI Master Mode - - SPIM Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Flag
bits : 3 - 3 (1 bit)
ERROR : Combined Error Interrupt
bits : 7 - 7 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt
bits : 2 - 2 (1 bit)
RXS : Receive Start Interrupt
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt
bits : 7 - 7 (1 bit)
USART INTERNAL CLOCK Mode - - USART_INT Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRE : Data Register Empty Interrupt
bits : 0 - 0 (1 bit)
TXC : Transmit Complete Interrupt
bits : 1 - 1 (1 bit)
RXC : Receive Complete Interrupt
bits : 2 - 2 (1 bit)
RXS : Receive Start Interrupt
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt
bits : 7 - 7 (1 bit)
USART_INT Interrupt Flag Status and Clear
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : Master On Bus Interrupt
bits : 0 - 0 (1 bit)
PREC : Stop Received Interrupt
bits : 0 - 0 (1 bit)
DRE : Data Register Empty Interrupt
bits : 0 - 0 (1 bit)
SB : Slave On Bus Interrupt
bits : 1 - 1 (1 bit)
AMATCH : Address Match Interrupt
bits : 1 - 1 (1 bit)
TXC : Transmit Complete Interrupt
bits : 1 - 1 (1 bit)
DRDY : Data Interrupt
bits : 2 - 2 (1 bit)
RXC : Receive Complete Interrupt
bits : 2 - 2 (1 bit)
SSL : Slave Select Low Interrupt Flag
bits : 3 - 3 (1 bit)
RXS : Receive Start Interrupt
bits : 3 - 3 (1 bit)
CTSIC : Clear To Send Input Change Interrupt
bits : 4 - 4 (1 bit)
RXBRK : Break Received Interrupt
bits : 5 - 5 (1 bit)
ERROR : Combined Error Interrupt
bits : 7 - 7 (1 bit)
I2C Master Mode - - I2CM Status
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSERR : Bus Error
bits : 0 - 0 (1 bit)
ARBLOST : Arbitration Lost
bits : 1 - 1 (1 bit)
RXNACK : Received Not Acknowledge
bits : 2 - 2 (1 bit)
BUSSTATE : Bus State
bits : 4 - 5 (2 bit)
LOWTOUT : SCL Low Timeout
bits : 6 - 6 (1 bit)
CLKHOLD : Clock Hold
bits : 7 - 7 (1 bit)
MEXTTOUT : Master SCL Low Extend Timeout
bits : 8 - 8 (1 bit)
SEXTTOUT : Slave SCL Low Extend Timeout
bits : 9 - 9 (1 bit)
LENERR : Length Error
bits : 10 - 10 (1 bit)
I2C Slave Mode - - I2CS Status
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSERR : Bus Error
bits : 0 - 0 (1 bit)
COLL : Transmit Collision
bits : 1 - 1 (1 bit)
RXNACK : Received Not Acknowledge
bits : 2 - 2 (1 bit)
DIR : Read/Write Direction
bits : 3 - 3 (1 bit)
SR : Repeated Start
bits : 4 - 4 (1 bit)
LOWTOUT : SCL Low Timeout
bits : 6 - 6 (1 bit)
CLKHOLD : Clock Hold
bits : 7 - 7 (1 bit)
SEXTTOUT : Slave SCL Low Extend Timeout
bits : 9 - 9 (1 bit)
HS : High Speed
bits : 10 - 10 (1 bit)
LENERR : Transaction Length Error
bits : 11 - 11 (1 bit)
SPI Slave Mode - - SPIS Status
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFOVF : Buffer Overflow
bits : 2 - 2 (1 bit)
LENERR : Transaction Length Error
bits : 11 - 11 (1 bit)
SPI Master Mode - - SPIM Status
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFOVF : Buffer Overflow
bits : 2 - 2 (1 bit)
LENERR : Transaction Length Error
bits : 11 - 11 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Status
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERR : Parity Error
bits : 0 - 0 (1 bit)
FERR : Frame Error
bits : 1 - 1 (1 bit)
BUFOVF : Buffer Overflow
bits : 2 - 2 (1 bit)
CTS : Clear To Send
bits : 3 - 3 (1 bit)
ISF : Inconsistent Sync Field
bits : 4 - 4 (1 bit)
COLL : Collision Detected
bits : 5 - 5 (1 bit)
TXE : Transmitter Empty
bits : 6 - 6 (1 bit)
ITER : Maximum Number of Repetitions Reached
bits : 7 - 7 (1 bit)
USART INTERNAL CLOCK Mode - - USART_INT Status
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERR : Parity Error
bits : 0 - 0 (1 bit)
FERR : Frame Error
bits : 1 - 1 (1 bit)
BUFOVF : Buffer Overflow
bits : 2 - 2 (1 bit)
CTS : Clear To Send
bits : 3 - 3 (1 bit)
ISF : Inconsistent Sync Field
bits : 4 - 4 (1 bit)
COLL : Collision Detected
bits : 5 - 5 (1 bit)
TXE : Transmitter Empty
bits : 6 - 6 (1 bit)
ITER : Maximum Number of Repetitions Reached
bits : 7 - 7 (1 bit)
USART_INT Status
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSERR : Bus Error
bits : 0 - 0 (1 bit)
PERR : Parity Error
bits : 0 - 0 (1 bit)
ARBLOST : Arbitration Lost
bits : 1 - 1 (1 bit)
FERR : Frame Error
bits : 1 - 1 (1 bit)
RXNACK : Received Not Acknowledge
bits : 2 - 2 (1 bit)
BUFOVF : Buffer Overflow
bits : 2 - 2 (1 bit)
DIR : Read/Write Direction
bits : 3 - 3 (1 bit)
CTS : Clear To Send
bits : 3 - 3 (1 bit)
BUSSTATE : Bus State
bits : 4 - 5 (2 bit)
SR : Repeated Start
bits : 4 - 4 (1 bit)
ISF : Inconsistent Sync Field
bits : 4 - 4 (1 bit)
COLL : Collision Detected
bits : 5 - 5 (1 bit)
LOWTOUT : SCL Low Timeout
bits : 6 - 6 (1 bit)
TXE : Transmitter Empty
bits : 6 - 6 (1 bit)
CLKHOLD : Clock Hold
bits : 7 - 7 (1 bit)
ITER : Maximum Number of Repetitions Reached
bits : 7 - 7 (1 bit)
MEXTTOUT : Master SCL Low Extend Timeout
bits : 8 - 8 (1 bit)
SEXTTOUT : Slave SCL Low Extend Timeout
bits : 9 - 9 (1 bit)
HS : High Speed
bits : 10 - 10 (1 bit)
LENERR : Transaction Length Error
bits : 11 - 11 (1 bit)
I2C Master Mode - - I2CM Synchronization Busy
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : SERCOM Enable Synchronization Busy
bits : 1 - 1 (1 bit)
SYSOP : System Operation Synchronization Busy
bits : 2 - 2 (1 bit)
LENGTH : Length Synchronization Busy
bits : 4 - 4 (1 bit)
I2C Slave Mode - - I2CS Synchronization Busy
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : SERCOM Enable Synchronization Busy
bits : 1 - 1 (1 bit)
LENGTH : Length Synchronization Busy
bits : 4 - 4 (1 bit)
SPI Slave Mode - - SPIS Synchronization Busy
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : SERCOM Enable Synchronization Busy
bits : 1 - 1 (1 bit)
CTRLB : CTRLB Synchronization Busy
bits : 2 - 2 (1 bit)
LENGTH : LENGTH Synchronization Busy
bits : 4 - 4 (1 bit)
SPI Master Mode - - SPIM Synchronization Busy
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : SERCOM Enable Synchronization Busy
bits : 1 - 1 (1 bit)
CTRLB : CTRLB Synchronization Busy
bits : 2 - 2 (1 bit)
LENGTH : LENGTH Synchronization Busy
bits : 4 - 4 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Synchronization Busy
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : SERCOM Enable Synchronization Busy
bits : 1 - 1 (1 bit)
CTRLB : CTRLB Synchronization Busy
bits : 2 - 2 (1 bit)
RXERRCNT : RXERRCNT Synchronization Busy
bits : 3 - 3 (1 bit)
LENGTH : LENGTH Synchronization Busy
bits : 4 - 4 (1 bit)
USART INTERNAL CLOCK Mode - - USART_INT Synchronization Busy
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : SERCOM Enable Synchronization Busy
bits : 1 - 1 (1 bit)
CTRLB : CTRLB Synchronization Busy
bits : 2 - 2 (1 bit)
RXERRCNT : RXERRCNT Synchronization Busy
bits : 3 - 3 (1 bit)
LENGTH : LENGTH Synchronization Busy
bits : 4 - 4 (1 bit)
USART_INT Synchronization Busy
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : SERCOM Enable Synchronization Busy
bits : 1 - 1 (1 bit)
SYSOP : System Operation Synchronization Busy
bits : 2 - 2 (1 bit)
CTRLB : CTRLB Synchronization Busy
bits : 2 - 2 (1 bit)
RXERRCNT : RXERRCNT Synchronization Busy
bits : 3 - 3 (1 bit)
LENGTH : LENGTH Synchronization Busy
bits : 4 - 4 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Receive Error Count
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USART INTERNAL CLOCK Mode - - USART_INT Receive Error Count
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USART_INT Receive Error Count
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXERRCNT : Receive Error Count
bits : 0 - 7 (8 bit)
I2C Slave Mode - - I2CS Length
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Data Length
bits : 0 - 7 (8 bit)
LENEN : Data Length Enable
bits : 8 - 8 (1 bit)
SPI Slave Mode - - SPIS Length
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Data Length
bits : 0 - 7 (8 bit)
LENEN : Data Length Enable
bits : 8 - 8 (1 bit)
SPI Master Mode - - SPIM Length
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Data Length
bits : 0 - 7 (8 bit)
LENEN : Data Length Enable
bits : 8 - 8 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Length
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Data Length
bits : 0 - 7 (8 bit)
LENEN : Data Length Enable
bits : 8 - 9 (2 bit)
USART INTERNAL CLOCK Mode - - USART_INT Length
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Data Length
bits : 0 - 7 (8 bit)
LENEN : Data Length Enable
bits : 8 - 9 (2 bit)
USART_INT Length
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEN : Data Length
bits : 0 - 7 (8 bit)
LENEN : Data Length Enable
bits : 8 - 9 (2 bit)
I2C Master Mode - - I2CM Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address Value
bits : 0 - 10 (11 bit)
LENEN : Length Enable
bits : 13 - 13 (1 bit)
HS : High Speed Mode
bits : 14 - 14 (1 bit)
TENBITEN : Ten Bit Addressing Enable
bits : 15 - 15 (1 bit)
LEN : Length
bits : 16 - 23 (8 bit)
I2C Slave Mode - - I2CS Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GENCEN : General Call Address Enable
bits : 0 - 0 (1 bit)
ADDR : Address Value
bits : 1 - 10 (10 bit)
TENBITEN : Ten Bit Addressing Enable
bits : 15 - 15 (1 bit)
ADDRMASK : Address Mask
bits : 17 - 26 (10 bit)
SPI Slave Mode - - SPIS Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address Value
bits : 0 - 7 (8 bit)
ADDRMASK : Address Mask
bits : 16 - 23 (8 bit)
SPI Master Mode - - SPIM Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address Value
bits : 0 - 7 (8 bit)
ADDRMASK : Address Mask
bits : 16 - 23 (8 bit)
SPIM Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address Value
bits : 0 - 7 (8 bit)
GENCEN : General Call Address Enable
bits : 0 - 0 (1 bit)
LENEN : Length Enable
bits : 13 - 13 (1 bit)
HS : High Speed Mode
bits : 14 - 14 (1 bit)
TENBITEN : Ten Bit Addressing Enable
bits : 15 - 15 (1 bit)
LEN : Length
bits : 16 - 23 (8 bit)
ADDRMASK : Address Mask
bits : 16 - 23 (8 bit)
I2C Master Mode - - I2CM Data
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data Value
bits : 0 - 7 (8 bit)
I2C Slave Mode - - I2CS Data
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data Value
bits : 0 - 31 (32 bit)
SPI Slave Mode - - SPIS Data
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data Value
bits : 0 - 31 (32 bit)
SPI Master Mode - - SPIM Data
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data Value
bits : 0 - 31 (32 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Data
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data Value
bits : 0 - 31 (32 bit)
USART INTERNAL CLOCK Mode - - USART_INT Data
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data Value
bits : 0 - 31 (32 bit)
USART_INT Data
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data Value
bits : 0 - 31 (32 bit)
I2C Master Mode - - I2CM Debug Control
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSTOP : Debug Mode
bits : 0 - 0 (1 bit)
SPI Slave Mode - - SPIS Debug Control
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSTOP : Debug Mode
bits : 0 - 0 (1 bit)
SPI Master Mode - - SPIM Debug Control
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSTOP : Debug Mode
bits : 0 - 0 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Debug Control
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSTOP : Debug Mode
bits : 0 - 0 (1 bit)
USART INTERNAL CLOCK Mode - - USART_INT Debug Control
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSTOP : Debug Mode
bits : 0 - 0 (1 bit)
USART_INT Debug Control
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGSTOP : Debug Mode
bits : 0 - 0 (1 bit)
I2C Master Mode - - I2CM Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMEN : Smart Mode Enable
bits : 8 - 8 (1 bit)
QCEN : Quick Command Enable
bits : 9 - 9 (1 bit)
CMD : Command
bits : 16 - 17 (2 bit)
ACKACT : Acknowledge Action
bits : 18 - 18 (1 bit)
I2C Slave Mode - - I2CS Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMEN : Smart Mode Enable
bits : 8 - 8 (1 bit)
GCMD : PMBus Group Command
bits : 9 - 9 (1 bit)
AACKEN : Automatic Address Acknowledge
bits : 10 - 10 (1 bit)
AMODE : Address Mode
bits : 14 - 15 (2 bit)
CMD : Command
bits : 16 - 17 (2 bit)
ACKACT : Acknowledge Action
bits : 18 - 18 (1 bit)
SPI Slave Mode - - SPIS Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSIZE : Character Size
bits : 0 - 2 (3 bit)
Enumeration: CHSIZESelect
0 : 8_BIT
8 bits
1 : 9_BIT
9 bits
End of enumeration elements list.
PLOADEN : Data Preload Enable
bits : 6 - 6 (1 bit)
SSDE : Slave Select Low Detect Enable
bits : 9 - 9 (1 bit)
MSSEN : Master Slave Select Enable
bits : 13 - 13 (1 bit)
AMODE : Address Mode
bits : 14 - 15 (2 bit)
Enumeration: AMODESelect
0 : MASK
SPI Address mask
1 : 2_ADDRESSES
Two unique Addressess
2 : RANGE
Address Range
End of enumeration elements list.
RXEN : Receiver Enable
bits : 17 - 17 (1 bit)
SPI Master Mode - - SPIM Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSIZE : Character Size
bits : 0 - 2 (3 bit)
Enumeration: CHSIZESelect
0 : 8_BIT
8 bits
1 : 9_BIT
9 bits
End of enumeration elements list.
PLOADEN : Data Preload Enable
bits : 6 - 6 (1 bit)
SSDE : Slave Select Low Detect Enable
bits : 9 - 9 (1 bit)
MSSEN : Master Slave Select Enable
bits : 13 - 13 (1 bit)
AMODE : Address Mode
bits : 14 - 15 (2 bit)
Enumeration: AMODESelect
0 : MASK
SPI Address mask
1 : 2_ADDRESSES
Two unique Addressess
2 : RANGE
Address Range
End of enumeration elements list.
RXEN : Receiver Enable
bits : 17 - 17 (1 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSIZE : Character Size
bits : 0 - 2 (3 bit)
Enumeration: CHSIZESelect
0 : 8_BIT
8 Bits
1 : 9_BIT
9 Bits
5 : 5_BIT
5 Bits
6 : 6_BIT
6 Bits
7 : 7_BIT
7 Bits
End of enumeration elements list.
SBMODE : Stop Bit Mode
bits : 6 - 6 (1 bit)
Enumeration: SBMODESelect
0 : 1_BIT
One Stop Bit
1 : 2_BIT
Two Stop Bits
End of enumeration elements list.
COLDEN : Collision Detection Enable
bits : 8 - 8 (1 bit)
SFDE : Start of Frame Detection Enable
bits : 9 - 9 (1 bit)
ENC : Encoding Format
bits : 10 - 10 (1 bit)
PMODE : Parity Mode
bits : 13 - 13 (1 bit)
Enumeration: PMODESelect
0 : EVEN
Even Parity
1 : ODD
Odd Parity
End of enumeration elements list.
TXEN : Transmitter Enable
bits : 16 - 16 (1 bit)
RXEN : Receiver Enable
bits : 17 - 17 (1 bit)
LINCMD : LIN Command
bits : 24 - 25 (2 bit)
USART INTERNAL CLOCK Mode - - USART_INT Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSIZE : Character Size
bits : 0 - 2 (3 bit)
Enumeration: CHSIZESelect
0 : 8_BIT
8 Bits
1 : 9_BIT
9 Bits
5 : 5_BIT
5 Bits
6 : 6_BIT
6 Bits
7 : 7_BIT
7 Bits
End of enumeration elements list.
SBMODE : Stop Bit Mode
bits : 6 - 6 (1 bit)
Enumeration: SBMODESelect
0 : 1_BIT
One Stop Bit
1 : 2_BIT
Two Stop Bits
End of enumeration elements list.
COLDEN : Collision Detection Enable
bits : 8 - 8 (1 bit)
SFDE : Start of Frame Detection Enable
bits : 9 - 9 (1 bit)
ENC : Encoding Format
bits : 10 - 10 (1 bit)
PMODE : Parity Mode
bits : 13 - 13 (1 bit)
Enumeration: PMODESelect
0 : EVEN
Even Parity
1 : ODD
Odd Parity
End of enumeration elements list.
TXEN : Transmitter Enable
bits : 16 - 16 (1 bit)
RXEN : Receiver Enable
bits : 17 - 17 (1 bit)
LINCMD : LIN Command
bits : 24 - 25 (2 bit)
USART_INT Control B
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSIZE : Character Size
bits : 0 - 2 (3 bit)
Enumeration: CHSIZESelect
0x0 : 8_BIT
8 Bits
0x1 : 9_BIT
9 Bits
0x5 : 5_BIT
5 Bits
0x6 : 6_BIT
6 Bits
0x7 : 7_BIT
7 Bits
End of enumeration elements list.
PLOADEN : Data Preload Enable
bits : 6 - 6 (1 bit)
SBMODE : Stop Bit Mode
bits : 6 - 6 (1 bit)
Enumeration: SBMODESelect
0x0 : 1_BIT
One Stop Bit
0x1 : 2_BIT
Two Stop Bits
End of enumeration elements list.
SMEN : Smart Mode Enable
bits : 8 - 8 (1 bit)
COLDEN : Collision Detection Enable
bits : 8 - 8 (1 bit)
QCEN : Quick Command Enable
bits : 9 - 9 (1 bit)
GCMD : PMBus Group Command
bits : 9 - 9 (1 bit)
SSDE : Slave Select Low Detect Enable
bits : 9 - 9 (1 bit)
SFDE : Start of Frame Detection Enable
bits : 9 - 9 (1 bit)
AACKEN : Automatic Address Acknowledge
bits : 10 - 10 (1 bit)
ENC : Encoding Format
bits : 10 - 10 (1 bit)
MSSEN : Master Slave Select Enable
bits : 13 - 13 (1 bit)
PMODE : Parity Mode
bits : 13 - 13 (1 bit)
Enumeration: PMODESelect
0x0 : EVEN
Even Parity
0x1 : ODD
Odd Parity
End of enumeration elements list.
AMODE : Address Mode
bits : 14 - 15 (2 bit)
Enumeration: AMODESelect
0x0 : MASK
SPI Address mask
0x1 : 2_ADDRESSES
Two unique Addressess
0x2 : RANGE
Address Range
End of enumeration elements list.
CMD : Command
bits : 16 - 17 (2 bit)
TXEN : Transmitter Enable
bits : 16 - 16 (1 bit)
RXEN : Receiver Enable
bits : 17 - 17 (1 bit)
ACKACT : Acknowledge Action
bits : 18 - 18 (1 bit)
LINCMD : LIN Command
bits : 24 - 25 (2 bit)
Enumeration: LINCMDSelect
0x0 : NONE
Normal USART transmission
0x1 : SOFTWARE_CONTROL_TRANSMIT_CMD
Break field is transmitted when DATA is written
0x2 : AUTO_TRANSMIT_CMD
Break, sync and identifier are automatically transmitted when DATA is written with the identifier
End of enumeration elements list.
I2C Master Mode - - I2CM Control C
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA32B : Data 32 Bit
bits : 24 - 24 (1 bit)
Enumeration: DATA32BSelect
0 : DATA_TRANS_8BIT
Data transaction from/to DATA register are 8-bit
1 : DATA_TRANS_32BIT
Data transaction from/to DATA register are 32-bit
End of enumeration elements list.
I2C Slave Mode - - I2CS Control C
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDASETUP : SDA Setup Time
bits : 0 - 3 (4 bit)
DATA32B : Data 32 Bit
bits : 24 - 24 (1 bit)
Enumeration: DATA32BSelect
0 : DATA_TRANS_8BIT
Data transaction from/to DATA register are 8-bit
1 : DATA_TRANS_32BIT
Data transaction from/to DATA register are 32-bit
End of enumeration elements list.
SPI Slave Mode - - SPIS Control C
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICSPACE : Inter-Character Spacing
bits : 0 - 5 (6 bit)
DATA32B : Data 32 Bit
bits : 24 - 24 (1 bit)
Enumeration: DATA32BSelect
0 : DATA_TRANS_8BIT
Transaction from and to DATA register are 8-bit
1 : DATA_TRANS_32BIT
Transaction from and to DATA register are 32-bit
End of enumeration elements list.
SPI Master Mode - - SPIM Control C
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICSPACE : Inter-Character Spacing
bits : 0 - 5 (6 bit)
DATA32B : Data 32 Bit
bits : 24 - 24 (1 bit)
Enumeration: DATA32BSelect
0 : DATA_TRANS_8BIT
Transaction from and to DATA register are 8-bit
1 : DATA_TRANS_32BIT
Transaction from and to DATA register are 32-bit
End of enumeration elements list.
USART EXTERNAL CLOCK Mode - - USART_EXT Control C
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTIME : Guard Time
bits : 0 - 2 (3 bit)
BRKLEN : LIN Master Break Length
bits : 8 - 9 (2 bit)
HDRDLY : LIN Master Header Delay
bits : 10 - 11 (2 bit)
INACK : Inhibit Not Acknowledge
bits : 16 - 16 (1 bit)
DSNACK : Disable Successive NACK
bits : 17 - 17 (1 bit)
MAXITER : Maximum Iterations
bits : 20 - 22 (3 bit)
DATA32B : Data 32 Bit
bits : 24 - 25 (2 bit)
Enumeration: DATA32BSelect
0 : DATA_READ_WRITE_CHSIZE
Data reads and writes according CTRLB.CHSIZE
1 : DATA_READ_CHSIZE_WRITE_32BIT
Data reads according CTRLB.CHSIZE and writes according 32-bit extension
2 : DATA_READ_32BIT_WRITE_CHSIZE
Data reads according 32-bit extension and writes according CTRLB.CHSIZE
3 : DATA_READ_WRITE_32BIT
Data reads and writes according 32-bit extension
End of enumeration elements list.
USART INTERNAL CLOCK Mode - - USART_INT Control C
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GTIME : Guard Time
bits : 0 - 2 (3 bit)
BRKLEN : LIN Master Break Length
bits : 8 - 9 (2 bit)
HDRDLY : LIN Master Header Delay
bits : 10 - 11 (2 bit)
INACK : Inhibit Not Acknowledge
bits : 16 - 16 (1 bit)
DSNACK : Disable Successive NACK
bits : 17 - 17 (1 bit)
MAXITER : Maximum Iterations
bits : 20 - 22 (3 bit)
DATA32B : Data 32 Bit
bits : 24 - 25 (2 bit)
Enumeration: DATA32BSelect
0 : DATA_READ_WRITE_CHSIZE
Data reads and writes according CTRLB.CHSIZE
1 : DATA_READ_CHSIZE_WRITE_32BIT
Data reads according CTRLB.CHSIZE and writes according 32-bit extension
2 : DATA_READ_32BIT_WRITE_CHSIZE
Data reads according 32-bit extension and writes according CTRLB.CHSIZE
3 : DATA_READ_WRITE_32BIT
Data reads and writes according 32-bit extension
End of enumeration elements list.
USART_INT Control C
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDASETUP : SDA Setup Time
bits : 0 - 3 (4 bit)
ICSPACE : Inter-Character Spacing
bits : 0 - 5 (6 bit)
GTIME : Guard Time
bits : 0 - 2 (3 bit)
BRKLEN : LIN Master Break Length
bits : 8 - 9 (2 bit)
Enumeration: BRKLENSelect
0x0 : 13_BIT
Break field transmission is 13 bit times
0x1 : 17_BIT
Break field transmission is 17 bit times
0x2 : 21_BIT
Break field transmission is 21 bit times
0x3 : 26_BIT
Break field transmission is 26 bit times
End of enumeration elements list.
HDRDLY : LIN Master Header Delay
bits : 10 - 11 (2 bit)
Enumeration: HDRDLYSelect
0x0 : DELAY0
Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time
0x1 : DELAY1
Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time
0x2 : DELAY2
Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time
0x3 : DELAY3
Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time
End of enumeration elements list.
INACK : Inhibit Not Acknowledge
bits : 16 - 16 (1 bit)
DSNACK : Disable Successive NACK
bits : 17 - 17 (1 bit)
MAXITER : Maximum Iterations
bits : 20 - 22 (3 bit)
DATA32B : Data 32 Bit
bits : 24 - 25 (2 bit)
Enumeration: DATA32BSelect
0x0 : DATA_TRANS_8BIT
Transaction from and to DATA register are 8-bit
0x1 : DATA_TRANS_32BIT
Transaction from and to DATA register are 32-bit
0x0 : DATA_READ_WRITE_CHSIZE
Data reads and writes according CTRLB.CHSIZE
0x1 : DATA_READ_CHSIZE_WRITE_32BIT
Data reads according CTRLB.CHSIZE and writes according 32-bit extension
0x2 : DATA_READ_32BIT_WRITE_CHSIZE
Data reads according 32-bit extension and writes according CTRLB.CHSIZE
0x3 : DATA_READ_WRITE_32BIT
Data reads and writes according 32-bit extension
End of enumeration elements list.
I2C Master Mode - - I2CM Baud Rate
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 7 (8 bit)
BAUDLOW : Baud Rate Value Low
bits : 8 - 15 (8 bit)
HSBAUD : High Speed Baud Rate Value
bits : 16 - 23 (8 bit)
HSBAUDLOW : High Speed Baud Rate Value Low
bits : 24 - 31 (8 bit)
SPI Slave Mode - - SPIS Baud Rate
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 7 (8 bit)
SPI Master Mode - - SPIM Baud Rate
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 7 (8 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 15 (16 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 12 (13 bit)
FP : Fractional Part
bits : 13 - 15 (3 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 12 (13 bit)
FP : Fractional Part
bits : 13 - 15 (3 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 15 (16 bit)
USART INTERNAL CLOCK Mode - - USART_INT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 15 (16 bit)
USART INTERNAL CLOCK Mode - - USART_INT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 12 (13 bit)
FP : Fractional Part
bits : 13 - 15 (3 bit)
USART INTERNAL CLOCK Mode - - USART_INT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 12 (13 bit)
FP : Fractional Part
bits : 13 - 15 (3 bit)
USART INTERNAL CLOCK Mode - - USART_INT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 15 (16 bit)
USART_INT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 15 (16 bit)
BAUDLOW : Baud Rate Value Low
bits : 8 - 15 (8 bit)
HSBAUD : High Speed Baud Rate Value
bits : 16 - 23 (8 bit)
HSBAUDLOW : High Speed Baud Rate Value Low
bits : 24 - 31 (8 bit)
USART_INT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 12 (13 bit)
FP : Fractional Part
bits : 13 - 15 (3 bit)
USART_INT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 12 (13 bit)
FP : Fractional Part
bits : 13 - 15 (3 bit)
USART_INT Baud Rate
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : BAUD
reset_Mask : 0x0
BAUD : Baud Rate Value
bits : 0 - 15 (16 bit)
USART EXTERNAL CLOCK Mode - - USART_EXT Receive Pulse Length
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPL : Receive Pulse Length
bits : 0 - 7 (8 bit)
USART INTERNAL CLOCK Mode - - USART_INT Receive Pulse Length
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPL : Receive Pulse Length
bits : 0 - 7 (8 bit)
USART_INT Receive Pulse Length
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPL : Receive Pulse Length
bits : 0 - 7 (8 bit)
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