Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : registers
protection : not protected
Core Release
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBSTEP : Sub-step of Core Release
bits : 20 - 23 (4 bit)
STEP : Step of Core Release
bits : 24 - 27 (4 bit)
REL : Core Release
bits : 28 - 31 (4 bit)
Core Release
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBSTEP : Sub-step of Core Release
bits : 20 - 23 (4 bit)
STEP : Step of Core Release
bits : 24 - 27 (4 bit)
REL : Core Release
bits : 28 - 31 (4 bit)
Test
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBCK : Loop Back Mode
bits : 4 - 4 (1 bit)
TX : Control of Transmit Pin
bits : 5 - 6 (2 bit)
Enumeration: TXSelect
0 : CORE
TX controlled by CAN core
1 : SAMPLE
TX monitoring sample point
2 : DOMINANT
Dominant (0) level at pin CAN_TX
3 : RECESSIVE
Recessive (1) level at pin CAN_TX
End of enumeration elements list.
RX : Receive Pin
bits : 7 - 7 (1 bit)
Test
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBCK : Loop Back Mode
bits : 4 - 4 (1 bit)
TX : Control of Transmit Pin
bits : 5 - 6 (2 bit)
Enumeration: TXSelect
0 : CORE
TX controlled by CAN core
1 : SAMPLE
TX monitoring sample point
2 : DOMINANT
Dominant (0) level at pin CAN_TX
3 : RECESSIVE
Recessive (1) level at pin CAN_TX
End of enumeration elements list.
RX : Receive Pin
bits : 7 - 7 (1 bit)
RAM Watchdog
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDC : Watchdog Configuration
bits : 0 - 7 (8 bit)
WDV : Watchdog Value
bits : 8 - 15 (8 bit)
RAM Watchdog
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDC : Watchdog Configuration
bits : 0 - 7 (8 bit)
WDV : Watchdog Value
bits : 8 - 15 (8 bit)
CC Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization
bits : 0 - 0 (1 bit)
CCE : Configuration Change Enable
bits : 1 - 1 (1 bit)
ASM : ASM Restricted Operation Mode
bits : 2 - 2 (1 bit)
CSA : Clock Stop Acknowledge
bits : 3 - 3 (1 bit)
CSR : Clock Stop Request
bits : 4 - 4 (1 bit)
MON : Bus Monitoring Mode
bits : 5 - 5 (1 bit)
DAR : Disable Automatic Retransmission
bits : 6 - 6 (1 bit)
TEST : Test Mode Enable
bits : 7 - 7 (1 bit)
FDOE : FD Operation Enable
bits : 8 - 8 (1 bit)
BRSE : Bit Rate Switch Enable
bits : 9 - 9 (1 bit)
PXHD : Protocol Exception Handling Disable
bits : 12 - 12 (1 bit)
EFBI : Edge Filtering during Bus Integration
bits : 13 - 13 (1 bit)
TXP : Transmit Pause
bits : 14 - 14 (1 bit)
NISO : Non ISO Operation
bits : 15 - 15 (1 bit)
CC Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization
bits : 0 - 0 (1 bit)
CCE : Configuration Change Enable
bits : 1 - 1 (1 bit)
ASM : ASM Restricted Operation Mode
bits : 2 - 2 (1 bit)
CSA : Clock Stop Acknowledge
bits : 3 - 3 (1 bit)
CSR : Clock Stop Request
bits : 4 - 4 (1 bit)
MON : Bus Monitoring Mode
bits : 5 - 5 (1 bit)
DAR : Disable Automatic Retransmission
bits : 6 - 6 (1 bit)
TEST : Test Mode Enable
bits : 7 - 7 (1 bit)
FDOE : FD Operation Enable
bits : 8 - 8 (1 bit)
BRSE : Bit Rate Switch Enable
bits : 9 - 9 (1 bit)
PXHD : Protocol Exception Handling Disable
bits : 12 - 12 (1 bit)
EFBI : Edge Filtering during Bus Integration
bits : 13 - 13 (1 bit)
TXP : Transmit Pause
bits : 14 - 14 (1 bit)
Nominal Bit Timing and Prescaler
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTSEG2 : Nominal Time segment after sample point
bits : 0 - 6 (7 bit)
NTSEG1 : Nominal Time segment before sample point
bits : 8 - 15 (8 bit)
NBRP : Nominal Baud Rate Prescaler
bits : 16 - 24 (9 bit)
NSJW : Nominal (Re)Synchronization Jump Width
bits : 25 - 31 (7 bit)
Nominal Bit Timing and Prescaler
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NTSEG2 : Nominal Time segment after sample point
bits : 0 - 6 (7 bit)
NTSEG1 : Nominal Time segment before sample point
bits : 8 - 15 (8 bit)
NBRP : Nominal Baud Rate Prescaler
bits : 16 - 24 (9 bit)
NSJW : Nominal (Re)Synchronization Jump Width
bits : 25 - 31 (7 bit)
Timestamp Counter Configuration
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Select
bits : 0 - 1 (2 bit)
Enumeration: TSSSelect
0 : ZERO
Timestamp counter value always 0x0000
1 : INC
Timestamp counter value incremented by TCP
2 : EXT
External timestamp counter value used
End of enumeration elements list.
TCP : Timestamp Counter Prescaler
bits : 16 - 19 (4 bit)
Timestamp Counter Configuration
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Select
bits : 0 - 1 (2 bit)
Enumeration: TSSSelect
0 : ZERO
Timestamp counter value always 0x0000
1 : INC
Timestamp counter value incremented by TCP
End of enumeration elements list.
TCP : Timestamp Counter Prescaler
bits : 16 - 19 (4 bit)
Timestamp Counter Value
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSC : Timestamp Counter
bits : 0 - 15 (16 bit)
Timestamp Counter Value
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TSC : Timestamp Counter
bits : 0 - 15 (16 bit)
Timeout Counter Configuration
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
TOS : Timeout Select
bits : 1 - 2 (2 bit)
Enumeration: TOSSelect
0 : CONT
Continuout operation
1 : TXEF
Timeout controlled by TX Event FIFO
2 : RXF0
Timeout controlled by Rx FIFO 0
3 : RXF1
Timeout controlled by Rx FIFO 1
End of enumeration elements list.
TOP : Timeout Period
bits : 16 - 31 (16 bit)
Timeout Counter Configuration
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
TOS : Timeout Select
bits : 1 - 2 (2 bit)
Enumeration: TOSSelect
0 : CONT
Continuout operation
1 : TXEF
Timeout controlled by TX Event FIFO
2 : RXF0
Timeout controlled by Rx FIFO 0
3 : RXF1
Timeout controlled by Rx FIFO 1
End of enumeration elements list.
TOP : Timeout Period
bits : 16 - 31 (16 bit)
Timeout Counter Value
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout Counter
bits : 0 - 15 (16 bit)
Timeout Counter Value
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout Counter
bits : 0 - 15 (16 bit)
Endian
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETV : Endianness Test Value
bits : 0 - 31 (32 bit)
Endian
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ETV : Endianness Test Value
bits : 0 - 31 (32 bit)
Error Counter
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
REC : Receive Error Counter
bits : 8 - 14 (7 bit)
RP : Receive Error Passive
bits : 15 - 15 (1 bit)
CEL : CAN Error Logging
bits : 16 - 23 (8 bit)
Error Counter
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
REC : Receive Error Counter
bits : 8 - 14 (7 bit)
RP : Receive Error Passive
bits : 15 - 15 (1 bit)
CEL : CAN Error Logging
bits : 16 - 23 (8 bit)
Protocol Status
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code
bits : 0 - 2 (3 bit)
Enumeration: LECSelect
0 : NONE
No Error
1 : STUFF
Stuff Error
2 : FORM
Form Error
3 : ACK
Ack Error
4 : BIT1
Bit1 Error
5 : BIT0
Bit0 Error
6 : CRC
CRC Error
7 : NC
No Change
End of enumeration elements list.
ACT : Activity
bits : 3 - 4 (2 bit)
Enumeration: ACTSelect
0 : SYNC
Node is synchronizing on CAN communication
1 : IDLE
Node is neither receiver nor transmitter
2 : RX
Node is operating as receiver
3 : TX
Node is operating as transmitter
End of enumeration elements list.
EP : Error Passive
bits : 5 - 5 (1 bit)
EW : Warning Status
bits : 6 - 6 (1 bit)
BO : Bus_Off Status
bits : 7 - 7 (1 bit)
DLEC : Data Phase Last Error Code
bits : 8 - 10 (3 bit)
Enumeration: DLECSelect
0 : NONE
No Error
1 : STUFF
Stuff Error
2 : FORM
Form Error
3 : ACK
Ack Error
4 : BIT1
Bit1 Error
5 : BIT0
Bit0 Error
6 : CRC
CRC Error
7 : NC
No Change
End of enumeration elements list.
RESI : ESI flag of last received CAN FD Message
bits : 11 - 11 (1 bit)
RBRS : BRS flag of last received CAN FD Message
bits : 12 - 12 (1 bit)
RFDF : Received a CAN FD Message
bits : 13 - 13 (1 bit)
PXE : Protocol Exception Event
bits : 14 - 14 (1 bit)
TDCV : Transmitter Delay Compensation Value
bits : 16 - 22 (7 bit)
Protocol Status
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code
bits : 0 - 2 (3 bit)
Enumeration: LECSelect
0 : NONE
No Error
1 : STUFF
Stuff Error
2 : FORM
Form Error
3 : ACK
Ack Error
4 : BIT1
Bit1 Error
5 : BIT0
Bit0 Error
6 : CRC
CRC Error
7 : NC
No Change
End of enumeration elements list.
ACT : Activity
bits : 3 - 4 (2 bit)
Enumeration: ACTSelect
0 : SYNC
Node is synchronizing on CAN communication
1 : IDLE
Node is neither receiver nor transmitter
2 : RX
Node is operating as receiver
3 : TX
Node is operating as transmitter
End of enumeration elements list.
EP : Error Passive
bits : 5 - 5 (1 bit)
EW : Warning Status
bits : 6 - 6 (1 bit)
BO : Bus_Off Status
bits : 7 - 7 (1 bit)
DLEC : Data Phase Last Error Code
bits : 8 - 10 (3 bit)
Enumeration: DLECSelect
0 : NONE
No Error
1 : STUFF
Stuff Error
2 : FORM
Form Error
3 : ACK
Ack Error
4 : BIT1
Bit1 Error
5 : BIT0
Bit0 Error
6 : CRC
CRC Error
7 : NC
No Change
End of enumeration elements list.
RESI : ESI flag of last received CAN FD Message
bits : 11 - 11 (1 bit)
RBRS : BRS flag of last received CAN FD Message
bits : 12 - 12 (1 bit)
RFDF : Received a CAN FD Message
bits : 13 - 13 (1 bit)
PXE : Protocol Exception Event
bits : 14 - 14 (1 bit)
TDCV : Transmitter Delay Compensation Value
bits : 16 - 22 (7 bit)
Extended ID Filter Configuration
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCF : Transmitter Delay Compensation Filter Length
bits : 0 - 6 (7 bit)
TDCO : Transmitter Delay Compensation Offset
bits : 8 - 14 (7 bit)
Extended ID Filter Configuration
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDCF : Transmitter Delay Compensation Filter Length
bits : 0 - 6 (7 bit)
TDCO : Transmitter Delay Compensation Offset
bits : 8 - 14 (7 bit)
Interrupt
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0N : Rx FIFO 0 New Message
bits : 0 - 0 (1 bit)
RF0W : Rx FIFO 0 Watermark Reached
bits : 1 - 1 (1 bit)
RF0F : Rx FIFO 0 Full
bits : 2 - 2 (1 bit)
RF0L : Rx FIFO 0 Message Lost
bits : 3 - 3 (1 bit)
RF1N : Rx FIFO 1 New Message
bits : 4 - 4 (1 bit)
RF1W : Rx FIFO 1 Watermark Reached
bits : 5 - 5 (1 bit)
RF1F : Rx FIFO 1 FIFO Full
bits : 6 - 6 (1 bit)
RF1L : Rx FIFO 1 Message Lost
bits : 7 - 7 (1 bit)
HPM : High Priority Message
bits : 8 - 8 (1 bit)
TC : Timestamp Completed
bits : 9 - 9 (1 bit)
TCF : Transmission Cancellation Finished
bits : 10 - 10 (1 bit)
TFE : Tx FIFO Empty
bits : 11 - 11 (1 bit)
TEFN : Tx Event FIFO New Entry
bits : 12 - 12 (1 bit)
TEFW : Tx Event FIFO Watermark Reached
bits : 13 - 13 (1 bit)
TEFF : Tx Event FIFO Full
bits : 14 - 14 (1 bit)
TEFL : Tx Event FIFO Element Lost
bits : 15 - 15 (1 bit)
TSW : Timestamp Wraparound
bits : 16 - 16 (1 bit)
MRAF : Message RAM Access Failure
bits : 17 - 17 (1 bit)
TOO : Timeout Occurred
bits : 18 - 18 (1 bit)
DRX : Message stored to Dedicated Rx Buffer
bits : 19 - 19 (1 bit)
BEC : Bit Error Corrected
bits : 20 - 20 (1 bit)
BEU : Bit Error Uncorrected
bits : 21 - 21 (1 bit)
ELO : Error Logging Overflow
bits : 22 - 22 (1 bit)
EP : Error Passive
bits : 23 - 23 (1 bit)
EW : Warning Status
bits : 24 - 24 (1 bit)
BO : Bus_Off Status
bits : 25 - 25 (1 bit)
WDI : Watchdog Interrupt
bits : 26 - 26 (1 bit)
PEA : Protocol Error in Arbitration Phase
bits : 27 - 27 (1 bit)
PED : Protocol Error in Data Phase
bits : 28 - 28 (1 bit)
ARA : Access to Reserved Address
bits : 29 - 29 (1 bit)
Interrupt
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0N : Rx FIFO 0 New Message
bits : 0 - 0 (1 bit)
RF0W : Rx FIFO 0 Watermark Reached
bits : 1 - 1 (1 bit)
RF0F : Rx FIFO 0 Full
bits : 2 - 2 (1 bit)
RF0L : Rx FIFO 0 Message Lost
bits : 3 - 3 (1 bit)
RF1N : Rx FIFO 1 New Message
bits : 4 - 4 (1 bit)
RF1W : Rx FIFO 1 Watermark Reached
bits : 5 - 5 (1 bit)
RF1F : Rx FIFO 1 FIFO Full
bits : 6 - 6 (1 bit)
RF1L : Rx FIFO 1 Message Lost
bits : 7 - 7 (1 bit)
HPM : High Priority Message
bits : 8 - 8 (1 bit)
TC : Timestamp Completed
bits : 9 - 9 (1 bit)
TCF : Transmission Cancellation Finished
bits : 10 - 10 (1 bit)
TFE : Tx FIFO Empty
bits : 11 - 11 (1 bit)
TEFN : Tx Event FIFO New Entry
bits : 12 - 12 (1 bit)
TEFW : Tx Event FIFO Watermark Reached
bits : 13 - 13 (1 bit)
TEFF : Tx Event FIFO Full
bits : 14 - 14 (1 bit)
TEFL : Tx Event FIFO Element Lost
bits : 15 - 15 (1 bit)
TSW : Timestamp Wraparound
bits : 16 - 16 (1 bit)
MRAF : Message RAM Access Failure
bits : 17 - 17 (1 bit)
TOO : Timeout Occurred
bits : 18 - 18 (1 bit)
DRX : Message stored to Dedicated Rx Buffer
bits : 19 - 19 (1 bit)
BEC : Bit Error Corrected
bits : 20 - 20 (1 bit)
BEU : Bit Error Uncorrected
bits : 21 - 21 (1 bit)
ELO : Error Logging Overflow
bits : 22 - 22 (1 bit)
EP : Error Passive
bits : 23 - 23 (1 bit)
EW : Warning Status
bits : 24 - 24 (1 bit)
BO : Bus_Off Status
bits : 25 - 25 (1 bit)
WDI : Watchdog Interrupt
bits : 26 - 26 (1 bit)
PEA : Protocol Error in Arbitration Phase
bits : 27 - 27 (1 bit)
PED : Protocol Error in Data Phase
bits : 28 - 28 (1 bit)
ARA : Access to Reserved Address
bits : 29 - 29 (1 bit)
Interrupt Enable
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NE : Rx FIFO 0 New Message Interrupt Enable
bits : 0 - 0 (1 bit)
RF0WE : Rx FIFO 0 Watermark Reached Interrupt Enable
bits : 1 - 1 (1 bit)
RF0FE : Rx FIFO 0 Full Interrupt Enable
bits : 2 - 2 (1 bit)
RF0LE : Rx FIFO 0 Message Lost Interrupt Enable
bits : 3 - 3 (1 bit)
RF1NE : Rx FIFO 1 New Message Interrupt Enable
bits : 4 - 4 (1 bit)
RF1WE : Rx FIFO 1 Watermark Reached Interrupt Enable
bits : 5 - 5 (1 bit)
RF1FE : Rx FIFO 1 FIFO Full Interrupt Enable
bits : 6 - 6 (1 bit)
RF1LE : Rx FIFO 1 Message Lost Interrupt Enable
bits : 7 - 7 (1 bit)
HPME : High Priority Message Interrupt Enable
bits : 8 - 8 (1 bit)
TCE : Timestamp Completed Interrupt Enable
bits : 9 - 9 (1 bit)
TCFE : Transmission Cancellation Finished Interrupt Enable
bits : 10 - 10 (1 bit)
TFEE : Tx FIFO Empty Interrupt Enable
bits : 11 - 11 (1 bit)
TEFNE : Tx Event FIFO New Entry Interrupt Enable
bits : 12 - 12 (1 bit)
TEFWE : Tx Event FIFO Watermark Reached Interrupt Enable
bits : 13 - 13 (1 bit)
TEFFE : Tx Event FIFO Full Interrupt Enable
bits : 14 - 14 (1 bit)
TEFLE : Tx Event FIFO Element Lost Interrupt Enable
bits : 15 - 15 (1 bit)
TSWE : Timestamp Wraparound Interrupt Enable
bits : 16 - 16 (1 bit)
MRAFE : Message RAM Access Failure Interrupt Enable
bits : 17 - 17 (1 bit)
TOOE : Timeout Occurred Interrupt Enable
bits : 18 - 18 (1 bit)
DRXE : Message stored to Dedicated Rx Buffer Interrupt Enable
bits : 19 - 19 (1 bit)
BECE : Bit Error Corrected Interrupt Enable
bits : 20 - 20 (1 bit)
BEUE : Bit Error Uncorrected Interrupt Enable
bits : 21 - 21 (1 bit)
ELOE : Error Logging Overflow Interrupt Enable
bits : 22 - 22 (1 bit)
EPE : Error Passive Interrupt Enable
bits : 23 - 23 (1 bit)
EWE : Warning Status Interrupt Enable
bits : 24 - 24 (1 bit)
BOE : Bus_Off Status Interrupt Enable
bits : 25 - 25 (1 bit)
WDIE : Watchdog Interrupt Interrupt Enable
bits : 26 - 26 (1 bit)
PEAE : Protocol Error in Arbitration Phase Enable
bits : 27 - 27 (1 bit)
PEDE : Protocol Error in Data Phase Enable
bits : 28 - 28 (1 bit)
ARAE : Access to Reserved Address Enable
bits : 29 - 29 (1 bit)
Interrupt Enable
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NE : Rx FIFO 0 New Message Interrupt Enable
bits : 0 - 0 (1 bit)
RF0WE : Rx FIFO 0 Watermark Reached Interrupt Enable
bits : 1 - 1 (1 bit)
RF0FE : Rx FIFO 0 Full Interrupt Enable
bits : 2 - 2 (1 bit)
RF0LE : Rx FIFO 0 Message Lost Interrupt Enable
bits : 3 - 3 (1 bit)
RF1NE : Rx FIFO 1 New Message Interrupt Enable
bits : 4 - 4 (1 bit)
RF1WE : Rx FIFO 1 Watermark Reached Interrupt Enable
bits : 5 - 5 (1 bit)
RF1FE : Rx FIFO 1 FIFO Full Interrupt Enable
bits : 6 - 6 (1 bit)
RF1LE : Rx FIFO 1 Message Lost Interrupt Enable
bits : 7 - 7 (1 bit)
HPME : High Priority Message Interrupt Enable
bits : 8 - 8 (1 bit)
TCE : Timestamp Completed Interrupt Enable
bits : 9 - 9 (1 bit)
TCFE : Transmission Cancellation Finished Interrupt Enable
bits : 10 - 10 (1 bit)
TFEE : Tx FIFO Empty Interrupt Enable
bits : 11 - 11 (1 bit)
TEFNE : Tx Event FIFO New Entry Interrupt Enable
bits : 12 - 12 (1 bit)
TEFWE : Tx Event FIFO Watermark Reached Interrupt Enable
bits : 13 - 13 (1 bit)
TEFFE : Tx Event FIFO Full Interrupt Enable
bits : 14 - 14 (1 bit)
TEFLE : Tx Event FIFO Element Lost Interrupt Enable
bits : 15 - 15 (1 bit)
TSWE : Timestamp Wraparound Interrupt Enable
bits : 16 - 16 (1 bit)
MRAFE : Message RAM Access Failure Interrupt Enable
bits : 17 - 17 (1 bit)
TOOE : Timeout Occurred Interrupt Enable
bits : 18 - 18 (1 bit)
DRXE : Message stored to Dedicated Rx Buffer Interrupt Enable
bits : 19 - 19 (1 bit)
BECE : Bit Error Corrected Interrupt Enable
bits : 20 - 20 (1 bit)
BEUE : Bit Error Uncorrected Interrupt Enable
bits : 21 - 21 (1 bit)
ELOE : Error Logging Overflow Interrupt Enable
bits : 22 - 22 (1 bit)
EPE : Error Passive Interrupt Enable
bits : 23 - 23 (1 bit)
EWE : Warning Status Interrupt Enable
bits : 24 - 24 (1 bit)
BOE : Bus_Off Status Interrupt Enable
bits : 25 - 25 (1 bit)
WDIE : Watchdog Interrupt Interrupt Enable
bits : 26 - 26 (1 bit)
PEAE : Protocol Error in Arbitration Phase Enable
bits : 27 - 27 (1 bit)
PEDE : Protocol Error in Data Phase Enable
bits : 28 - 28 (1 bit)
ARAE : Access to Reserved Address Enable
bits : 29 - 29 (1 bit)
Interrupt Line Select
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 1 (1 bit)
RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 2 (1 bit)
RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 3 (1 bit)
RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 4 (1 bit)
RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 5 (1 bit)
RF1FL : Rx FIFO 1 FIFO Full Interrupt Line
bits : 6 - 6 (1 bit)
RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 7 (1 bit)
HPML : High Priority Message Interrupt Line
bits : 8 - 8 (1 bit)
TCL : Timestamp Completed Interrupt Line
bits : 9 - 9 (1 bit)
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 10 (1 bit)
TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 11 (1 bit)
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 12 (1 bit)
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 13 (1 bit)
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 14 (1 bit)
TEFLL : Tx Event FIFO Element Lost Interrupt Line
bits : 15 - 15 (1 bit)
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 16 (1 bit)
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 17 (1 bit)
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 18 (1 bit)
DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 19 (1 bit)
BECL : Bit Error Corrected Interrupt Line
bits : 20 - 20 (1 bit)
BEUL : Bit Error Uncorrected Interrupt Line
bits : 21 - 21 (1 bit)
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 22 (1 bit)
EPL : Error Passive Interrupt Line
bits : 23 - 23 (1 bit)
EWL : Warning Status Interrupt Line
bits : 24 - 24 (1 bit)
BOL : Bus_Off Status Interrupt Line
bits : 25 - 25 (1 bit)
WDIL : Watchdog Interrupt Interrupt Line
bits : 26 - 26 (1 bit)
PEAL : Protocol Error in Arbitration Phase Line
bits : 27 - 27 (1 bit)
PEDL : Protocol Error in Data Phase Line
bits : 28 - 28 (1 bit)
ARAL : Access to Reserved Address Line
bits : 29 - 29 (1 bit)
Interrupt Line Select
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NL : Rx FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
RF0WL : Rx FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 1 (1 bit)
RF0FL : Rx FIFO 0 Full Interrupt Line
bits : 2 - 2 (1 bit)
RF0LL : Rx FIFO 0 Message Lost Interrupt Line
bits : 3 - 3 (1 bit)
RF1NL : Rx FIFO 1 New Message Interrupt Line
bits : 4 - 4 (1 bit)
RF1WL : Rx FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 5 (1 bit)
RF1FL : Rx FIFO 1 FIFO Full Interrupt Line
bits : 6 - 6 (1 bit)
RF1LL : Rx FIFO 1 Message Lost Interrupt Line
bits : 7 - 7 (1 bit)
HPML : High Priority Message Interrupt Line
bits : 8 - 8 (1 bit)
TCL : Timestamp Completed Interrupt Line
bits : 9 - 9 (1 bit)
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 10 (1 bit)
TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 11 (1 bit)
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 12 (1 bit)
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 13 (1 bit)
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 14 (1 bit)
TEFLL : Tx Event FIFO Element Lost Interrupt Line
bits : 15 - 15 (1 bit)
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 16 (1 bit)
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 17 (1 bit)
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 18 (1 bit)
DRXL : Message stored to Dedicated Rx Buffer Interrupt Line
bits : 19 - 19 (1 bit)
BECL : Bit Error Corrected Interrupt Line
bits : 20 - 20 (1 bit)
BEUL : Bit Error Uncorrected Interrupt Line
bits : 21 - 21 (1 bit)
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 22 (1 bit)
EPL : Error Passive Interrupt Line
bits : 23 - 23 (1 bit)
EWL : Warning Status Interrupt Line
bits : 24 - 24 (1 bit)
BOL : Bus_Off Status Interrupt Line
bits : 25 - 25 (1 bit)
WDIL : Watchdog Interrupt Interrupt Line
bits : 26 - 26 (1 bit)
PEAL : Protocol Error in Arbitration Phase Line
bits : 27 - 27 (1 bit)
PEDL : Protocol Error in Data Phase Line
bits : 28 - 28 (1 bit)
ARAL : Access to Reserved Address Line
bits : 29 - 29 (1 bit)
Interrupt Line Enable
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EINT0 : Enable Interrupt Line 0
bits : 0 - 0 (1 bit)
EINT1 : Enable Interrupt Line 1
bits : 1 - 1 (1 bit)
Interrupt Line Enable
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EINT0 : Enable Interrupt Line 0
bits : 0 - 0 (1 bit)
EINT1 : Enable Interrupt Line 1
bits : 1 - 1 (1 bit)
Message RAM Configuration
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QOS : Quality of Service
bits : 0 - 1 (2 bit)
Enumeration: QOSSelect
0 : DISABLE
Background (no sensitive operation)
1 : LOW
Sensitive Bandwidth
2 : MEDIUM
Sensitive Latency
3 : HIGH
Critical Latency
End of enumeration elements list.
Message RAM Configuration
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QOS : Quality of Service
bits : 0 - 1 (2 bit)
Enumeration: QOSSelect
0 : DISABLE
Background (no sensitive operation)
1 : LOW
Sensitive Bandwidth
2 : MEDIUM
Sensitive Latency
3 : HIGH
Critical Latency
End of enumeration elements list.
Global Filter Configuration
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFE : Reject Remote Frames Extended
bits : 0 - 0 (1 bit)
RRFS : Reject Remote Frames Standard
bits : 1 - 1 (1 bit)
ANFE : Accept Non-matching Frames Extended
bits : 2 - 3 (2 bit)
Enumeration: ANFESelect
0 : RXF0
Accept in Rx FIFO 0
1 : RXF1
Accept in Rx FIFO 1
2 : REJECT
Reject
End of enumeration elements list.
ANFS : Accept Non-matching Frames Standard
bits : 4 - 5 (2 bit)
Enumeration: ANFSSelect
0 : RXF0
Accept in Rx FIFO 0
1 : RXF1
Accept in Rx FIFO 1
2 : REJECT
Reject
End of enumeration elements list.
Global Filter Configuration
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFE : Reject Remote Frames Extended
bits : 0 - 0 (1 bit)
RRFS : Reject Remote Frames Standard
bits : 1 - 1 (1 bit)
ANFE : Accept Non-matching Frames Extended
bits : 2 - 3 (2 bit)
Enumeration: ANFESelect
0 : RXF0
Accept in Rx FIFO 0
1 : RXF1
Accept in Rx FIFO 1
2 : REJECT
Reject
End of enumeration elements list.
ANFS : Accept Non-matching Frames Standard
bits : 4 - 5 (2 bit)
Enumeration: ANFSSelect
0 : RXF0
Accept in Rx FIFO 0
1 : RXF1
Accept in Rx FIFO 1
2 : REJECT
Reject
End of enumeration elements list.
Standard ID Filter Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSSA : Filter List Standard Start Address
bits : 0 - 15 (16 bit)
LSS : List Size Standard
bits : 16 - 23 (8 bit)
Standard ID Filter Configuration
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSSA : Filter List Standard Start Address
bits : 0 - 15 (16 bit)
LSS : List Size Standard
bits : 16 - 23 (8 bit)
Extended ID Filter Configuration
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLESA : Filter List Extended Start Address
bits : 0 - 15 (16 bit)
LSE : List Size Extended
bits : 16 - 22 (7 bit)
Extended ID Filter Configuration
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLESA : Filter List Extended Start Address
bits : 0 - 15 (16 bit)
LSE : List Size Extended
bits : 16 - 22 (7 bit)
Extended ID AND Mask
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIDM : Extended ID Mask
bits : 0 - 28 (29 bit)
Extended ID AND Mask
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIDM : Extended ID Mask
bits : 0 - 28 (29 bit)
High Priority Message Status
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : Buffer Index
bits : 0 - 5 (6 bit)
MSI : Message Storage Indicator
bits : 6 - 7 (2 bit)
Enumeration: MSISelect
0 : NONE
No FIFO selected
1 : LOST
FIFO message lost
2 : FIFO0
Message stored in FIFO 0
3 : FIFO1
Message stored in FIFO 1
End of enumeration elements list.
FIDX : Filter Index
bits : 8 - 14 (7 bit)
FLST : Filter List
bits : 15 - 15 (1 bit)
High Priority Message Status
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : Buffer Index
bits : 0 - 5 (6 bit)
MSI : Message Storage Indicator
bits : 6 - 7 (2 bit)
Enumeration: MSISelect
0 : NONE
No FIFO selected
1 : LOST
FIFO message lost
2 : FIFO0
Message stored in FIFO 0
3 : FIFO1
Message stored in FIFO 1
End of enumeration elements list.
FIDX : Filter Index
bits : 8 - 14 (7 bit)
FLST : Filter List
bits : 15 - 15 (1 bit)
New Data 1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND0 : New Data 0
bits : 0 - 0 (1 bit)
ND1 : New Data 1
bits : 1 - 1 (1 bit)
ND2 : New Data 2
bits : 2 - 2 (1 bit)
ND3 : New Data 3
bits : 3 - 3 (1 bit)
ND4 : New Data 4
bits : 4 - 4 (1 bit)
ND5 : New Data 5
bits : 5 - 5 (1 bit)
ND6 : New Data 6
bits : 6 - 6 (1 bit)
ND7 : New Data 7
bits : 7 - 7 (1 bit)
ND8 : New Data 8
bits : 8 - 8 (1 bit)
ND9 : New Data 9
bits : 9 - 9 (1 bit)
ND10 : New Data 10
bits : 10 - 10 (1 bit)
ND11 : New Data 11
bits : 11 - 11 (1 bit)
ND12 : New Data 12
bits : 12 - 12 (1 bit)
ND13 : New Data 13
bits : 13 - 13 (1 bit)
ND14 : New Data 14
bits : 14 - 14 (1 bit)
ND15 : New Data 15
bits : 15 - 15 (1 bit)
ND16 : New Data 16
bits : 16 - 16 (1 bit)
ND17 : New Data 17
bits : 17 - 17 (1 bit)
ND18 : New Data 18
bits : 18 - 18 (1 bit)
ND19 : New Data 19
bits : 19 - 19 (1 bit)
ND20 : New Data 20
bits : 20 - 20 (1 bit)
ND21 : New Data 21
bits : 21 - 21 (1 bit)
ND22 : New Data 22
bits : 22 - 22 (1 bit)
ND23 : New Data 23
bits : 23 - 23 (1 bit)
ND24 : New Data 24
bits : 24 - 24 (1 bit)
ND25 : New Data 25
bits : 25 - 25 (1 bit)
ND26 : New Data 26
bits : 26 - 26 (1 bit)
ND27 : New Data 27
bits : 27 - 27 (1 bit)
ND28 : New Data 28
bits : 28 - 28 (1 bit)
ND29 : New Data 29
bits : 29 - 29 (1 bit)
ND30 : New Data 30
bits : 30 - 30 (1 bit)
ND31 : New Data 31
bits : 31 - 31 (1 bit)
New Data 1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND0 : New Data 0
bits : 0 - 0 (1 bit)
ND1 : New Data 1
bits : 1 - 1 (1 bit)
ND2 : New Data 2
bits : 2 - 2 (1 bit)
ND3 : New Data 3
bits : 3 - 3 (1 bit)
ND4 : New Data 4
bits : 4 - 4 (1 bit)
ND5 : New Data 5
bits : 5 - 5 (1 bit)
ND6 : New Data 6
bits : 6 - 6 (1 bit)
ND7 : New Data 7
bits : 7 - 7 (1 bit)
ND8 : New Data 8
bits : 8 - 8 (1 bit)
ND9 : New Data 9
bits : 9 - 9 (1 bit)
ND10 : New Data 10
bits : 10 - 10 (1 bit)
ND11 : New Data 11
bits : 11 - 11 (1 bit)
ND12 : New Data 12
bits : 12 - 12 (1 bit)
ND13 : New Data 13
bits : 13 - 13 (1 bit)
ND14 : New Data 14
bits : 14 - 14 (1 bit)
ND15 : New Data 15
bits : 15 - 15 (1 bit)
ND16 : New Data 16
bits : 16 - 16 (1 bit)
ND17 : New Data 17
bits : 17 - 17 (1 bit)
ND18 : New Data 18
bits : 18 - 18 (1 bit)
ND19 : New Data 19
bits : 19 - 19 (1 bit)
ND20 : New Data 20
bits : 20 - 20 (1 bit)
ND21 : New Data 21
bits : 21 - 21 (1 bit)
ND22 : New Data 22
bits : 22 - 22 (1 bit)
ND23 : New Data 23
bits : 23 - 23 (1 bit)
ND24 : New Data 24
bits : 24 - 24 (1 bit)
ND25 : New Data 25
bits : 25 - 25 (1 bit)
ND26 : New Data 26
bits : 26 - 26 (1 bit)
ND27 : New Data 27
bits : 27 - 27 (1 bit)
ND28 : New Data 28
bits : 28 - 28 (1 bit)
ND29 : New Data 29
bits : 29 - 29 (1 bit)
ND30 : New Data 30
bits : 30 - 30 (1 bit)
ND31 : New Data 31
bits : 31 - 31 (1 bit)
New Data 2
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND32 : New Data 32
bits : 0 - 0 (1 bit)
ND33 : New Data 33
bits : 1 - 1 (1 bit)
ND34 : New Data 34
bits : 2 - 2 (1 bit)
ND35 : New Data 35
bits : 3 - 3 (1 bit)
ND36 : New Data 36
bits : 4 - 4 (1 bit)
ND37 : New Data 37
bits : 5 - 5 (1 bit)
ND38 : New Data 38
bits : 6 - 6 (1 bit)
ND39 : New Data 39
bits : 7 - 7 (1 bit)
ND40 : New Data 40
bits : 8 - 8 (1 bit)
ND41 : New Data 41
bits : 9 - 9 (1 bit)
ND42 : New Data 42
bits : 10 - 10 (1 bit)
ND43 : New Data 43
bits : 11 - 11 (1 bit)
ND44 : New Data 44
bits : 12 - 12 (1 bit)
ND45 : New Data 45
bits : 13 - 13 (1 bit)
ND46 : New Data 46
bits : 14 - 14 (1 bit)
ND47 : New Data 47
bits : 15 - 15 (1 bit)
ND48 : New Data 48
bits : 16 - 16 (1 bit)
ND49 : New Data 49
bits : 17 - 17 (1 bit)
ND50 : New Data 50
bits : 18 - 18 (1 bit)
ND51 : New Data 51
bits : 19 - 19 (1 bit)
ND52 : New Data 52
bits : 20 - 20 (1 bit)
ND53 : New Data 53
bits : 21 - 21 (1 bit)
ND54 : New Data 54
bits : 22 - 22 (1 bit)
ND55 : New Data 55
bits : 23 - 23 (1 bit)
ND56 : New Data 56
bits : 24 - 24 (1 bit)
ND57 : New Data 57
bits : 25 - 25 (1 bit)
ND58 : New Data 58
bits : 26 - 26 (1 bit)
ND59 : New Data 59
bits : 27 - 27 (1 bit)
ND60 : New Data 60
bits : 28 - 28 (1 bit)
ND61 : New Data 61
bits : 29 - 29 (1 bit)
ND62 : New Data 62
bits : 30 - 30 (1 bit)
ND63 : New Data 63
bits : 31 - 31 (1 bit)
New Data 2
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND32 : New Data 32
bits : 0 - 0 (1 bit)
ND33 : New Data 33
bits : 1 - 1 (1 bit)
ND34 : New Data 34
bits : 2 - 2 (1 bit)
ND35 : New Data 35
bits : 3 - 3 (1 bit)
ND36 : New Data 36
bits : 4 - 4 (1 bit)
ND37 : New Data 37
bits : 5 - 5 (1 bit)
ND38 : New Data 38
bits : 6 - 6 (1 bit)
ND39 : New Data 39
bits : 7 - 7 (1 bit)
ND40 : New Data 40
bits : 8 - 8 (1 bit)
ND41 : New Data 41
bits : 9 - 9 (1 bit)
ND42 : New Data 42
bits : 10 - 10 (1 bit)
ND43 : New Data 43
bits : 11 - 11 (1 bit)
ND44 : New Data 44
bits : 12 - 12 (1 bit)
ND45 : New Data 45
bits : 13 - 13 (1 bit)
ND46 : New Data 46
bits : 14 - 14 (1 bit)
ND47 : New Data 47
bits : 15 - 15 (1 bit)
ND48 : New Data 48
bits : 16 - 16 (1 bit)
ND49 : New Data 49
bits : 17 - 17 (1 bit)
ND50 : New Data 50
bits : 18 - 18 (1 bit)
ND51 : New Data 51
bits : 19 - 19 (1 bit)
ND52 : New Data 52
bits : 20 - 20 (1 bit)
ND53 : New Data 53
bits : 21 - 21 (1 bit)
ND54 : New Data 54
bits : 22 - 22 (1 bit)
ND55 : New Data 55
bits : 23 - 23 (1 bit)
ND56 : New Data 56
bits : 24 - 24 (1 bit)
ND57 : New Data 57
bits : 25 - 25 (1 bit)
ND58 : New Data 58
bits : 26 - 26 (1 bit)
ND59 : New Data 59
bits : 27 - 27 (1 bit)
ND60 : New Data 60
bits : 28 - 28 (1 bit)
ND61 : New Data 61
bits : 29 - 29 (1 bit)
ND62 : New Data 62
bits : 30 - 30 (1 bit)
ND63 : New Data 63
bits : 31 - 31 (1 bit)
Rx FIFO 0 Configuration
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0SA : Rx FIFO 0 Start Address
bits : 0 - 15 (16 bit)
F0S : Rx FIFO 0 Size
bits : 16 - 22 (7 bit)
F0WM : Rx FIFO 0 Watermark
bits : 24 - 30 (7 bit)
F0OM : FIFO 0 Operation Mode
bits : 31 - 31 (1 bit)
Rx FIFO 0 Configuration
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0SA : Rx FIFO 0 Start Address
bits : 0 - 15 (16 bit)
F0S : Rx FIFO 0 Size
bits : 16 - 22 (7 bit)
F0WM : Rx FIFO 0 Watermark
bits : 24 - 30 (7 bit)
F0OM : FIFO 0 Operation Mode
bits : 31 - 31 (1 bit)
Rx FIFO 0 Status
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F0FL : Rx FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
F0GI : Rx FIFO 0 Get Index
bits : 8 - 13 (6 bit)
F0PI : Rx FIFO 0 Put Index
bits : 16 - 21 (6 bit)
F0F : Rx FIFO 0 Full
bits : 24 - 24 (1 bit)
RF0L : Rx FIFO 0 Message Lost
bits : 25 - 25 (1 bit)
Rx FIFO 0 Status
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F0FL : Rx FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
F0GI : Rx FIFO 0 Get Index
bits : 8 - 13 (6 bit)
F0PI : Rx FIFO 0 Put Index
bits : 16 - 21 (6 bit)
F0F : Rx FIFO 0 Full
bits : 24 - 24 (1 bit)
RF0L : Rx FIFO 0 Message Lost
bits : 25 - 25 (1 bit)
Rx FIFO 0 Acknowledge
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0AI : Rx FIFO 0 Acknowledge Index
bits : 0 - 5 (6 bit)
Rx FIFO 0 Acknowledge
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0AI : Rx FIFO 0 Acknowledge Index
bits : 0 - 5 (6 bit)
Rx Buffer Configuration
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBSA : Rx Buffer Start Address
bits : 0 - 15 (16 bit)
Rx Buffer Configuration
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBSA : Rx Buffer Start Address
bits : 0 - 15 (16 bit)
Rx FIFO 1 Configuration
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1SA : Rx FIFO 1 Start Address
bits : 0 - 15 (16 bit)
F1S : Rx FIFO 1 Size
bits : 16 - 22 (7 bit)
F1WM : Rx FIFO 1 Watermark
bits : 24 - 30 (7 bit)
F1OM : FIFO 1 Operation Mode
bits : 31 - 31 (1 bit)
Rx FIFO 1 Configuration
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1SA : Rx FIFO 1 Start Address
bits : 0 - 15 (16 bit)
F1S : Rx FIFO 1 Size
bits : 16 - 22 (7 bit)
F1WM : Rx FIFO 1 Watermark
bits : 24 - 30 (7 bit)
F1OM : FIFO 1 Operation Mode
bits : 31 - 31 (1 bit)
Rx FIFO 1 Status
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F1FL : Rx FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
F1GI : Rx FIFO 1 Get Index
bits : 8 - 13 (6 bit)
F1PI : Rx FIFO 1 Put Index
bits : 16 - 21 (6 bit)
F1F : Rx FIFO 1 Full
bits : 24 - 24 (1 bit)
RF1L : Rx FIFO 1 Message Lost
bits : 25 - 25 (1 bit)
DMS : Debug Message Status
bits : 30 - 31 (2 bit)
Enumeration: DMSSelect
0 : IDLE
Idle state
1 : DBGA
Debug message A received
2 : DBGB
Debug message A/B received
3 : DBGC
Debug message A/B/C received, DMA request set
End of enumeration elements list.
Rx FIFO 1 Status
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F1FL : Rx FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
F1GI : Rx FIFO 1 Get Index
bits : 8 - 13 (6 bit)
F1PI : Rx FIFO 1 Put Index
bits : 16 - 21 (6 bit)
F1F : Rx FIFO 1 Full
bits : 24 - 24 (1 bit)
RF1L : Rx FIFO 1 Message Lost
bits : 25 - 25 (1 bit)
DMS : Debug Message Status
bits : 30 - 31 (2 bit)
Enumeration: DMSSelect
0 : IDLE
Idle state
1 : DBGA
Debug message A received
2 : DBGB
Debug message A/B received
3 : DBGC
Debug message A/B/C received, DMA request set
End of enumeration elements list.
Rx FIFO 1 Acknowledge
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
Rx FIFO 1 Acknowledge
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
Rx Buffer / FIFO Element Size Configuration
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DS : Rx FIFO 0 Data Field Size
bits : 0 - 2 (3 bit)
Enumeration: F0DSSelect
0 : DATA8
8 byte data field
1 : DATA12
12 byte data field
2 : DATA16
16 byte data field
3 : DATA20
20 byte data field
4 : DATA24
24 byte data field
5 : DATA32
32 byte data field
6 : DATA48
48 byte data field
7 : DATA64
64 byte data field
End of enumeration elements list.
F1DS : Rx FIFO 1 Data Field Size
bits : 4 - 6 (3 bit)
Enumeration: F1DSSelect
0 : DATA8
8 byte data field
1 : DATA12
12 byte data field
2 : DATA16
16 byte data field
3 : DATA20
20 byte data field
4 : DATA24
24 byte data field
5 : DATA32
32 byte data field
6 : DATA48
48 byte data field
7 : DATA64
64 byte data field
End of enumeration elements list.
RBDS : Rx Buffer Data Field Size
bits : 8 - 10 (3 bit)
Enumeration: RBDSSelect
0 : DATA8
8 byte data field
1 : DATA12
12 byte data field
2 : DATA16
16 byte data field
3 : DATA20
20 byte data field
4 : DATA24
24 byte data field
5 : DATA32
32 byte data field
6 : DATA48
48 byte data field
7 : DATA64
64 byte data field
End of enumeration elements list.
Rx Buffer / FIFO Element Size Configuration
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DS : Rx FIFO 0 Data Field Size
bits : 0 - 2 (3 bit)
Enumeration: F0DSSelect
0 : DATA8
8 byte data field
1 : DATA12
12 byte data field
2 : DATA16
16 byte data field
3 : DATA20
20 byte data field
4 : DATA24
24 byte data field
5 : DATA32
32 byte data field
6 : DATA48
48 byte data field
7 : DATA64
64 byte data field
End of enumeration elements list.
F1DS : Rx FIFO 1 Data Field Size
bits : 4 - 6 (3 bit)
Enumeration: F1DSSelect
0 : DATA8
8 byte data field
1 : DATA12
12 byte data field
2 : DATA16
16 byte data field
3 : DATA20
20 byte data field
4 : DATA24
24 byte data field
5 : DATA32
32 byte data field
6 : DATA48
48 byte data field
7 : DATA64
64 byte data field
End of enumeration elements list.
RBDS : Rx Buffer Data Field Size
bits : 8 - 10 (3 bit)
Enumeration: RBDSSelect
0 : DATA8
8 byte data field
1 : DATA12
12 byte data field
2 : DATA16
16 byte data field
3 : DATA20
20 byte data field
4 : DATA24
24 byte data field
5 : DATA32
32 byte data field
6 : DATA48
48 byte data field
7 : DATA64
64 byte data field
End of enumeration elements list.
Fast Bit Timing and Prescaler
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSJW : Data (Re)Synchronization Jump Width
bits : 0 - 3 (4 bit)
DTSEG2 : Data time segment after sample point
bits : 4 - 7 (4 bit)
DTSEG1 : Data time segment before sample point
bits : 8 - 12 (5 bit)
DBRP : Data Baud Rate Prescaler
bits : 16 - 20 (5 bit)
TDC : Tranceiver Delay Compensation
bits : 23 - 23 (1 bit)
Fast Bit Timing and Prescaler
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSJW : Data (Re)Synchronization Jump Width
bits : 0 - 3 (4 bit)
DTSEG2 : Data time segment after sample point
bits : 4 - 7 (4 bit)
DTSEG1 : Data time segment before sample point
bits : 8 - 12 (5 bit)
DBRP : Data Baud Rate Prescaler
bits : 16 - 20 (5 bit)
TDC : Tranceiver Delay Compensation
bits : 23 - 23 (1 bit)
Tx Buffer Configuration
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBSA : Tx Buffers Start Address
bits : 0 - 15 (16 bit)
NDTB : Number of Dedicated Transmit Buffers
bits : 16 - 21 (6 bit)
TFQS : Transmit FIFO/Queue Size
bits : 24 - 29 (6 bit)
TFQM : Tx FIFO/Queue Mode
bits : 30 - 30 (1 bit)
Tx Buffer Configuration
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBSA : Tx Buffers Start Address
bits : 0 - 15 (16 bit)
NDTB : Number of Dedicated Transmit Buffers
bits : 16 - 21 (6 bit)
TFQS : Transmit FIFO/Queue Size
bits : 24 - 29 (6 bit)
TFQM : Tx FIFO/Queue Mode
bits : 30 - 30 (1 bit)
Tx FIFO / Queue Status
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
TFGI : Tx FIFO Get Index
bits : 8 - 12 (5 bit)
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 20 (5 bit)
TFQF : Tx FIFO/Queue Full
bits : 21 - 21 (1 bit)
Tx FIFO / Queue Status
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
TFGI : Tx FIFO Get Index
bits : 8 - 12 (5 bit)
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 20 (5 bit)
TFQF : Tx FIFO/Queue Full
bits : 21 - 21 (1 bit)
Tx Buffer Element Size Configuration
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBDS : Tx Buffer Data Field Size
bits : 0 - 2 (3 bit)
Enumeration: TBDSSelect
0 : DATA8
8 byte data field
1 : DATA12
12 byte data field
2 : DATA16
16 byte data field
3 : DATA20
20 byte data field
4 : DATA24
24 byte data field
5 : DATA32
32 byte data field
6 : DATA48
48 byte data field
7 : DATA64
64 byte data field
End of enumeration elements list.
Tx Buffer Element Size Configuration
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBDS : Tx Buffer Data Field Size
bits : 0 - 2 (3 bit)
Enumeration: TBDSSelect
0 : DATA8
8 byte data field
1 : DATA12
12 byte data field
2 : DATA16
16 byte data field
3 : DATA20
20 byte data field
4 : DATA24
24 byte data field
5 : DATA32
32 byte data field
6 : DATA48
48 byte data field
7 : DATA64
64 byte data field
End of enumeration elements list.
Tx Buffer Request Pending
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRP0 : Transmission Request Pending 0
bits : 0 - 0 (1 bit)
TRP1 : Transmission Request Pending 1
bits : 1 - 1 (1 bit)
TRP2 : Transmission Request Pending 2
bits : 2 - 2 (1 bit)
TRP3 : Transmission Request Pending 3
bits : 3 - 3 (1 bit)
TRP4 : Transmission Request Pending 4
bits : 4 - 4 (1 bit)
TRP5 : Transmission Request Pending 5
bits : 5 - 5 (1 bit)
TRP6 : Transmission Request Pending 6
bits : 6 - 6 (1 bit)
TRP7 : Transmission Request Pending 7
bits : 7 - 7 (1 bit)
TRP8 : Transmission Request Pending 8
bits : 8 - 8 (1 bit)
TRP9 : Transmission Request Pending 9
bits : 9 - 9 (1 bit)
TRP10 : Transmission Request Pending 10
bits : 10 - 10 (1 bit)
TRP11 : Transmission Request Pending 11
bits : 11 - 11 (1 bit)
TRP12 : Transmission Request Pending 12
bits : 12 - 12 (1 bit)
TRP13 : Transmission Request Pending 13
bits : 13 - 13 (1 bit)
TRP14 : Transmission Request Pending 14
bits : 14 - 14 (1 bit)
TRP15 : Transmission Request Pending 15
bits : 15 - 15 (1 bit)
TRP16 : Transmission Request Pending 16
bits : 16 - 16 (1 bit)
TRP17 : Transmission Request Pending 17
bits : 17 - 17 (1 bit)
TRP18 : Transmission Request Pending 18
bits : 18 - 18 (1 bit)
TRP19 : Transmission Request Pending 19
bits : 19 - 19 (1 bit)
TRP20 : Transmission Request Pending 20
bits : 20 - 20 (1 bit)
TRP21 : Transmission Request Pending 21
bits : 21 - 21 (1 bit)
TRP22 : Transmission Request Pending 22
bits : 22 - 22 (1 bit)
TRP23 : Transmission Request Pending 23
bits : 23 - 23 (1 bit)
TRP24 : Transmission Request Pending 24
bits : 24 - 24 (1 bit)
TRP25 : Transmission Request Pending 25
bits : 25 - 25 (1 bit)
TRP26 : Transmission Request Pending 26
bits : 26 - 26 (1 bit)
TRP27 : Transmission Request Pending 27
bits : 27 - 27 (1 bit)
TRP28 : Transmission Request Pending 28
bits : 28 - 28 (1 bit)
TRP29 : Transmission Request Pending 29
bits : 29 - 29 (1 bit)
TRP30 : Transmission Request Pending 30
bits : 30 - 30 (1 bit)
TRP31 : Transmission Request Pending 31
bits : 31 - 31 (1 bit)
Tx Buffer Request Pending
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRP0 : Transmission Request Pending 0
bits : 0 - 0 (1 bit)
TRP1 : Transmission Request Pending 1
bits : 1 - 1 (1 bit)
TRP2 : Transmission Request Pending 2
bits : 2 - 2 (1 bit)
TRP3 : Transmission Request Pending 3
bits : 3 - 3 (1 bit)
TRP4 : Transmission Request Pending 4
bits : 4 - 4 (1 bit)
TRP5 : Transmission Request Pending 5
bits : 5 - 5 (1 bit)
TRP6 : Transmission Request Pending 6
bits : 6 - 6 (1 bit)
TRP7 : Transmission Request Pending 7
bits : 7 - 7 (1 bit)
TRP8 : Transmission Request Pending 8
bits : 8 - 8 (1 bit)
TRP9 : Transmission Request Pending 9
bits : 9 - 9 (1 bit)
TRP10 : Transmission Request Pending 10
bits : 10 - 10 (1 bit)
TRP11 : Transmission Request Pending 11
bits : 11 - 11 (1 bit)
TRP12 : Transmission Request Pending 12
bits : 12 - 12 (1 bit)
TRP13 : Transmission Request Pending 13
bits : 13 - 13 (1 bit)
TRP14 : Transmission Request Pending 14
bits : 14 - 14 (1 bit)
TRP15 : Transmission Request Pending 15
bits : 15 - 15 (1 bit)
TRP16 : Transmission Request Pending 16
bits : 16 - 16 (1 bit)
TRP17 : Transmission Request Pending 17
bits : 17 - 17 (1 bit)
TRP18 : Transmission Request Pending 18
bits : 18 - 18 (1 bit)
TRP19 : Transmission Request Pending 19
bits : 19 - 19 (1 bit)
TRP20 : Transmission Request Pending 20
bits : 20 - 20 (1 bit)
TRP21 : Transmission Request Pending 21
bits : 21 - 21 (1 bit)
TRP22 : Transmission Request Pending 22
bits : 22 - 22 (1 bit)
TRP23 : Transmission Request Pending 23
bits : 23 - 23 (1 bit)
TRP24 : Transmission Request Pending 24
bits : 24 - 24 (1 bit)
TRP25 : Transmission Request Pending 25
bits : 25 - 25 (1 bit)
TRP26 : Transmission Request Pending 26
bits : 26 - 26 (1 bit)
TRP27 : Transmission Request Pending 27
bits : 27 - 27 (1 bit)
TRP28 : Transmission Request Pending 28
bits : 28 - 28 (1 bit)
TRP29 : Transmission Request Pending 29
bits : 29 - 29 (1 bit)
TRP30 : Transmission Request Pending 30
bits : 30 - 30 (1 bit)
TRP31 : Transmission Request Pending 31
bits : 31 - 31 (1 bit)
Tx Buffer Add Request
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR0 : Add Request 0
bits : 0 - 0 (1 bit)
AR1 : Add Request 1
bits : 1 - 1 (1 bit)
AR2 : Add Request 2
bits : 2 - 2 (1 bit)
AR3 : Add Request 3
bits : 3 - 3 (1 bit)
AR4 : Add Request 4
bits : 4 - 4 (1 bit)
AR5 : Add Request 5
bits : 5 - 5 (1 bit)
AR6 : Add Request 6
bits : 6 - 6 (1 bit)
AR7 : Add Request 7
bits : 7 - 7 (1 bit)
AR8 : Add Request 8
bits : 8 - 8 (1 bit)
AR9 : Add Request 9
bits : 9 - 9 (1 bit)
AR10 : Add Request 10
bits : 10 - 10 (1 bit)
AR11 : Add Request 11
bits : 11 - 11 (1 bit)
AR12 : Add Request 12
bits : 12 - 12 (1 bit)
AR13 : Add Request 13
bits : 13 - 13 (1 bit)
AR14 : Add Request 14
bits : 14 - 14 (1 bit)
AR15 : Add Request 15
bits : 15 - 15 (1 bit)
AR16 : Add Request 16
bits : 16 - 16 (1 bit)
AR17 : Add Request 17
bits : 17 - 17 (1 bit)
AR18 : Add Request 18
bits : 18 - 18 (1 bit)
AR19 : Add Request 19
bits : 19 - 19 (1 bit)
AR20 : Add Request 20
bits : 20 - 20 (1 bit)
AR21 : Add Request 21
bits : 21 - 21 (1 bit)
AR22 : Add Request 22
bits : 22 - 22 (1 bit)
AR23 : Add Request 23
bits : 23 - 23 (1 bit)
AR24 : Add Request 24
bits : 24 - 24 (1 bit)
AR25 : Add Request 25
bits : 25 - 25 (1 bit)
AR26 : Add Request 26
bits : 26 - 26 (1 bit)
AR27 : Add Request 27
bits : 27 - 27 (1 bit)
AR28 : Add Request 28
bits : 28 - 28 (1 bit)
AR29 : Add Request 29
bits : 29 - 29 (1 bit)
AR30 : Add Request 30
bits : 30 - 30 (1 bit)
AR31 : Add Request 31
bits : 31 - 31 (1 bit)
Tx Buffer Add Request
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR0 : Add Request 0
bits : 0 - 0 (1 bit)
AR1 : Add Request 1
bits : 1 - 1 (1 bit)
AR2 : Add Request 2
bits : 2 - 2 (1 bit)
AR3 : Add Request 3
bits : 3 - 3 (1 bit)
AR4 : Add Request 4
bits : 4 - 4 (1 bit)
AR5 : Add Request 5
bits : 5 - 5 (1 bit)
AR6 : Add Request 6
bits : 6 - 6 (1 bit)
AR7 : Add Request 7
bits : 7 - 7 (1 bit)
AR8 : Add Request 8
bits : 8 - 8 (1 bit)
AR9 : Add Request 9
bits : 9 - 9 (1 bit)
AR10 : Add Request 10
bits : 10 - 10 (1 bit)
AR11 : Add Request 11
bits : 11 - 11 (1 bit)
AR12 : Add Request 12
bits : 12 - 12 (1 bit)
AR13 : Add Request 13
bits : 13 - 13 (1 bit)
AR14 : Add Request 14
bits : 14 - 14 (1 bit)
AR15 : Add Request 15
bits : 15 - 15 (1 bit)
AR16 : Add Request 16
bits : 16 - 16 (1 bit)
AR17 : Add Request 17
bits : 17 - 17 (1 bit)
AR18 : Add Request 18
bits : 18 - 18 (1 bit)
AR19 : Add Request 19
bits : 19 - 19 (1 bit)
AR20 : Add Request 20
bits : 20 - 20 (1 bit)
AR21 : Add Request 21
bits : 21 - 21 (1 bit)
AR22 : Add Request 22
bits : 22 - 22 (1 bit)
AR23 : Add Request 23
bits : 23 - 23 (1 bit)
AR24 : Add Request 24
bits : 24 - 24 (1 bit)
AR25 : Add Request 25
bits : 25 - 25 (1 bit)
AR26 : Add Request 26
bits : 26 - 26 (1 bit)
AR27 : Add Request 27
bits : 27 - 27 (1 bit)
AR28 : Add Request 28
bits : 28 - 28 (1 bit)
AR29 : Add Request 29
bits : 29 - 29 (1 bit)
AR30 : Add Request 30
bits : 30 - 30 (1 bit)
AR31 : Add Request 31
bits : 31 - 31 (1 bit)
Tx Buffer Cancellation Request
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR0 : Cancellation Request 0
bits : 0 - 0 (1 bit)
CR1 : Cancellation Request 1
bits : 1 - 1 (1 bit)
CR2 : Cancellation Request 2
bits : 2 - 2 (1 bit)
CR3 : Cancellation Request 3
bits : 3 - 3 (1 bit)
CR4 : Cancellation Request 4
bits : 4 - 4 (1 bit)
CR5 : Cancellation Request 5
bits : 5 - 5 (1 bit)
CR6 : Cancellation Request 6
bits : 6 - 6 (1 bit)
CR7 : Cancellation Request 7
bits : 7 - 7 (1 bit)
CR8 : Cancellation Request 8
bits : 8 - 8 (1 bit)
CR9 : Cancellation Request 9
bits : 9 - 9 (1 bit)
CR10 : Cancellation Request 10
bits : 10 - 10 (1 bit)
CR11 : Cancellation Request 11
bits : 11 - 11 (1 bit)
CR12 : Cancellation Request 12
bits : 12 - 12 (1 bit)
CR13 : Cancellation Request 13
bits : 13 - 13 (1 bit)
CR14 : Cancellation Request 14
bits : 14 - 14 (1 bit)
CR15 : Cancellation Request 15
bits : 15 - 15 (1 bit)
CR16 : Cancellation Request 16
bits : 16 - 16 (1 bit)
CR17 : Cancellation Request 17
bits : 17 - 17 (1 bit)
CR18 : Cancellation Request 18
bits : 18 - 18 (1 bit)
CR19 : Cancellation Request 19
bits : 19 - 19 (1 bit)
CR20 : Cancellation Request 20
bits : 20 - 20 (1 bit)
CR21 : Cancellation Request 21
bits : 21 - 21 (1 bit)
CR22 : Cancellation Request 22
bits : 22 - 22 (1 bit)
CR23 : Cancellation Request 23
bits : 23 - 23 (1 bit)
CR24 : Cancellation Request 24
bits : 24 - 24 (1 bit)
CR25 : Cancellation Request 25
bits : 25 - 25 (1 bit)
CR26 : Cancellation Request 26
bits : 26 - 26 (1 bit)
CR27 : Cancellation Request 27
bits : 27 - 27 (1 bit)
CR28 : Cancellation Request 28
bits : 28 - 28 (1 bit)
CR29 : Cancellation Request 29
bits : 29 - 29 (1 bit)
CR30 : Cancellation Request 30
bits : 30 - 30 (1 bit)
CR31 : Cancellation Request 31
bits : 31 - 31 (1 bit)
Tx Buffer Cancellation Request
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR0 : Cancellation Request 0
bits : 0 - 0 (1 bit)
CR1 : Cancellation Request 1
bits : 1 - 1 (1 bit)
CR2 : Cancellation Request 2
bits : 2 - 2 (1 bit)
CR3 : Cancellation Request 3
bits : 3 - 3 (1 bit)
CR4 : Cancellation Request 4
bits : 4 - 4 (1 bit)
CR5 : Cancellation Request 5
bits : 5 - 5 (1 bit)
CR6 : Cancellation Request 6
bits : 6 - 6 (1 bit)
CR7 : Cancellation Request 7
bits : 7 - 7 (1 bit)
CR8 : Cancellation Request 8
bits : 8 - 8 (1 bit)
CR9 : Cancellation Request 9
bits : 9 - 9 (1 bit)
CR10 : Cancellation Request 10
bits : 10 - 10 (1 bit)
CR11 : Cancellation Request 11
bits : 11 - 11 (1 bit)
CR12 : Cancellation Request 12
bits : 12 - 12 (1 bit)
CR13 : Cancellation Request 13
bits : 13 - 13 (1 bit)
CR14 : Cancellation Request 14
bits : 14 - 14 (1 bit)
CR15 : Cancellation Request 15
bits : 15 - 15 (1 bit)
CR16 : Cancellation Request 16
bits : 16 - 16 (1 bit)
CR17 : Cancellation Request 17
bits : 17 - 17 (1 bit)
CR18 : Cancellation Request 18
bits : 18 - 18 (1 bit)
CR19 : Cancellation Request 19
bits : 19 - 19 (1 bit)
CR20 : Cancellation Request 20
bits : 20 - 20 (1 bit)
CR21 : Cancellation Request 21
bits : 21 - 21 (1 bit)
CR22 : Cancellation Request 22
bits : 22 - 22 (1 bit)
CR23 : Cancellation Request 23
bits : 23 - 23 (1 bit)
CR24 : Cancellation Request 24
bits : 24 - 24 (1 bit)
CR25 : Cancellation Request 25
bits : 25 - 25 (1 bit)
CR26 : Cancellation Request 26
bits : 26 - 26 (1 bit)
CR27 : Cancellation Request 27
bits : 27 - 27 (1 bit)
CR28 : Cancellation Request 28
bits : 28 - 28 (1 bit)
CR29 : Cancellation Request 29
bits : 29 - 29 (1 bit)
CR30 : Cancellation Request 30
bits : 30 - 30 (1 bit)
CR31 : Cancellation Request 31
bits : 31 - 31 (1 bit)
Tx Buffer Transmission Occurred
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TO0 : Transmission Occurred 0
bits : 0 - 0 (1 bit)
TO1 : Transmission Occurred 1
bits : 1 - 1 (1 bit)
TO2 : Transmission Occurred 2
bits : 2 - 2 (1 bit)
TO3 : Transmission Occurred 3
bits : 3 - 3 (1 bit)
TO4 : Transmission Occurred 4
bits : 4 - 4 (1 bit)
TO5 : Transmission Occurred 5
bits : 5 - 5 (1 bit)
TO6 : Transmission Occurred 6
bits : 6 - 6 (1 bit)
TO7 : Transmission Occurred 7
bits : 7 - 7 (1 bit)
TO8 : Transmission Occurred 8
bits : 8 - 8 (1 bit)
TO9 : Transmission Occurred 9
bits : 9 - 9 (1 bit)
TO10 : Transmission Occurred 10
bits : 10 - 10 (1 bit)
TO11 : Transmission Occurred 11
bits : 11 - 11 (1 bit)
TO12 : Transmission Occurred 12
bits : 12 - 12 (1 bit)
TO13 : Transmission Occurred 13
bits : 13 - 13 (1 bit)
TO14 : Transmission Occurred 14
bits : 14 - 14 (1 bit)
TO15 : Transmission Occurred 15
bits : 15 - 15 (1 bit)
TO16 : Transmission Occurred 16
bits : 16 - 16 (1 bit)
TO17 : Transmission Occurred 17
bits : 17 - 17 (1 bit)
TO18 : Transmission Occurred 18
bits : 18 - 18 (1 bit)
TO19 : Transmission Occurred 19
bits : 19 - 19 (1 bit)
TO20 : Transmission Occurred 20
bits : 20 - 20 (1 bit)
TO21 : Transmission Occurred 21
bits : 21 - 21 (1 bit)
TO22 : Transmission Occurred 22
bits : 22 - 22 (1 bit)
TO23 : Transmission Occurred 23
bits : 23 - 23 (1 bit)
TO24 : Transmission Occurred 24
bits : 24 - 24 (1 bit)
TO25 : Transmission Occurred 25
bits : 25 - 25 (1 bit)
TO26 : Transmission Occurred 26
bits : 26 - 26 (1 bit)
TO27 : Transmission Occurred 27
bits : 27 - 27 (1 bit)
TO28 : Transmission Occurred 28
bits : 28 - 28 (1 bit)
TO29 : Transmission Occurred 29
bits : 29 - 29 (1 bit)
TO30 : Transmission Occurred 30
bits : 30 - 30 (1 bit)
TO31 : Transmission Occurred 31
bits : 31 - 31 (1 bit)
Tx Buffer Transmission Occurred
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TO0 : Transmission Occurred 0
bits : 0 - 0 (1 bit)
TO1 : Transmission Occurred 1
bits : 1 - 1 (1 bit)
TO2 : Transmission Occurred 2
bits : 2 - 2 (1 bit)
TO3 : Transmission Occurred 3
bits : 3 - 3 (1 bit)
TO4 : Transmission Occurred 4
bits : 4 - 4 (1 bit)
TO5 : Transmission Occurred 5
bits : 5 - 5 (1 bit)
TO6 : Transmission Occurred 6
bits : 6 - 6 (1 bit)
TO7 : Transmission Occurred 7
bits : 7 - 7 (1 bit)
TO8 : Transmission Occurred 8
bits : 8 - 8 (1 bit)
TO9 : Transmission Occurred 9
bits : 9 - 9 (1 bit)
TO10 : Transmission Occurred 10
bits : 10 - 10 (1 bit)
TO11 : Transmission Occurred 11
bits : 11 - 11 (1 bit)
TO12 : Transmission Occurred 12
bits : 12 - 12 (1 bit)
TO13 : Transmission Occurred 13
bits : 13 - 13 (1 bit)
TO14 : Transmission Occurred 14
bits : 14 - 14 (1 bit)
TO15 : Transmission Occurred 15
bits : 15 - 15 (1 bit)
TO16 : Transmission Occurred 16
bits : 16 - 16 (1 bit)
TO17 : Transmission Occurred 17
bits : 17 - 17 (1 bit)
TO18 : Transmission Occurred 18
bits : 18 - 18 (1 bit)
TO19 : Transmission Occurred 19
bits : 19 - 19 (1 bit)
TO20 : Transmission Occurred 20
bits : 20 - 20 (1 bit)
TO21 : Transmission Occurred 21
bits : 21 - 21 (1 bit)
TO22 : Transmission Occurred 22
bits : 22 - 22 (1 bit)
TO23 : Transmission Occurred 23
bits : 23 - 23 (1 bit)
TO24 : Transmission Occurred 24
bits : 24 - 24 (1 bit)
TO25 : Transmission Occurred 25
bits : 25 - 25 (1 bit)
TO26 : Transmission Occurred 26
bits : 26 - 26 (1 bit)
TO27 : Transmission Occurred 27
bits : 27 - 27 (1 bit)
TO28 : Transmission Occurred 28
bits : 28 - 28 (1 bit)
TO29 : Transmission Occurred 29
bits : 29 - 29 (1 bit)
TO30 : Transmission Occurred 30
bits : 30 - 30 (1 bit)
TO31 : Transmission Occurred 31
bits : 31 - 31 (1 bit)
Tx Buffer Cancellation Finished
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CF0 : Tx Buffer Cancellation Finished 0
bits : 0 - 0 (1 bit)
CF1 : Tx Buffer Cancellation Finished 1
bits : 1 - 1 (1 bit)
CF2 : Tx Buffer Cancellation Finished 2
bits : 2 - 2 (1 bit)
CF3 : Tx Buffer Cancellation Finished 3
bits : 3 - 3 (1 bit)
CF4 : Tx Buffer Cancellation Finished 4
bits : 4 - 4 (1 bit)
CF5 : Tx Buffer Cancellation Finished 5
bits : 5 - 5 (1 bit)
CF6 : Tx Buffer Cancellation Finished 6
bits : 6 - 6 (1 bit)
CF7 : Tx Buffer Cancellation Finished 7
bits : 7 - 7 (1 bit)
CF8 : Tx Buffer Cancellation Finished 8
bits : 8 - 8 (1 bit)
CF9 : Tx Buffer Cancellation Finished 9
bits : 9 - 9 (1 bit)
CF10 : Tx Buffer Cancellation Finished 10
bits : 10 - 10 (1 bit)
CF11 : Tx Buffer Cancellation Finished 11
bits : 11 - 11 (1 bit)
CF12 : Tx Buffer Cancellation Finished 12
bits : 12 - 12 (1 bit)
CF13 : Tx Buffer Cancellation Finished 13
bits : 13 - 13 (1 bit)
CF14 : Tx Buffer Cancellation Finished 14
bits : 14 - 14 (1 bit)
CF15 : Tx Buffer Cancellation Finished 15
bits : 15 - 15 (1 bit)
CF16 : Tx Buffer Cancellation Finished 16
bits : 16 - 16 (1 bit)
CF17 : Tx Buffer Cancellation Finished 17
bits : 17 - 17 (1 bit)
CF18 : Tx Buffer Cancellation Finished 18
bits : 18 - 18 (1 bit)
CF19 : Tx Buffer Cancellation Finished 19
bits : 19 - 19 (1 bit)
CF20 : Tx Buffer Cancellation Finished 20
bits : 20 - 20 (1 bit)
CF21 : Tx Buffer Cancellation Finished 21
bits : 21 - 21 (1 bit)
CF22 : Tx Buffer Cancellation Finished 22
bits : 22 - 22 (1 bit)
CF23 : Tx Buffer Cancellation Finished 23
bits : 23 - 23 (1 bit)
CF24 : Tx Buffer Cancellation Finished 24
bits : 24 - 24 (1 bit)
CF25 : Tx Buffer Cancellation Finished 25
bits : 25 - 25 (1 bit)
CF26 : Tx Buffer Cancellation Finished 26
bits : 26 - 26 (1 bit)
CF27 : Tx Buffer Cancellation Finished 27
bits : 27 - 27 (1 bit)
CF28 : Tx Buffer Cancellation Finished 28
bits : 28 - 28 (1 bit)
CF29 : Tx Buffer Cancellation Finished 29
bits : 29 - 29 (1 bit)
CF30 : Tx Buffer Cancellation Finished 30
bits : 30 - 30 (1 bit)
CF31 : Tx Buffer Cancellation Finished 31
bits : 31 - 31 (1 bit)
Tx Buffer Cancellation Finished
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CF0 : Tx Buffer Cancellation Finished 0
bits : 0 - 0 (1 bit)
CF1 : Tx Buffer Cancellation Finished 1
bits : 1 - 1 (1 bit)
CF2 : Tx Buffer Cancellation Finished 2
bits : 2 - 2 (1 bit)
CF3 : Tx Buffer Cancellation Finished 3
bits : 3 - 3 (1 bit)
CF4 : Tx Buffer Cancellation Finished 4
bits : 4 - 4 (1 bit)
CF5 : Tx Buffer Cancellation Finished 5
bits : 5 - 5 (1 bit)
CF6 : Tx Buffer Cancellation Finished 6
bits : 6 - 6 (1 bit)
CF7 : Tx Buffer Cancellation Finished 7
bits : 7 - 7 (1 bit)
CF8 : Tx Buffer Cancellation Finished 8
bits : 8 - 8 (1 bit)
CF9 : Tx Buffer Cancellation Finished 9
bits : 9 - 9 (1 bit)
CF10 : Tx Buffer Cancellation Finished 10
bits : 10 - 10 (1 bit)
CF11 : Tx Buffer Cancellation Finished 11
bits : 11 - 11 (1 bit)
CF12 : Tx Buffer Cancellation Finished 12
bits : 12 - 12 (1 bit)
CF13 : Tx Buffer Cancellation Finished 13
bits : 13 - 13 (1 bit)
CF14 : Tx Buffer Cancellation Finished 14
bits : 14 - 14 (1 bit)
CF15 : Tx Buffer Cancellation Finished 15
bits : 15 - 15 (1 bit)
CF16 : Tx Buffer Cancellation Finished 16
bits : 16 - 16 (1 bit)
CF17 : Tx Buffer Cancellation Finished 17
bits : 17 - 17 (1 bit)
CF18 : Tx Buffer Cancellation Finished 18
bits : 18 - 18 (1 bit)
CF19 : Tx Buffer Cancellation Finished 19
bits : 19 - 19 (1 bit)
CF20 : Tx Buffer Cancellation Finished 20
bits : 20 - 20 (1 bit)
CF21 : Tx Buffer Cancellation Finished 21
bits : 21 - 21 (1 bit)
CF22 : Tx Buffer Cancellation Finished 22
bits : 22 - 22 (1 bit)
CF23 : Tx Buffer Cancellation Finished 23
bits : 23 - 23 (1 bit)
CF24 : Tx Buffer Cancellation Finished 24
bits : 24 - 24 (1 bit)
CF25 : Tx Buffer Cancellation Finished 25
bits : 25 - 25 (1 bit)
CF26 : Tx Buffer Cancellation Finished 26
bits : 26 - 26 (1 bit)
CF27 : Tx Buffer Cancellation Finished 27
bits : 27 - 27 (1 bit)
CF28 : Tx Buffer Cancellation Finished 28
bits : 28 - 28 (1 bit)
CF29 : Tx Buffer Cancellation Finished 29
bits : 29 - 29 (1 bit)
CF30 : Tx Buffer Cancellation Finished 30
bits : 30 - 30 (1 bit)
CF31 : Tx Buffer Cancellation Finished 31
bits : 31 - 31 (1 bit)
Tx Buffer Transmission Interrupt Enable
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE0 : Transmission Interrupt Enable 0
bits : 0 - 0 (1 bit)
TIE1 : Transmission Interrupt Enable 1
bits : 1 - 1 (1 bit)
TIE2 : Transmission Interrupt Enable 2
bits : 2 - 2 (1 bit)
TIE3 : Transmission Interrupt Enable 3
bits : 3 - 3 (1 bit)
TIE4 : Transmission Interrupt Enable 4
bits : 4 - 4 (1 bit)
TIE5 : Transmission Interrupt Enable 5
bits : 5 - 5 (1 bit)
TIE6 : Transmission Interrupt Enable 6
bits : 6 - 6 (1 bit)
TIE7 : Transmission Interrupt Enable 7
bits : 7 - 7 (1 bit)
TIE8 : Transmission Interrupt Enable 8
bits : 8 - 8 (1 bit)
TIE9 : Transmission Interrupt Enable 9
bits : 9 - 9 (1 bit)
TIE10 : Transmission Interrupt Enable 10
bits : 10 - 10 (1 bit)
TIE11 : Transmission Interrupt Enable 11
bits : 11 - 11 (1 bit)
TIE12 : Transmission Interrupt Enable 12
bits : 12 - 12 (1 bit)
TIE13 : Transmission Interrupt Enable 13
bits : 13 - 13 (1 bit)
TIE14 : Transmission Interrupt Enable 14
bits : 14 - 14 (1 bit)
TIE15 : Transmission Interrupt Enable 15
bits : 15 - 15 (1 bit)
TIE16 : Transmission Interrupt Enable 16
bits : 16 - 16 (1 bit)
TIE17 : Transmission Interrupt Enable 17
bits : 17 - 17 (1 bit)
TIE18 : Transmission Interrupt Enable 18
bits : 18 - 18 (1 bit)
TIE19 : Transmission Interrupt Enable 19
bits : 19 - 19 (1 bit)
TIE20 : Transmission Interrupt Enable 20
bits : 20 - 20 (1 bit)
TIE21 : Transmission Interrupt Enable 21
bits : 21 - 21 (1 bit)
TIE22 : Transmission Interrupt Enable 22
bits : 22 - 22 (1 bit)
TIE23 : Transmission Interrupt Enable 23
bits : 23 - 23 (1 bit)
TIE24 : Transmission Interrupt Enable 24
bits : 24 - 24 (1 bit)
TIE25 : Transmission Interrupt Enable 25
bits : 25 - 25 (1 bit)
TIE26 : Transmission Interrupt Enable 26
bits : 26 - 26 (1 bit)
TIE27 : Transmission Interrupt Enable 27
bits : 27 - 27 (1 bit)
TIE28 : Transmission Interrupt Enable 28
bits : 28 - 28 (1 bit)
TIE29 : Transmission Interrupt Enable 29
bits : 29 - 29 (1 bit)
TIE30 : Transmission Interrupt Enable 30
bits : 30 - 30 (1 bit)
TIE31 : Transmission Interrupt Enable 31
bits : 31 - 31 (1 bit)
Tx Buffer Transmission Interrupt Enable
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE0 : Transmission Interrupt Enable 0
bits : 0 - 0 (1 bit)
TIE1 : Transmission Interrupt Enable 1
bits : 1 - 1 (1 bit)
TIE2 : Transmission Interrupt Enable 2
bits : 2 - 2 (1 bit)
TIE3 : Transmission Interrupt Enable 3
bits : 3 - 3 (1 bit)
TIE4 : Transmission Interrupt Enable 4
bits : 4 - 4 (1 bit)
TIE5 : Transmission Interrupt Enable 5
bits : 5 - 5 (1 bit)
TIE6 : Transmission Interrupt Enable 6
bits : 6 - 6 (1 bit)
TIE7 : Transmission Interrupt Enable 7
bits : 7 - 7 (1 bit)
TIE8 : Transmission Interrupt Enable 8
bits : 8 - 8 (1 bit)
TIE9 : Transmission Interrupt Enable 9
bits : 9 - 9 (1 bit)
TIE10 : Transmission Interrupt Enable 10
bits : 10 - 10 (1 bit)
TIE11 : Transmission Interrupt Enable 11
bits : 11 - 11 (1 bit)
TIE12 : Transmission Interrupt Enable 12
bits : 12 - 12 (1 bit)
TIE13 : Transmission Interrupt Enable 13
bits : 13 - 13 (1 bit)
TIE14 : Transmission Interrupt Enable 14
bits : 14 - 14 (1 bit)
TIE15 : Transmission Interrupt Enable 15
bits : 15 - 15 (1 bit)
TIE16 : Transmission Interrupt Enable 16
bits : 16 - 16 (1 bit)
TIE17 : Transmission Interrupt Enable 17
bits : 17 - 17 (1 bit)
TIE18 : Transmission Interrupt Enable 18
bits : 18 - 18 (1 bit)
TIE19 : Transmission Interrupt Enable 19
bits : 19 - 19 (1 bit)
TIE20 : Transmission Interrupt Enable 20
bits : 20 - 20 (1 bit)
TIE21 : Transmission Interrupt Enable 21
bits : 21 - 21 (1 bit)
TIE22 : Transmission Interrupt Enable 22
bits : 22 - 22 (1 bit)
TIE23 : Transmission Interrupt Enable 23
bits : 23 - 23 (1 bit)
TIE24 : Transmission Interrupt Enable 24
bits : 24 - 24 (1 bit)
TIE25 : Transmission Interrupt Enable 25
bits : 25 - 25 (1 bit)
TIE26 : Transmission Interrupt Enable 26
bits : 26 - 26 (1 bit)
TIE27 : Transmission Interrupt Enable 27
bits : 27 - 27 (1 bit)
TIE28 : Transmission Interrupt Enable 28
bits : 28 - 28 (1 bit)
TIE29 : Transmission Interrupt Enable 29
bits : 29 - 29 (1 bit)
TIE30 : Transmission Interrupt Enable 30
bits : 30 - 30 (1 bit)
TIE31 : Transmission Interrupt Enable 31
bits : 31 - 31 (1 bit)
Tx Buffer Cancellation Finished Interrupt Enable
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFIE0 : Cancellation Finished Interrupt Enable 0
bits : 0 - 0 (1 bit)
CFIE1 : Cancellation Finished Interrupt Enable 1
bits : 1 - 1 (1 bit)
CFIE2 : Cancellation Finished Interrupt Enable 2
bits : 2 - 2 (1 bit)
CFIE3 : Cancellation Finished Interrupt Enable 3
bits : 3 - 3 (1 bit)
CFIE4 : Cancellation Finished Interrupt Enable 4
bits : 4 - 4 (1 bit)
CFIE5 : Cancellation Finished Interrupt Enable 5
bits : 5 - 5 (1 bit)
CFIE6 : Cancellation Finished Interrupt Enable 6
bits : 6 - 6 (1 bit)
CFIE7 : Cancellation Finished Interrupt Enable 7
bits : 7 - 7 (1 bit)
CFIE8 : Cancellation Finished Interrupt Enable 8
bits : 8 - 8 (1 bit)
CFIE9 : Cancellation Finished Interrupt Enable 9
bits : 9 - 9 (1 bit)
CFIE10 : Cancellation Finished Interrupt Enable 10
bits : 10 - 10 (1 bit)
CFIE11 : Cancellation Finished Interrupt Enable 11
bits : 11 - 11 (1 bit)
CFIE12 : Cancellation Finished Interrupt Enable 12
bits : 12 - 12 (1 bit)
CFIE13 : Cancellation Finished Interrupt Enable 13
bits : 13 - 13 (1 bit)
CFIE14 : Cancellation Finished Interrupt Enable 14
bits : 14 - 14 (1 bit)
CFIE15 : Cancellation Finished Interrupt Enable 15
bits : 15 - 15 (1 bit)
CFIE16 : Cancellation Finished Interrupt Enable 16
bits : 16 - 16 (1 bit)
CFIE17 : Cancellation Finished Interrupt Enable 17
bits : 17 - 17 (1 bit)
CFIE18 : Cancellation Finished Interrupt Enable 18
bits : 18 - 18 (1 bit)
CFIE19 : Cancellation Finished Interrupt Enable 19
bits : 19 - 19 (1 bit)
CFIE20 : Cancellation Finished Interrupt Enable 20
bits : 20 - 20 (1 bit)
CFIE21 : Cancellation Finished Interrupt Enable 21
bits : 21 - 21 (1 bit)
CFIE22 : Cancellation Finished Interrupt Enable 22
bits : 22 - 22 (1 bit)
CFIE23 : Cancellation Finished Interrupt Enable 23
bits : 23 - 23 (1 bit)
CFIE24 : Cancellation Finished Interrupt Enable 24
bits : 24 - 24 (1 bit)
CFIE25 : Cancellation Finished Interrupt Enable 25
bits : 25 - 25 (1 bit)
CFIE26 : Cancellation Finished Interrupt Enable 26
bits : 26 - 26 (1 bit)
CFIE27 : Cancellation Finished Interrupt Enable 27
bits : 27 - 27 (1 bit)
CFIE28 : Cancellation Finished Interrupt Enable 28
bits : 28 - 28 (1 bit)
CFIE29 : Cancellation Finished Interrupt Enable 29
bits : 29 - 29 (1 bit)
CFIE30 : Cancellation Finished Interrupt Enable 30
bits : 30 - 30 (1 bit)
CFIE31 : Cancellation Finished Interrupt Enable 31
bits : 31 - 31 (1 bit)
Tx Buffer Cancellation Finished Interrupt Enable
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFIE0 : Cancellation Finished Interrupt Enable 0
bits : 0 - 0 (1 bit)
CFIE1 : Cancellation Finished Interrupt Enable 1
bits : 1 - 1 (1 bit)
CFIE2 : Cancellation Finished Interrupt Enable 2
bits : 2 - 2 (1 bit)
CFIE3 : Cancellation Finished Interrupt Enable 3
bits : 3 - 3 (1 bit)
CFIE4 : Cancellation Finished Interrupt Enable 4
bits : 4 - 4 (1 bit)
CFIE5 : Cancellation Finished Interrupt Enable 5
bits : 5 - 5 (1 bit)
CFIE6 : Cancellation Finished Interrupt Enable 6
bits : 6 - 6 (1 bit)
CFIE7 : Cancellation Finished Interrupt Enable 7
bits : 7 - 7 (1 bit)
CFIE8 : Cancellation Finished Interrupt Enable 8
bits : 8 - 8 (1 bit)
CFIE9 : Cancellation Finished Interrupt Enable 9
bits : 9 - 9 (1 bit)
CFIE10 : Cancellation Finished Interrupt Enable 10
bits : 10 - 10 (1 bit)
CFIE11 : Cancellation Finished Interrupt Enable 11
bits : 11 - 11 (1 bit)
CFIE12 : Cancellation Finished Interrupt Enable 12
bits : 12 - 12 (1 bit)
CFIE13 : Cancellation Finished Interrupt Enable 13
bits : 13 - 13 (1 bit)
CFIE14 : Cancellation Finished Interrupt Enable 14
bits : 14 - 14 (1 bit)
CFIE15 : Cancellation Finished Interrupt Enable 15
bits : 15 - 15 (1 bit)
CFIE16 : Cancellation Finished Interrupt Enable 16
bits : 16 - 16 (1 bit)
CFIE17 : Cancellation Finished Interrupt Enable 17
bits : 17 - 17 (1 bit)
CFIE18 : Cancellation Finished Interrupt Enable 18
bits : 18 - 18 (1 bit)
CFIE19 : Cancellation Finished Interrupt Enable 19
bits : 19 - 19 (1 bit)
CFIE20 : Cancellation Finished Interrupt Enable 20
bits : 20 - 20 (1 bit)
CFIE21 : Cancellation Finished Interrupt Enable 21
bits : 21 - 21 (1 bit)
CFIE22 : Cancellation Finished Interrupt Enable 22
bits : 22 - 22 (1 bit)
CFIE23 : Cancellation Finished Interrupt Enable 23
bits : 23 - 23 (1 bit)
CFIE24 : Cancellation Finished Interrupt Enable 24
bits : 24 - 24 (1 bit)
CFIE25 : Cancellation Finished Interrupt Enable 25
bits : 25 - 25 (1 bit)
CFIE26 : Cancellation Finished Interrupt Enable 26
bits : 26 - 26 (1 bit)
CFIE27 : Cancellation Finished Interrupt Enable 27
bits : 27 - 27 (1 bit)
CFIE28 : Cancellation Finished Interrupt Enable 28
bits : 28 - 28 (1 bit)
CFIE29 : Cancellation Finished Interrupt Enable 29
bits : 29 - 29 (1 bit)
CFIE30 : Cancellation Finished Interrupt Enable 30
bits : 30 - 30 (1 bit)
CFIE31 : Cancellation Finished Interrupt Enable 31
bits : 31 - 31 (1 bit)
Tx Event FIFO Configuration
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFSA : Event FIFO Start Address
bits : 0 - 15 (16 bit)
EFS : Event FIFO Size
bits : 16 - 21 (6 bit)
EFWM : Event FIFO Watermark
bits : 24 - 29 (6 bit)
Tx Event FIFO Configuration
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFSA : Event FIFO Start Address
bits : 0 - 15 (16 bit)
EFS : Event FIFO Size
bits : 16 - 21 (6 bit)
EFWM : Event FIFO Watermark
bits : 24 - 29 (6 bit)
Tx Event FIFO Status
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
EFGI : Event FIFO Get Index
bits : 8 - 12 (5 bit)
EFPI : Event FIFO Put Index
bits : 16 - 20 (5 bit)
EFF : Event FIFO Full
bits : 24 - 24 (1 bit)
TEFL : Tx Event FIFO Element Lost
bits : 25 - 25 (1 bit)
Tx Event FIFO Status
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
EFGI : Event FIFO Get Index
bits : 8 - 12 (5 bit)
EFPI : Event FIFO Put Index
bits : 16 - 20 (5 bit)
EFF : Event FIFO Full
bits : 24 - 24 (1 bit)
TEFL : Tx Event FIFO Element Lost
bits : 25 - 25 (1 bit)
Tx Event FIFO Acknowledge
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
Tx Event FIFO Acknowledge
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
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