Registers
CTRLA
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
CHANNEL
Channel n Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
INTPEND
Channel Pending Interrupt
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Channel ID
bits : 0 - 3 (4 bit)
OVR : Channel Overrun
bits : 8 - 8 (1 bit)
EVD : Channel Event Detected
bits : 9 - 9 (1 bit)
READY : Ready
bits : 14 - 14 (1 bit)
BUSY : Busy
bits : 15 - 15 (1 bit)
CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x1054 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x1055 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x1056 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x1057 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[12]
User Multiplexer n
address_offset : 0x10F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x115C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x115D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x115E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x115F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER0
User Multiplexer n
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER1
User Multiplexer n
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[13]
User Multiplexer n
address_offset : 0x124C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x1268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x126C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x126D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x126E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x126F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER2
User Multiplexer n
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER3
User Multiplexer n
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER4
User Multiplexer n
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER5
User Multiplexer n
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
USER6
User Multiplexer n
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x1380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x1384 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x1385 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x1386 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x1387 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[14]
User Multiplexer n
address_offset : 0x13A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
USER7
User Multiplexer n
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x13D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x13E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x13F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
INTSTATUS
Interrupt Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHINT0 : Channel 0 Pending Interrupt
bits : 0 - 0 (1 bit)
CHINT1 : Channel 1 Pending Interrupt
bits : 1 - 1 (1 bit)
CHINT2 : Channel 2 Pending Interrupt
bits : 2 - 2 (1 bit)
CHINT3 : Channel 3 Pending Interrupt
bits : 3 - 3 (1 bit)
CHINT4 : Channel 4 Pending Interrupt
bits : 4 - 4 (1 bit)
CHINT5 : Channel 5 Pending Interrupt
bits : 5 - 5 (1 bit)
CHINT6 : Channel 6 Pending Interrupt
bits : 6 - 6 (1 bit)
CHINT7 : Channel 7 Pending Interrupt
bits : 7 - 7 (1 bit)
CHINT8 : Channel 8 Pending Interrupt
bits : 8 - 8 (1 bit)
CHINT9 : Channel 9 Pending Interrupt
bits : 9 - 9 (1 bit)
CHINT10 : Channel 10 Pending Interrupt
bits : 10 - 10 (1 bit)
CHINT11 : Channel 11 Pending Interrupt
bits : 11 - 11 (1 bit)
USER8
User Multiplexer n
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER9
User Multiplexer n
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER10
User Multiplexer n
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER11
User Multiplexer n
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER12
User Multiplexer n
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[15]
User Multiplexer n
address_offset : 0x1500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER13
User Multiplexer n
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER14
User Multiplexer n
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER15
User Multiplexer n
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER16
User Multiplexer n
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER17
User Multiplexer n
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[16]
User Multiplexer n
address_offset : 0x1660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER18
User Multiplexer n
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER19
User Multiplexer n
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER20
User Multiplexer n
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER21
User Multiplexer n
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER22
User Multiplexer n
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER23
User Multiplexer n
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[17]
User Multiplexer n
address_offset : 0x17C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
BUSYCH
Busy Channels
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSYCH0 : Busy Channel 0
bits : 0 - 0 (1 bit)
BUSYCH1 : Busy Channel 1
bits : 1 - 1 (1 bit)
BUSYCH2 : Busy Channel 2
bits : 2 - 2 (1 bit)
BUSYCH3 : Busy Channel 3
bits : 3 - 3 (1 bit)
BUSYCH4 : Busy Channel 4
bits : 4 - 4 (1 bit)
BUSYCH5 : Busy Channel 5
bits : 5 - 5 (1 bit)
BUSYCH6 : Busy Channel 6
bits : 6 - 6 (1 bit)
BUSYCH7 : Busy Channel 7
bits : 7 - 7 (1 bit)
BUSYCH8 : Busy Channel 8
bits : 8 - 8 (1 bit)
BUSYCH9 : Busy Channel 9
bits : 9 - 9 (1 bit)
BUSYCH10 : Busy Channel 10
bits : 10 - 10 (1 bit)
BUSYCH11 : Busy Channel 11
bits : 11 - 11 (1 bit)
USER24
User Multiplexer n
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER25
User Multiplexer n
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
USER26
User Multiplexer n
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
USER27
User Multiplexer n
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x18D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x18E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x18F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER28
User Multiplexer n
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[18]
User Multiplexer n
address_offset : 0x192C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER29
User Multiplexer n
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER30
User Multiplexer n
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER31
User Multiplexer n
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER32
User Multiplexer n
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER33
User Multiplexer n
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER34
User Multiplexer n
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[19]
User Multiplexer n
address_offset : 0x1A98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER35
User Multiplexer n
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER36
User Multiplexer n
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER37
User Multiplexer n
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER38
User Multiplexer n
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER39
User Multiplexer n
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
READYUSR
Ready Users
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READYUSR0 : Ready User for Channel 0
bits : 0 - 0 (1 bit)
READYUSR1 : Ready User for Channel 1
bits : 1 - 1 (1 bit)
READYUSR2 : Ready User for Channel 2
bits : 2 - 2 (1 bit)
READYUSR3 : Ready User for Channel 3
bits : 3 - 3 (1 bit)
READYUSR4 : Ready User for Channel 4
bits : 4 - 4 (1 bit)
READYUSR5 : Ready User for Channel 5
bits : 5 - 5 (1 bit)
READYUSR6 : Ready User for Channel 6
bits : 6 - 6 (1 bit)
READYUSR7 : Ready User for Channel 7
bits : 7 - 7 (1 bit)
READYUSR8 : Ready User for Channel 8
bits : 8 - 8 (1 bit)
READYUSR9 : Ready User for Channel 9
bits : 9 - 9 (1 bit)
READYUSR10 : Ready User for Channel 10
bits : 10 - 10 (1 bit)
READYUSR11 : Ready User for Channel 11
bits : 11 - 11 (1 bit)
USER40
User Multiplexer n
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[20]
User Multiplexer n
address_offset : 0x1C08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER41
User Multiplexer n
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER42
User Multiplexer n
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER43
User Multiplexer n
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER44
User Multiplexer n
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER45
User Multiplexer n
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[21]
User Multiplexer n
address_offset : 0x1D7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER46
User Multiplexer n
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER47
User Multiplexer n
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
USER48
User Multiplexer n
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
USER49
User Multiplexer n
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x1E7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER50
User Multiplexer n
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER51
User Multiplexer n
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[22]
User Multiplexer n
address_offset : 0x1EF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER52
User Multiplexer n
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER53
User Multiplexer n
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER54
User Multiplexer n
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER55
User Multiplexer n
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
USER56
User Multiplexer n
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER57
User Multiplexer n
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[23]
User Multiplexer n
address_offset : 0x2070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER58
User Multiplexer n
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER59
User Multiplexer n
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER60
User Multiplexer n
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER61
User Multiplexer n
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER62
User Multiplexer n
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER63
User Multiplexer n
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[24]
User Multiplexer n
address_offset : 0x21F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER64
User Multiplexer n
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER65
User Multiplexer n
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER66
User Multiplexer n
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[25]
User Multiplexer n
address_offset : 0x2374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
USER[0]
User Multiplexer n
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x244 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x245 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x246 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x247 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[26]
User Multiplexer n
address_offset : 0x24FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
USER[27]
User Multiplexer n
address_offset : 0x2688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[28]
User Multiplexer n
address_offset : 0x2818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[29]
User Multiplexer n
address_offset : 0x29AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x2AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x2AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x2AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x2AF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[30]
User Multiplexer n
address_offset : 0x2B44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[31]
User Multiplexer n
address_offset : 0x2CE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[32]
User Multiplexer n
address_offset : 0x2E80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[33]
User Multiplexer n
address_offset : 0x3024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x31C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
USER[34]
User Multiplexer n
address_offset : 0x31CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x31D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x31E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x31F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[35]
User Multiplexer n
address_offset : 0x3378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[36]
User Multiplexer n
address_offset : 0x3528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[1]
User Multiplexer n
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[37]
User Multiplexer n
address_offset : 0x36DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[38]
User Multiplexer n
address_offset : 0x3894 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x394 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x395 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x396 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x397 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[39]
User Multiplexer n
address_offset : 0x3A50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[40]
User Multiplexer n
address_offset : 0x3C10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[41]
User Multiplexer n
address_offset : 0x3DD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[42]
User Multiplexer n
address_offset : 0x3F9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
SWEVT
Software Event
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHANNEL0 : Channel 0 Software Selection
bits : 0 - 0 (1 bit)
CHANNEL1 : Channel 1 Software Selection
bits : 1 - 1 (1 bit)
CHANNEL2 : Channel 2 Software Selection
bits : 2 - 2 (1 bit)
CHANNEL3 : Channel 3 Software Selection
bits : 3 - 3 (1 bit)
CHANNEL4 : Channel 4 Software Selection
bits : 4 - 4 (1 bit)
CHANNEL5 : Channel 5 Software Selection
bits : 5 - 5 (1 bit)
CHANNEL6 : Channel 6 Software Selection
bits : 6 - 6 (1 bit)
CHANNEL7 : Channel 7 Software Selection
bits : 7 - 7 (1 bit)
CHANNEL8 : Channel 8 Software Selection
bits : 8 - 8 (1 bit)
CHANNEL9 : Channel 9 Software Selection
bits : 9 - 9 (1 bit)
CHANNEL10 : Channel 10 Software Selection
bits : 10 - 10 (1 bit)
CHANNEL11 : Channel 11 Software Selection
bits : 11 - 11 (1 bit)
CHANNEL12 : Channel 12 Software Selection
bits : 12 - 12 (1 bit)
CHANNEL13 : Channel 13 Software Selection
bits : 13 - 13 (1 bit)
CHANNEL14 : Channel 14 Software Selection
bits : 14 - 14 (1 bit)
CHANNEL15 : Channel 15 Software Selection
bits : 15 - 15 (1 bit)
CHANNEL16 : Channel 16 Software Selection
bits : 16 - 16 (1 bit)
CHANNEL17 : Channel 17 Software Selection
bits : 17 - 17 (1 bit)
CHANNEL18 : Channel 18 Software Selection
bits : 18 - 18 (1 bit)
CHANNEL19 : Channel 19 Software Selection
bits : 19 - 19 (1 bit)
CHANNEL20 : Channel 20 Software Selection
bits : 20 - 20 (1 bit)
CHANNEL21 : Channel 21 Software Selection
bits : 21 - 21 (1 bit)
CHANNEL22 : Channel 22 Software Selection
bits : 22 - 22 (1 bit)
CHANNEL23 : Channel 23 Software Selection
bits : 23 - 23 (1 bit)
CHANNEL24 : Channel 24 Software Selection
bits : 24 - 24 (1 bit)
CHANNEL25 : Channel 25 Software Selection
bits : 25 - 25 (1 bit)
CHANNEL26 : Channel 26 Software Selection
bits : 26 - 26 (1 bit)
CHANNEL27 : Channel 27 Software Selection
bits : 27 - 27 (1 bit)
CHANNEL28 : Channel 28 Software Selection
bits : 28 - 28 (1 bit)
CHANNEL29 : Channel 29 Software Selection
bits : 29 - 29 (1 bit)
CHANNEL30 : Channel 30 Software Selection
bits : 30 - 30 (1 bit)
CHANNEL31 : Channel 31 Software Selection
bits : 31 - 31 (1 bit)
CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x414 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x415 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x416 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
USER[43]
User Multiplexer n
address_offset : 0x4168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x417 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[44]
User Multiplexer n
address_offset : 0x4338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[45]
User Multiplexer n
address_offset : 0x450C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[46]
User Multiplexer n
address_offset : 0x46E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
USER[2]
User Multiplexer n
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[47]
User Multiplexer n
address_offset : 0x48C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x49C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x49D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x49E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x49F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[48]
User Multiplexer n
address_offset : 0x4AA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
USER[49]
User Multiplexer n
address_offset : 0x4C84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
USER[50]
User Multiplexer n
address_offset : 0x4E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
USER[51]
User Multiplexer n
address_offset : 0x5058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[52]
User Multiplexer n
address_offset : 0x5248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x52C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x52D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x52E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x52F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[53]
User Multiplexer n
address_offset : 0x543C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[54]
User Multiplexer n
address_offset : 0x5634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[55]
User Multiplexer n
address_offset : 0x5830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[56]
User Multiplexer n
address_offset : 0x5A30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[3]
User Multiplexer n
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
USER[57]
User Multiplexer n
address_offset : 0x5C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x5C4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x5C5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x5C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x5C7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[58]
User Multiplexer n
address_offset : 0x5E3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
USER[59]
User Multiplexer n
address_offset : 0x6048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[60]
User Multiplexer n
address_offset : 0x6258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[61]
User Multiplexer n
address_offset : 0x646C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x664 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x665 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x666 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x667 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[62]
User Multiplexer n
address_offset : 0x6684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[63]
User Multiplexer n
address_offset : 0x68A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[64]
User Multiplexer n
address_offset : 0x6AC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[65]
User Multiplexer n
address_offset : 0x6CE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[4]
User Multiplexer n
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
USER[66]
User Multiplexer n
address_offset : 0x6F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHSTATUS
Channel n Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x70C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x70D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x70E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x70F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x7BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x7BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x7BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x7BF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x7F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
PRICTRL
Priority Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI : Channel Priority Number
bits : 0 - 3 (4 bit)
RREN : Round-Robin Scheduling Enable
bits : 7 - 7 (1 bit)
USER[5]
User Multiplexer n
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x874 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x875 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x876 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x877 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x934 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x935 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x936 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x937 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[6]
User Multiplexer n
address_offset : 0x954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0x9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0x9FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0x9FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0x9FE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0x9FF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[7]
User Multiplexer n
address_offset : 0xA90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0xAC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0xACC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0xACD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0xACE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0xACF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0xB5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0xB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0xB7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0xBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0xBA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0xBA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0xBA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0xBA7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[8]
User Multiplexer n
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0xC80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0xC84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0xC85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0xC86 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0xC87 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[9]
User Multiplexer n
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0xD68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0xD6C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0xD6D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0xD6E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0xD6F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0xE58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0xE5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
USER[10]
User Multiplexer n
address_offset : 0xE5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0xE5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0xE5E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0xE5F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0xF5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
Channel n Control
address_offset : 0xF50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 6 (7 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
Channel n Interrupt Enable Clear
address_offset : 0xF54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
Channel n Interrupt Enable Set
address_offset : 0xF55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0xF56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0xF57 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
Channel n Interrupt Flag Status and Clear
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Channel n Status
address_offset : 0xF7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
USER[11]
User Multiplexer n
address_offset : 0xFA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 5 (6 bit)
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