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TPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFD0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SSPSR

ACPR

FFSR

FFCR

FSCR

CSPSR

TRIGGER

FIFO0

ITATBCTR2

ITATBCTR0

FIFO1

SPPR

ITCTRL

CLAIMSET

CLAIMCLR

DEVID

DEVTYPE


SSPSR

Supported Parallel Port Size Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SSPSR SSPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ACPR

Asynchronous Clock Prescaler Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACPR ACPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALER

PRESCALER :
bits : 0 - 12 (13 bit)


FFSR

Formatter and Flush Status Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FFSR FFSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FlInProg FtStopped TCPresent FtNonStop

FlInProg :
bits : 0 - 0 (1 bit)

FtStopped :
bits : 1 - 1 (1 bit)

TCPresent :
bits : 2 - 2 (1 bit)

FtNonStop :
bits : 3 - 3 (1 bit)


FFCR

Formatter and Flush Control Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FFCR FFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EnFCont TrigIn

EnFCont :
bits : 1 - 1 (1 bit)

TrigIn :
bits : 8 - 8 (1 bit)


FSCR

Formatter Synchronization Counter Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSCR FSCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CSPSR

Current Parallel Port Size Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSPSR CSPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRIGGER

TRIGGER
address_offset : 0xEE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TRIGGER TRIGGER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIGGER

TRIGGER :
bits : 0 - 0 (1 bit)


FIFO0

Integration ETM Data
address_offset : 0xEEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO0 FIFO0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETM0 ETM1 ETM2 ETM_bytecount ETM_ATVALID ITM_bytecount ITM_ATVALID

ETM0 :
bits : 0 - 7 (8 bit)

ETM1 :
bits : 8 - 15 (8 bit)

ETM2 :
bits : 16 - 23 (8 bit)

ETM_bytecount :
bits : 24 - 25 (2 bit)

ETM_ATVALID :
bits : 26 - 26 (1 bit)

ITM_bytecount :
bits : 27 - 28 (2 bit)

ITM_ATVALID :
bits : 29 - 29 (1 bit)


ITATBCTR2

ITATBCTR2
address_offset : 0xEF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITATBCTR2 ITATBCTR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATREADY

ATREADY :
bits : 0 - 0 (1 bit)


ITATBCTR0

ITATBCTR0
address_offset : 0xEF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ITATBCTR0 ITATBCTR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ATREADY

ATREADY :
bits : 0 - 0 (1 bit)


FIFO1

Integration ITM Data
address_offset : 0xEFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO1 FIFO1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITM0 ITM1 ITM2 ETM_bytecount ETM_ATVALID ITM_bytecount ITM_ATVALID

ITM0 :
bits : 0 - 7 (8 bit)

ITM1 :
bits : 8 - 15 (8 bit)

ITM2 :
bits : 16 - 23 (8 bit)

ETM_bytecount :
bits : 24 - 25 (2 bit)

ETM_ATVALID :
bits : 26 - 26 (1 bit)

ITM_bytecount :
bits : 27 - 28 (2 bit)

ITM_ATVALID :
bits : 29 - 29 (1 bit)


SPPR

Selected Pin Protocol Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPPR SPPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXMODE

TXMODE :
bits : 0 - 1 (2 bit)


ITCTRL

Integration Mode Control
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ITCTRL ITCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Mode

Mode :
bits : 0 - 0 (1 bit)


CLAIMSET

Claim tag set
address_offset : 0xFA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLAIMSET CLAIMSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLAIMCLR

Claim tag clear
address_offset : 0xFA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLAIMCLR CLAIMCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DEVID

TPIU_DEVID
address_offset : 0xFC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVID DEVID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NrTraceInput AsynClkIn MinBufSz PTINVALID MANCVALID NRZVALID

NrTraceInput :
bits : 0 - 0 (1 bit)

AsynClkIn :
bits : 5 - 5 (1 bit)

MinBufSz :
bits : 6 - 8 (3 bit)

PTINVALID :
bits : 9 - 9 (1 bit)

MANCVALID :
bits : 10 - 10 (1 bit)

NRZVALID :
bits : 11 - 11 (1 bit)


DEVTYPE

TPIU_DEVTYPE
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVTYPE DEVTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SubType MajorType

SubType :
bits : 0 - 3 (4 bit)

MajorType :
bits : 4 - 7 (4 bit)



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