\n

FREQM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRLA

CTRLB

VALUE

CFGA

INTENCLR

INTENSET

INTFLAG

STATUS

SYNCBUSY


CTRLA

Control A Register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)


CTRLB

Control B Register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTRLB CTRLB write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 START

START : Start Measurement
bits : 0 - 0 (1 bit)


VALUE

Count Value Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VALUE VALUE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Measurement Value
bits : 0 - 23 (24 bit)


CFGA

Config A register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGA CFGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFNUM

REFNUM : Number of Reference Clock Cycles
bits : 0 - 7 (8 bit)


INTENCLR

Interrupt Enable Clear Register
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DONE

DONE : Measurement Done Interrupt Enable
bits : 0 - 0 (1 bit)


INTENSET

Interrupt Enable Set Register
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DONE

DONE : Measurement Done Interrupt Enable
bits : 0 - 0 (1 bit)


INTFLAG

Interrupt Flag Register
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DONE

DONE : Measurement Done
bits : 0 - 0 (1 bit)


STATUS

Status Register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BUSY OVF

BUSY : FREQM Status
bits : 0 - 0 (1 bit)

OVF : Sticky Count Value Overflow
bits : 1 - 1 (1 bit)


SYNCBUSY

Synchronization Busy Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)



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