\n
address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected
8-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Timer Counter Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0 : COUNT16
Counter in 16-bit mode
1 : COUNT8
Counter in 8-bit mode
2 : COUNT32
Counter in 32-bit mode
End of enumeration elements list.
PRESCSYNC : Prescaler and Counter Synchronization
bits : 4 - 5 (2 bit)
Enumeration: PRESCSYNCSelect
0 : GCLK
Reload or reset the counter on next generic clock
1 : PRESC
Reload or reset the counter on next prescaler clock
2 : RESYNC
Reload or reset the counter on next generic clock and reset the prescaler counter
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)
ONDEMAND : Clock On Demand
bits : 7 - 7 (1 bit)
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0 : DIV1
Prescaler: GCLK_TC
1 : DIV2
Prescaler: GCLK_TC/2
2 : DIV4
Prescaler: GCLK_TC/4
3 : DIV8
Prescaler: GCLK_TC/8
4 : DIV16
Prescaler: GCLK_TC/16
5 : DIV64
Prescaler: GCLK_TC/64
6 : DIV256
Prescaler: GCLK_TC/256
7 : DIV1024
Prescaler: GCLK_TC/1024
End of enumeration elements list.
ALOCK : Auto Lock
bits : 11 - 11 (1 bit)
CAPTEN0 : Capture Channel 0 Enable
bits : 16 - 16 (1 bit)
CAPTEN1 : Capture Channel 1 Enable
bits : 17 - 17 (1 bit)
COPEN0 : Capture On Pin 0 Enable
bits : 20 - 20 (1 bit)
COPEN1 : Capture On Pin 1 Enable
bits : 21 - 21 (1 bit)
CAPTMODE0 : Capture Mode Channel 0
bits : 24 - 25 (2 bit)
Enumeration: CAPTMODE0Select
0 : DEFAULT
Default capture
1 : CAPTMIN
Minimum capture
2 : CAPTMAX
Maximum capture
End of enumeration elements list.
CAPTMODE1 : Capture mode Channel 1
bits : 27 - 28 (2 bit)
Enumeration: CAPTMODE1Select
0 : DEFAULT
Default capture
1 : CAPTMIN
Minimum capture
2 : CAPTMAX
Maximum capture
End of enumeration elements list.
16-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Timer Counter Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0 : COUNT16
Counter in 16-bit mode
1 : COUNT8
Counter in 8-bit mode
2 : COUNT32
Counter in 32-bit mode
End of enumeration elements list.
PRESCSYNC : Prescaler and Counter Synchronization
bits : 4 - 5 (2 bit)
Enumeration: PRESCSYNCSelect
0 : GCLK
Reload or reset the counter on next generic clock
1 : PRESC
Reload or reset the counter on next prescaler clock
2 : RESYNC
Reload or reset the counter on next generic clock and reset the prescaler counter
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)
ONDEMAND : Clock On Demand
bits : 7 - 7 (1 bit)
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0 : DIV1
Prescaler: GCLK_TC
1 : DIV2
Prescaler: GCLK_TC/2
2 : DIV4
Prescaler: GCLK_TC/4
3 : DIV8
Prescaler: GCLK_TC/8
4 : DIV16
Prescaler: GCLK_TC/16
5 : DIV64
Prescaler: GCLK_TC/64
6 : DIV256
Prescaler: GCLK_TC/256
7 : DIV1024
Prescaler: GCLK_TC/1024
End of enumeration elements list.
ALOCK : Auto Lock
bits : 11 - 11 (1 bit)
CAPTEN0 : Capture Channel 0 Enable
bits : 16 - 16 (1 bit)
CAPTEN1 : Capture Channel 1 Enable
bits : 17 - 17 (1 bit)
COPEN0 : Capture On Pin 0 Enable
bits : 20 - 20 (1 bit)
COPEN1 : Capture On Pin 1 Enable
bits : 21 - 21 (1 bit)
CAPTMODE0 : Capture Mode Channel 0
bits : 24 - 25 (2 bit)
Enumeration: CAPTMODE0Select
0 : DEFAULT
Default capture
1 : CAPTMIN
Minimum capture
2 : CAPTMAX
Maximum capture
End of enumeration elements list.
CAPTMODE1 : Capture mode Channel 1
bits : 27 - 28 (2 bit)
Enumeration: CAPTMODE1Select
0 : DEFAULT
Default capture
1 : CAPTMIN
Minimum capture
2 : CAPTMAX
Maximum capture
End of enumeration elements list.
32-bit Counter Mode - - Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Timer Counter Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0 : COUNT16
Counter in 16-bit mode
1 : COUNT8
Counter in 8-bit mode
2 : COUNT32
Counter in 32-bit mode
End of enumeration elements list.
PRESCSYNC : Prescaler and Counter Synchronization
bits : 4 - 5 (2 bit)
Enumeration: PRESCSYNCSelect
0 : GCLK
Reload or reset the counter on next generic clock
1 : PRESC
Reload or reset the counter on next prescaler clock
2 : RESYNC
Reload or reset the counter on next generic clock and reset the prescaler counter
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)
ONDEMAND : Clock On Demand
bits : 7 - 7 (1 bit)
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0 : DIV1
Prescaler: GCLK_TC
1 : DIV2
Prescaler: GCLK_TC/2
2 : DIV4
Prescaler: GCLK_TC/4
3 : DIV8
Prescaler: GCLK_TC/8
4 : DIV16
Prescaler: GCLK_TC/16
5 : DIV64
Prescaler: GCLK_TC/64
6 : DIV256
Prescaler: GCLK_TC/256
7 : DIV1024
Prescaler: GCLK_TC/1024
End of enumeration elements list.
ALOCK : Auto Lock
bits : 11 - 11 (1 bit)
CAPTEN0 : Capture Channel 0 Enable
bits : 16 - 16 (1 bit)
CAPTEN1 : Capture Channel 1 Enable
bits : 17 - 17 (1 bit)
COPEN0 : Capture On Pin 0 Enable
bits : 20 - 20 (1 bit)
COPEN1 : Capture On Pin 1 Enable
bits : 21 - 21 (1 bit)
CAPTMODE0 : Capture Mode Channel 0
bits : 24 - 25 (2 bit)
Enumeration: CAPTMODE0Select
0 : DEFAULT
Default capture
1 : CAPTMIN
Minimum capture
2 : CAPTMAX
Maximum capture
End of enumeration elements list.
CAPTMODE1 : Capture mode Channel 1
bits : 27 - 28 (2 bit)
Enumeration: CAPTMODE1Select
0 : DEFAULT
Default capture
1 : CAPTMIN
Minimum capture
2 : CAPTMAX
Maximum capture
End of enumeration elements list.
Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
MODE : Timer Counter Mode
bits : 2 - 3 (2 bit)
Enumeration: MODESelect
0 : COUNT16
Counter in 16-bit mode
1 : COUNT8
Counter in 8-bit mode
2 : COUNT32
Counter in 32-bit mode
End of enumeration elements list.
PRESCSYNC : Prescaler and Counter Synchronization
bits : 4 - 5 (2 bit)
Enumeration: PRESCSYNCSelect
0 : GCLK
Reload or reset the counter on next generic clock
1 : PRESC
Reload or reset the counter on next prescaler clock
2 : RESYNC
Reload or reset the counter on next generic clock and reset the prescaler counter
End of enumeration elements list.
RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)
ONDEMAND : Clock On Demand
bits : 7 - 7 (1 bit)
PRESCALER : Prescaler
bits : 8 - 10 (3 bit)
Enumeration: PRESCALERSelect
0 : DIV1
Prescaler: GCLK_TC
1 : DIV2
Prescaler: GCLK_TC/2
2 : DIV4
Prescaler: GCLK_TC/4
3 : DIV8
Prescaler: GCLK_TC/8
4 : DIV16
Prescaler: GCLK_TC/16
5 : DIV64
Prescaler: GCLK_TC/64
6 : DIV256
Prescaler: GCLK_TC/256
7 : DIV1024
Prescaler: GCLK_TC/1024
End of enumeration elements list.
ALOCK : Auto Lock
bits : 11 - 11 (1 bit)
CAPTEN0 : Capture Channel 0 Enable
bits : 16 - 16 (1 bit)
CAPTEN1 : Capture Channel 1 Enable
bits : 17 - 17 (1 bit)
COPEN0 : Capture On Pin 0 Enable
bits : 20 - 20 (1 bit)
COPEN1 : Capture On Pin 1 Enable
bits : 21 - 21 (1 bit)
CAPTMODE0 : Capture Mode Channel 0
bits : 24 - 25 (2 bit)
Enumeration: CAPTMODE0Select
0 : DEFAULT
Default capture
1 : CAPTMIN
Minimum capture
2 : CAPTMAX
Maximum capture
End of enumeration elements list.
CAPTMODE1 : Capture mode Channel 1
bits : 27 - 28 (2 bit)
Enumeration: CAPTMODE1Select
0 : DEFAULT
Default capture
1 : CAPTMIN
Minimum capture
2 : CAPTMAX
Maximum capture
End of enumeration elements list.
8-bit Counter Mode - - Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : swrst
bits : 0 - 0 (1 bit)
ENABLE : enable
bits : 1 - 1 (1 bit)
CTRLB : CTRLB
bits : 2 - 2 (1 bit)
STATUS : STATUS
bits : 3 - 3 (1 bit)
COUNT : Counter
bits : 4 - 4 (1 bit)
PER : Period
bits : 5 - 5 (1 bit)
CC0 : Compare Channel 0
bits : 6 - 6 (1 bit)
CC1 : Compare Channel 1
bits : 7 - 7 (1 bit)
16-bit Counter Mode - - Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : swrst
bits : 0 - 0 (1 bit)
ENABLE : enable
bits : 1 - 1 (1 bit)
CTRLB : CTRLB
bits : 2 - 2 (1 bit)
STATUS : STATUS
bits : 3 - 3 (1 bit)
COUNT : Counter
bits : 4 - 4 (1 bit)
PER : Period
bits : 5 - 5 (1 bit)
CC0 : Compare Channel 0
bits : 6 - 6 (1 bit)
CC1 : Compare Channel 1
bits : 7 - 7 (1 bit)
32-bit Counter Mode - - Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : swrst
bits : 0 - 0 (1 bit)
ENABLE : enable
bits : 1 - 1 (1 bit)
CTRLB : CTRLB
bits : 2 - 2 (1 bit)
STATUS : STATUS
bits : 3 - 3 (1 bit)
COUNT : Counter
bits : 4 - 4 (1 bit)
PER : Period
bits : 5 - 5 (1 bit)
CC0 : Compare Channel 0
bits : 6 - 6 (1 bit)
CC1 : Compare Channel 1
bits : 7 - 7 (1 bit)
Synchronization Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : swrst
bits : 0 - 0 (1 bit)
ENABLE : enable
bits : 1 - 1 (1 bit)
CTRLB : CTRLB
bits : 2 - 2 (1 bit)
STATUS : STATUS
bits : 3 - 3 (1 bit)
COUNT : Counter
bits : 4 - 4 (1 bit)
PER : Period
bits : 5 - 5 (1 bit)
CC0 : Compare Channel 0
bits : 6 - 6 (1 bit)
CC1 : Compare Channel 1
bits : 7 - 7 (1 bit)
8-bit Counter Mode - - COUNT8 Count
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 7 (8 bit)
16-bit Counter Mode - - COUNT16 Count
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 15 (16 bit)
32-bit Counter Mode - - COUNT32 Count
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 31 (32 bit)
COUNT32 Count
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : Counter Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - COUNT8 Period
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PER : Period Value
bits : 0 - 7 (8 bit)
COUNT8 Period
address_offset : 0x1B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PER : Period Value
bits : 0 - 7 (8 bit)
COUNT32 Compare and Capture
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Counter/Compare Value
bits : 0 - 31 (32 bit)
COUNT32 Compare and Capture
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Counter/Compare Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - COUNT8 Period Buffer
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERBUF : Period Buffer Value
bits : 0 - 7 (8 bit)
COUNT8 Period Buffer
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERBUF : Period Buffer Value
bits : 0 - 7 (8 bit)
COUNT32 Compare and Capture Buffer
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Counter/Compare Buffer Value
bits : 0 - 31 (32 bit)
COUNT32 Compare and Capture Buffer
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Counter/Compare Buffer Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - COUNT8 Compare and Capture
address_offset : 0x38 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Counter/Compare Value
bits : 0 - 7 (8 bit)
16-bit Counter Mode - - COUNT16 Compare and Capture
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Counter/Compare Value
bits : 0 - 15 (16 bit)
32-bit Counter Mode - - COUNT32 Compare and Capture
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Counter/Compare Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a start, restart or retrigger
2 : STOP
Force a stop
3 : UPDATE
Force update of double-buffered register
4 : READSYNC
Force a read synchronization of COUNT
5 : DMAOS
One-shot DMA trigger
End of enumeration elements list.
16-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a start, restart or retrigger
2 : STOP
Force a stop
3 : UPDATE
Force update of double-buffered register
4 : READSYNC
Force a read synchronization of COUNT
5 : DMAOS
One-shot DMA trigger
End of enumeration elements list.
32-bit Counter Mode - - Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a start, restart or retrigger
2 : STOP
Force a stop
3 : UPDATE
Force update of double-buffered register
4 : READSYNC
Force a read synchronization of COUNT
5 : DMAOS
One-shot DMA trigger
End of enumeration elements list.
Control B Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a start, restart or retrigger
2 : STOP
Force a stop
3 : UPDATE
Force update of double-buffered register
4 : READSYNC
Force a read synchronization of COUNT
End of enumeration elements list.
8-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a start, restart or retrigger
2 : STOP
Force a stop
3 : UPDATE
Force update of double-buffered register
4 : READSYNC
Force a read synchronization of COUNT
5 : DMAOS
One-shot DMA trigger
End of enumeration elements list.
16-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a start, restart or retrigger
2 : STOP
Force a stop
3 : UPDATE
Force update of double-buffered register
4 : READSYNC
Force a read synchronization of COUNT
5 : DMAOS
One-shot DMA trigger
End of enumeration elements list.
32-bit Counter Mode - - Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a start, restart or retrigger
2 : STOP
Force a stop
3 : UPDATE
Force update of double-buffered register
4 : READSYNC
Force a read synchronization of COUNT
5 : DMAOS
One-shot DMA trigger
End of enumeration elements list.
Control B Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIR : Counter Direction
bits : 0 - 0 (1 bit)
LUPD : Lock Update
bits : 1 - 1 (1 bit)
ONESHOT : One-Shot on Counter
bits : 2 - 2 (1 bit)
CMD : Command
bits : 5 - 7 (3 bit)
Enumeration: CMDSelect
0 : NONE
No action
1 : RETRIGGER
Force a start, restart or retrigger
2 : STOP
Force a stop
3 : UPDATE
Force update of double-buffered register
4 : READSYNC
Force a read synchronization of COUNT
End of enumeration elements list.
8-bit Counter Mode - - COUNT8 Compare and Capture
address_offset : 0x55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Counter/Compare Value
bits : 0 - 7 (8 bit)
16-bit Counter Mode - - COUNT16 Compare and Capture
address_offset : 0x56 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Counter/Compare Value
bits : 0 - 15 (16 bit)
32-bit Counter Mode - - COUNT32 Compare and Capture
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CC : Counter/Compare Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : OFF
Event action disabled
1 : RETRIGGER
Start, restart or retrigger TC on event
2 : COUNT
Count on event
3 : START
Start TC on event
4 : STAMP
Time stamp capture
5 : PPW
Period catured in CC0, pulse width in CC1
6 : PWP
Period catured in CC1, pulse width in CC0
7 : PW
Pulse width capture
End of enumeration elements list.
TCINV : TC Event Input Polarity
bits : 4 - 4 (1 bit)
TCEI : TC Event Enable
bits : 5 - 5 (1 bit)
OVFEO : Event Output Enable
bits : 8 - 8 (1 bit)
MCEO0 : MC Event Output Enable 0
bits : 12 - 12 (1 bit)
MCEO1 : MC Event Output Enable 1
bits : 13 - 13 (1 bit)
16-bit Counter Mode - - Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : OFF
Event action disabled
1 : RETRIGGER
Start, restart or retrigger TC on event
2 : COUNT
Count on event
3 : START
Start TC on event
4 : STAMP
Time stamp capture
5 : PPW
Period catured in CC0, pulse width in CC1
6 : PWP
Period catured in CC1, pulse width in CC0
7 : PW
Pulse width capture
End of enumeration elements list.
TCINV : TC Event Input Polarity
bits : 4 - 4 (1 bit)
TCEI : TC Event Enable
bits : 5 - 5 (1 bit)
OVFEO : Event Output Enable
bits : 8 - 8 (1 bit)
MCEO0 : MC Event Output Enable 0
bits : 12 - 12 (1 bit)
MCEO1 : MC Event Output Enable 1
bits : 13 - 13 (1 bit)
32-bit Counter Mode - - Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : OFF
Event action disabled
1 : RETRIGGER
Start, restart or retrigger TC on event
2 : COUNT
Count on event
3 : START
Start TC on event
4 : STAMP
Time stamp capture
5 : PPW
Period catured in CC0, pulse width in CC1
6 : PWP
Period catured in CC1, pulse width in CC0
7 : PW
Pulse width capture
End of enumeration elements list.
TCINV : TC Event Input Polarity
bits : 4 - 4 (1 bit)
TCEI : TC Event Enable
bits : 5 - 5 (1 bit)
OVFEO : Event Output Enable
bits : 8 - 8 (1 bit)
MCEO0 : MC Event Output Enable 0
bits : 12 - 12 (1 bit)
MCEO1 : MC Event Output Enable 1
bits : 13 - 13 (1 bit)
Event Control
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Event Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : OFF
Event action disabled
1 : RETRIGGER
Start, restart or retrigger TC on event
2 : COUNT
Count on event
3 : START
Start TC on event
4 : STAMP
Time stamp capture
5 : PPW
Period catured in CC0, pulse width in CC1
6 : PWP
Period catured in CC1, pulse width in CC0
7 : PW
Pulse width capture
End of enumeration elements list.
TCINV : TC Event Input Polarity
bits : 4 - 4 (1 bit)
TCEI : TC Event Enable
bits : 5 - 5 (1 bit)
OVFEO : Event Output Enable
bits : 8 - 8 (1 bit)
MCEO0 : MC Event Output Enable 0
bits : 12 - 12 (1 bit)
MCEO1 : MC Event Output Enable 1
bits : 13 - 13 (1 bit)
8-bit Counter Mode - - COUNT8 Compare and Capture Buffer
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Counter/Compare Buffer Value
bits : 0 - 7 (8 bit)
16-bit Counter Mode - - COUNT16 Compare and Capture Buffer
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Counter/Compare Buffer Value
bits : 0 - 15 (16 bit)
32-bit Counter Mode - - COUNT32 Compare and Capture Buffer
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Counter/Compare Buffer Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Disable
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Disable
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Disable 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Disable 1
bits : 5 - 5 (1 bit)
16-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Disable
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Disable
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Disable 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Disable 1
bits : 5 - 5 (1 bit)
32-bit Counter Mode - - Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Disable
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Disable
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Disable 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Disable 1
bits : 5 - 5 (1 bit)
Interrupt Enable Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Disable
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Disable
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Disable 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Disable 1
bits : 5 - 5 (1 bit)
8-bit Counter Mode - - Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Enable
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Enable 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Enable 1
bits : 5 - 5 (1 bit)
16-bit Counter Mode - - Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Enable
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Enable 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Enable 1
bits : 5 - 5 (1 bit)
32-bit Counter Mode - - Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Enable
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Enable 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Enable 1
bits : 5 - 5 (1 bit)
Interrupt Enable Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Enable
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Enable
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Enable 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Enable 1
bits : 5 - 5 (1 bit)
8-bit Counter Mode - - COUNT8 Compare and Capture Buffer
address_offset : 0x91 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Counter/Compare Buffer Value
bits : 0 - 7 (8 bit)
16-bit Counter Mode - - COUNT16 Compare and Capture Buffer
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Counter/Compare Buffer Value
bits : 0 - 15 (16 bit)
32-bit Counter Mode - - COUNT32 Compare and Capture Buffer
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCBUF : Counter/Compare Buffer Value
bits : 0 - 31 (32 bit)
8-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Flag
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Flag
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Flag 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Flag 1
bits : 5 - 5 (1 bit)
16-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Flag
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Flag
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Flag 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Flag 1
bits : 5 - 5 (1 bit)
32-bit Counter Mode - - Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Flag
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Flag
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Flag 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Flag 1
bits : 5 - 5 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVF : OVF Interrupt Flag
bits : 0 - 0 (1 bit)
ERR : ERR Interrupt Flag
bits : 1 - 1 (1 bit)
MC0 : MC Interrupt Flag 0
bits : 4 - 4 (1 bit)
MC1 : MC Interrupt Flag 1
bits : 5 - 5 (1 bit)
8-bit Counter Mode - - Status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop Status Flag
bits : 0 - 0 (1 bit)
SLAVE : Slave Status Flag
bits : 1 - 1 (1 bit)
PERBUFV : Synchronization Busy Status
bits : 3 - 3 (1 bit)
CCBUFV0 : Compare channel buffer 0 valid
bits : 4 - 4 (1 bit)
CCBUFV1 : Compare channel buffer 1 valid
bits : 5 - 5 (1 bit)
16-bit Counter Mode - - Status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop Status Flag
bits : 0 - 0 (1 bit)
SLAVE : Slave Status Flag
bits : 1 - 1 (1 bit)
PERBUFV : Synchronization Busy Status
bits : 3 - 3 (1 bit)
CCBUFV0 : Compare channel buffer 0 valid
bits : 4 - 4 (1 bit)
CCBUFV1 : Compare channel buffer 1 valid
bits : 5 - 5 (1 bit)
32-bit Counter Mode - - Status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop Status Flag
bits : 0 - 0 (1 bit)
SLAVE : Slave Status Flag
bits : 1 - 1 (1 bit)
PERBUFV : Synchronization Busy Status
bits : 3 - 3 (1 bit)
CCBUFV0 : Compare channel buffer 0 valid
bits : 4 - 4 (1 bit)
CCBUFV1 : Compare channel buffer 1 valid
bits : 5 - 5 (1 bit)
Status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOP : Stop Status Flag
bits : 0 - 0 (1 bit)
SLAVE : Slave Status Flag
bits : 1 - 1 (1 bit)
PERBUFV : Synchronization Busy Status
bits : 3 - 3 (1 bit)
CCBUFV0 : Compare channel buffer 0 valid
bits : 4 - 4 (1 bit)
CCBUFV1 : Compare channel buffer 1 valid
bits : 5 - 5 (1 bit)
8-bit Counter Mode - - Waveform Generation Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAVEGEN : Waveform Generation Mode
bits : 0 - 1 (2 bit)
Enumeration: WAVEGENSelect
0 : NFRQ
Normal frequency
1 : MFRQ
Match frequency
2 : NPWM
Normal PWM
3 : MPWM
Match PWM
End of enumeration elements list.
16-bit Counter Mode - - Waveform Generation Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAVEGEN : Waveform Generation Mode
bits : 0 - 1 (2 bit)
Enumeration: WAVEGENSelect
0 : NFRQ
Normal frequency
1 : MFRQ
Match frequency
2 : NPWM
Normal PWM
3 : MPWM
Match PWM
End of enumeration elements list.
32-bit Counter Mode - - Waveform Generation Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAVEGEN : Waveform Generation Mode
bits : 0 - 1 (2 bit)
Enumeration: WAVEGENSelect
0 : NFRQ
Normal frequency
1 : MFRQ
Match frequency
2 : NPWM
Normal PWM
3 : MPWM
Match PWM
End of enumeration elements list.
Waveform Generation Control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAVEGEN : Waveform Generation Mode
bits : 0 - 1 (2 bit)
Enumeration: WAVEGENSelect
0 : NFRQ
Normal frequency
1 : MFRQ
Match frequency
2 : NPWM
Normal PWM
3 : MPWM
Match PWM
End of enumeration elements list.
8-bit Counter Mode - - Control C
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEN0 : Output Waveform Invert Enable 0
bits : 0 - 0 (1 bit)
INVEN1 : Output Waveform Invert Enable 1
bits : 1 - 1 (1 bit)
16-bit Counter Mode - - Control C
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEN0 : Output Waveform Invert Enable 0
bits : 0 - 0 (1 bit)
INVEN1 : Output Waveform Invert Enable 1
bits : 1 - 1 (1 bit)
32-bit Counter Mode - - Control C
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEN0 : Output Waveform Invert Enable 0
bits : 0 - 0 (1 bit)
INVEN1 : Output Waveform Invert Enable 1
bits : 1 - 1 (1 bit)
Control C
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEN0 : Output Waveform Invert Enable 0
bits : 0 - 0 (1 bit)
INVEN1 : Output Waveform Invert Enable 1
bits : 1 - 1 (1 bit)
8-bit Counter Mode - - Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)
16-bit Counter Mode - - Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)
32-bit Counter Mode - - Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)
Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Run During Debug
bits : 0 - 0 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.