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SystemControl

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD8C byte (0x0)
mem_usage : registers
protection : not protected

Registers

PFR[0]

MMFR[0]

ISAR[0]

PFR[1]

MMFR[1]

ISAR[1]

MMFR[2]

ISAR[2]

ICTR

MMFR[3]

ISAR[3]

ISAR[4]

ACTLR

CPUID

ICSR

VTOR

AIRCR

SCR

CCR

SHPR1

SHPR2

SHPR3

SHCSR

CFSR

HFSR

DFSR

MMFAR

BFAR

AFSR

PFR0

PFR1

DFR

ADR

MMFR0

MMFR1

MMFR2

MMFR3

ISAR0

ISAR1

ISAR2

ISAR3

ISAR4

CPACR


PFR[0]

Processor Feature Register
address_offset : 0x1A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR[0] PFR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMFR[0]

Memory Model Feature Register
address_offset : 0x1AA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMFR[0] MMFR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR[0]

Instruction Set Attributes Register
address_offset : 0x1AC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR[0] ISAR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PFR[1]

Processor Feature Register
address_offset : 0x27C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR[1] PFR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMFR[1]

Memory Model Feature Register
address_offset : 0x27F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMFR[1] MMFR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR[1]

Instruction Set Attributes Register
address_offset : 0x2824 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR[1] ISAR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMFR[2]

Memory Model Feature Register
address_offset : 0x354C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMFR[2] MMFR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR[2]

Instruction Set Attributes Register
address_offset : 0x358C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR[2] ISAR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ICTR

Interrupt Controller Type Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ICTR ICTR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTLINESNUM

INTLINESNUM :
bits : 0 - 3 (4 bit)


MMFR[3]

Memory Model Feature Register
address_offset : 0x42A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMFR[3] MMFR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR[3]

Instruction Set Attributes Register
address_offset : 0x42F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR[3] ISAR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR[4]

Instruction Set Attributes Register
address_offset : 0x5068 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR[4] ISAR[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ACTLR

Auxiliary Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTLR ACTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DISMCYCINT DISDEFWBUF DISFOLD DISFPCA DISOOFP

DISMCYCINT : Disable interruption of LDM/STM instructions
bits : 0 - 0 (1 bit)

DISDEFWBUF : Disable wruite buffer use during default memory map accesses
bits : 1 - 1 (1 bit)

DISFOLD : Disable IT folding
bits : 2 - 2 (1 bit)

DISFPCA : Disable automatic update of CONTROL.FPCA
bits : 8 - 8 (1 bit)

DISOOFP : Disable out-of-order FP instructions
bits : 9 - 9 (1 bit)


CPUID

CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPUID CPUID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REVISION PARTNO CONSTANT VARIANT IMPLEMENTER

REVISION : Processor revision number
bits : 0 - 3 (4 bit)

PARTNO : Process Part Number, 0xC24=Cortex-M4
bits : 4 - 15 (12 bit)

CONSTANT : Constant
bits : 16 - 19 (4 bit)

VARIANT : Variant number
bits : 20 - 23 (4 bit)

IMPLEMENTER : Implementer code, 0x41=ARM
bits : 24 - 31 (8 bit)


ICSR

Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSR ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTACTIVE RETTOBASE VECTPENDING ISRPENDING ISRPREEMPT PENDSTCLR PENDSTSET PENDSVCLR PENDSVSET NMIPENDSET

VECTACTIVE : Active exception number
bits : 0 - 8 (9 bit)

RETTOBASE : No preempted active exceptions to execute
bits : 11 - 11 (1 bit)

VECTPENDING : Exception number of the highest priority pending enabled exception
bits : 12 - 17 (6 bit)

ISRPENDING : Interrupt pending flag
bits : 22 - 22 (1 bit)

ISRPREEMPT : Debug only
bits : 23 - 23 (1 bit)

PENDSTCLR : SysTick clear-pending bit
bits : 25 - 25 (1 bit)

Enumeration: PENDSTCLRSelect

0 : VALUE_0

No effect

1 : VALUE_1

Removes the pending state from the SysTick exception

End of enumeration elements list.

PENDSTSET : SysTick set-pending bit
bits : 26 - 26 (1 bit)

Enumeration: PENDSTSETSelect

0 : VALUE_0

Write: no effect; read: SysTick exception is not pending

1 : VALUE_1

Write: changes SysTick exception state to pending; read: SysTick exception is pending

End of enumeration elements list.

PENDSVCLR : PendSV clear-pending bit
bits : 27 - 27 (1 bit)

Enumeration: PENDSVCLRSelect

0 : VALUE_0

No effect

1 : VALUE_1

Removes the pending state from the PendSV exception

End of enumeration elements list.

PENDSVSET : PendSV set-pending bit
bits : 28 - 28 (1 bit)

Enumeration: PENDSVSETSelect

0 : VALUE_0

Write: no effect; read: PendSV exception is not pending

1 : VALUE_1

Write: changes PendSV exception state to pending; read: PendSV exception is pending

End of enumeration elements list.

NMIPENDSET : NMI set-pending bit
bits : 31 - 31 (1 bit)

Enumeration: NMIPENDSETSelect

0 : VALUE_0

Write: no effect; read: NMI exception is not pending

1 : VALUE_1

Write: changes NMI exception state to pending; read: NMI exception is pending

End of enumeration elements list.


VTOR

Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTOR VTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBLOFF

TBLOFF : Vector table base offset
bits : 7 - 31 (25 bit)


AIRCR

Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AIRCR AIRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTRESET VECTCLRACTIVE SYSRESETREQ PRIGROUP ENDIANNESS VECTKEY

VECTRESET : Must write 0
bits : 0 - 0 (1 bit)

VECTCLRACTIVE : Must write 0
bits : 1 - 1 (1 bit)

SYSRESETREQ : System Reset Request
bits : 2 - 2 (1 bit)

Enumeration: SYSRESETREQSelect

0 : VALUE_0

No system reset request

1 : VALUE_1

Asserts a signal to the outer system that requests a reset

End of enumeration elements list.

PRIGROUP : Interrupt priority grouping
bits : 8 - 10 (3 bit)

ENDIANNESS : Data endianness, 0=little, 1=big
bits : 15 - 15 (1 bit)

Enumeration: ENDIANNESSSelect

0 : VALUE_0

Little-endian

1 : VALUE_1

Big-endian

End of enumeration elements list.

VECTKEY : Register key
bits : 16 - 31 (16 bit)


SCR

System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEPONEXIT SLEEPDEEP SEVONPEND

SLEEPONEXIT : Sleep-on-exit on handler return
bits : 1 - 1 (1 bit)

Enumeration: SLEEPONEXITSelect

0 : VALUE_0

Do not sleep when returning to Thread mode

1 : VALUE_1

Enter sleep, or deep sleep, on return from an ISR

End of enumeration elements list.

SLEEPDEEP : Deep Sleep used as low power mode
bits : 2 - 2 (1 bit)

Enumeration: SLEEPDEEPSelect

0 : VALUE_0

Sleep

1 : VALUE_1

Deep sleep

End of enumeration elements list.

SEVONPEND : Send Event on Pending bit
bits : 4 - 4 (1 bit)

Enumeration: SEVONPENDSelect

0 : VALUE_0

Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded

1 : VALUE_1

Enabled events and all interrupts, including disabled interrupts, can wakeup the processor

End of enumeration elements list.


CCR

Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NONBASETHRDENA USERSETMPEND UNALIGN_TRP DIV_0_TRP BFHFNMIGN STKALIGN

NONBASETHRDENA : Indicates how processor enters Thread mode
bits : 0 - 0 (1 bit)

USERSETMPEND : Enables unprivileged software access to STIR register
bits : 1 - 1 (1 bit)

UNALIGN_TRP : Enables unaligned access traps
bits : 3 - 3 (1 bit)

Enumeration: UNALIGN_TRPSelect

0 : VALUE_0

Do not trap unaligned halfword and word accesses

1 : VALUE_1

Trap unaligned halfword and word accesses

End of enumeration elements list.

DIV_0_TRP : Enables divide by 0 trap
bits : 4 - 4 (1 bit)

BFHFNMIGN : Ignore LDM/STM BusFault for -1/-2 priority handlers
bits : 8 - 8 (1 bit)

STKALIGN : Indicates stack alignment on exception entry
bits : 9 - 9 (1 bit)

Enumeration: STKALIGNSelect

0 : VALUE_0

4-byte aligned

1 : VALUE_1

8-byte aligned

End of enumeration elements list.


SHPR1

System Handler Priority Register 1
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR1 SHPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4 PRI_5 PRI_6

PRI_4 : Priority of system handler 4, MemManage
bits : 0 - 7 (8 bit)

PRI_5 : Priority of system handler 5, BusFault
bits : 8 - 15 (8 bit)

PRI_6 : Priority of system handler 6, UsageFault
bits : 16 - 23 (8 bit)


SHPR2

System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR2 SHPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_11

PRI_11 : Priority of system handler 11, SVCall
bits : 24 - 31 (8 bit)


SHPR3

System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR3 SHPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_14 PRI_15

PRI_14 : Priority of system handler 14, PendSV
bits : 16 - 23 (8 bit)

PRI_15 : Priority of system handler 15, SysTick exception
bits : 24 - 31 (8 bit)


SHCSR

System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHCSR SHCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMFAULTACT BUSFAULTACT USGFAULTACT SVCALLACT MONITORACT PENDSVACT SYSTICKACT USGFAULTPENDED MEMFAULTPENDED BUSFAULTPENDED SVCALLPENDED MEMFAULTENA BUSFAULTENA USGFAULTENA

MEMFAULTACT : MemManage exception active bit
bits : 0 - 0 (1 bit)

BUSFAULTACT : BusFault exception active bit
bits : 1 - 1 (1 bit)

USGFAULTACT : UsageFault exception active bit
bits : 3 - 3 (1 bit)

SVCALLACT : SVCall active bit
bits : 7 - 7 (1 bit)

MONITORACT : DebugMonitor exception active bit
bits : 8 - 8 (1 bit)

PENDSVACT : PendSV exception active bit
bits : 10 - 10 (1 bit)

SYSTICKACT : SysTick exception active bit
bits : 11 - 11 (1 bit)

USGFAULTPENDED : UsageFault exception pending bit
bits : 12 - 12 (1 bit)

MEMFAULTPENDED : MemManage exception pending bit
bits : 13 - 13 (1 bit)

BUSFAULTPENDED : BusFault exception pending bit
bits : 14 - 14 (1 bit)

SVCALLPENDED : SVCall pending bit
bits : 15 - 15 (1 bit)

MEMFAULTENA : MemManage enable bit
bits : 16 - 16 (1 bit)

BUSFAULTENA : BusFault enable bit
bits : 17 - 17 (1 bit)

USGFAULTENA : UsageFault enable bit
bits : 18 - 18 (1 bit)


CFSR

Configurable Fault Status Register
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFSR CFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IACCVIOL DACCVIOL MUNSTKERR MSTKERR MLSPERR MMARVALID IBUSERR PRECISERR IMPRECISERR UNSTKERR STKERR LSPERR BFARVALID UNDEFINSTR INVSTATE INVPC NOCP UNALIGNED DIVBYZERO

IACCVIOL : Instruction access violation
bits : 0 - 0 (1 bit)

DACCVIOL : Data access violation
bits : 1 - 1 (1 bit)

MUNSTKERR : MemManage Fault on unstacking for exception return
bits : 3 - 3 (1 bit)

MSTKERR : MemManage Fault on stacking for exception entry
bits : 4 - 4 (1 bit)

MLSPERR : MemManager Fault occured during FP lazy state preservation
bits : 5 - 5 (1 bit)

MMARVALID : MemManage Fault Address Register valid
bits : 7 - 7 (1 bit)

IBUSERR : Instruction bus error
bits : 8 - 8 (1 bit)

PRECISERR : Precise data bus error
bits : 9 - 9 (1 bit)

IMPRECISERR : Imprecise data bus error
bits : 10 - 10 (1 bit)

UNSTKERR : BusFault on unstacking for exception return
bits : 11 - 11 (1 bit)

STKERR : BusFault on stacking for exception entry
bits : 12 - 12 (1 bit)

LSPERR : BusFault occured during FP lazy state preservation
bits : 13 - 13 (1 bit)

BFARVALID : BusFault Address Register valid
bits : 15 - 15 (1 bit)

UNDEFINSTR : Undefined instruction UsageFault
bits : 16 - 16 (1 bit)

INVSTATE : Invalid state UsageFault
bits : 17 - 17 (1 bit)

INVPC : Invalid PC load UsageFault
bits : 18 - 18 (1 bit)

NOCP : No coprocessor UsageFault
bits : 19 - 19 (1 bit)

UNALIGNED : Unaligned access UsageFault
bits : 24 - 24 (1 bit)

DIVBYZERO : Divide by zero UsageFault
bits : 25 - 25 (1 bit)


HFSR

HardFault Status Register
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFSR HFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTTBL FORCED DEBUGEVT

VECTTBL : BusFault on a Vector Table read during exception processing
bits : 1 - 1 (1 bit)

FORCED : Forced Hard Fault
bits : 30 - 30 (1 bit)

DEBUGEVT : Debug: always write 0
bits : 31 - 31 (1 bit)


DFSR

Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFSR DFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALTED BKPT DWTTRAP VCATCH EXTERNAL

HALTED :
bits : 0 - 0 (1 bit)

BKPT :
bits : 1 - 1 (1 bit)

DWTTRAP :
bits : 2 - 2 (1 bit)

VCATCH :
bits : 3 - 3 (1 bit)

EXTERNAL :
bits : 4 - 4 (1 bit)


MMFAR

MemManage Fault Address Register
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMFAR MMFAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Address that generated the MemManage fault
bits : 0 - 31 (32 bit)


BFAR

BusFault Address Register
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BFAR BFAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Address that generated the BusFault
bits : 0 - 31 (32 bit)


AFSR

Auxiliary Fault Status Register
address_offset : 0xD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFSR AFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMPDEF

IMPDEF : AUXFAULT input signals
bits : 0 - 31 (32 bit)


PFR0

Processor Feature Register
address_offset : 0xD40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR0 PFR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PFR1

Processor Feature Register
address_offset : 0xD44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PFR1 PFR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DFR

Debug Feature Register
address_offset : 0xD48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFR DFR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADR

Auxiliary Feature Register
address_offset : 0xD4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADR ADR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMFR0

Memory Model Feature Register
address_offset : 0xD50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMFR0 MMFR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMFR1

Memory Model Feature Register
address_offset : 0xD54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMFR1 MMFR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMFR2

Memory Model Feature Register
address_offset : 0xD58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMFR2 MMFR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MMFR3

Memory Model Feature Register
address_offset : 0xD5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MMFR3 MMFR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR0

Instruction Set Attributes Register
address_offset : 0xD60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR0 ISAR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR1

Instruction Set Attributes Register
address_offset : 0xD64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR1 ISAR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR2

Instruction Set Attributes Register
address_offset : 0xD68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR2 ISAR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR3

Instruction Set Attributes Register
address_offset : 0xD6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR3 ISAR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ISAR4

Instruction Set Attributes Register
address_offset : 0xD70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISAR4 ISAR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CPACR

Coprocessor Access Control Register
address_offset : 0xD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPACR CPACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP10 CP11

CP10 : Access privileges for coprocessor 10
bits : 20 - 21 (2 bit)

Enumeration: CP10Select

0 : DENIED

Access denied

1 : PRIV

Privileged access only

3 : FULL

Full access

End of enumeration elements list.

CP11 : Access privileges for coprocessor 11
bits : 22 - 23 (2 bit)

Enumeration: CP11Select

0 : DENIED

Access denied

1 : PRIV

Privileged access only

3 : FULL

Full access

End of enumeration elements list.



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