\n
address_offset : 0x0 Bytes (0x0)
size : 0xD8C byte (0x0)
mem_usage : registers
protection : not protected
Processor Feature Register
address_offset : 0x1A80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature Register
address_offset : 0x1AA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0x1AC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Processor Feature Register
address_offset : 0x27C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature Register
address_offset : 0x27F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0x2824 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature Register
address_offset : 0x354C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0x358C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Interrupt Controller Type Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTLINESNUM :
bits : 0 - 3 (4 bit)
Memory Model Feature Register
address_offset : 0x42A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0x42F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0x5068 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Auxiliary Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISMCYCINT : Disable interruption of LDM/STM instructions
bits : 0 - 0 (1 bit)
DISDEFWBUF : Disable wruite buffer use during default memory map accesses
bits : 1 - 1 (1 bit)
DISFOLD : Disable IT folding
bits : 2 - 2 (1 bit)
DISFPCA : Disable automatic update of CONTROL.FPCA
bits : 8 - 8 (1 bit)
DISOOFP : Disable out-of-order FP instructions
bits : 9 - 9 (1 bit)
CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Processor revision number
bits : 0 - 3 (4 bit)
PARTNO : Process Part Number, 0xC24=Cortex-M4
bits : 4 - 15 (12 bit)
CONSTANT : Constant
bits : 16 - 19 (4 bit)
VARIANT : Variant number
bits : 20 - 23 (4 bit)
IMPLEMENTER : Implementer code, 0x41=ARM
bits : 24 - 31 (8 bit)
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Active exception number
bits : 0 - 8 (9 bit)
RETTOBASE : No preempted active exceptions to execute
bits : 11 - 11 (1 bit)
VECTPENDING : Exception number of the highest priority pending enabled exception
bits : 12 - 17 (6 bit)
ISRPENDING : Interrupt pending flag
bits : 22 - 22 (1 bit)
ISRPREEMPT : Debug only
bits : 23 - 23 (1 bit)
PENDSTCLR : SysTick clear-pending bit
bits : 25 - 25 (1 bit)
Enumeration: PENDSTCLRSelect
0 : VALUE_0
No effect
1 : VALUE_1
Removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick set-pending bit
bits : 26 - 26 (1 bit)
Enumeration: PENDSTSETSelect
0 : VALUE_0
Write: no effect; read: SysTick exception is not pending
1 : VALUE_1
Write: changes SysTick exception state to pending; read: SysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV clear-pending bit
bits : 27 - 27 (1 bit)
Enumeration: PENDSVCLRSelect
0 : VALUE_0
No effect
1 : VALUE_1
Removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV set-pending bit
bits : 28 - 28 (1 bit)
Enumeration: PENDSVSETSelect
0 : VALUE_0
Write: no effect; read: PendSV exception is not pending
1 : VALUE_1
Write: changes PendSV exception state to pending; read: PendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI set-pending bit
bits : 31 - 31 (1 bit)
Enumeration: NMIPENDSETSelect
0 : VALUE_0
Write: no effect; read: NMI exception is not pending
1 : VALUE_1
Write: changes NMI exception state to pending; read: NMI exception is pending
End of enumeration elements list.
Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector table base offset
bits : 7 - 31 (25 bit)
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTRESET : Must write 0
bits : 0 - 0 (1 bit)
VECTCLRACTIVE : Must write 0
bits : 1 - 1 (1 bit)
SYSRESETREQ : System Reset Request
bits : 2 - 2 (1 bit)
Enumeration: SYSRESETREQSelect
0 : VALUE_0
No system reset request
1 : VALUE_1
Asserts a signal to the outer system that requests a reset
End of enumeration elements list.
PRIGROUP : Interrupt priority grouping
bits : 8 - 10 (3 bit)
ENDIANNESS : Data endianness, 0=little, 1=big
bits : 15 - 15 (1 bit)
Enumeration: ENDIANNESSSelect
0 : VALUE_0
Little-endian
1 : VALUE_1
Big-endian
End of enumeration elements list.
VECTKEY : Register key
bits : 16 - 31 (16 bit)
System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep-on-exit on handler return
bits : 1 - 1 (1 bit)
Enumeration: SLEEPONEXITSelect
0 : VALUE_0
Do not sleep when returning to Thread mode
1 : VALUE_1
Enter sleep, or deep sleep, on return from an ISR
End of enumeration elements list.
SLEEPDEEP : Deep Sleep used as low power mode
bits : 2 - 2 (1 bit)
Enumeration: SLEEPDEEPSelect
0 : VALUE_0
Sleep
1 : VALUE_1
Deep sleep
End of enumeration elements list.
SEVONPEND : Send Event on Pending bit
bits : 4 - 4 (1 bit)
Enumeration: SEVONPENDSelect
0 : VALUE_0
Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1 : VALUE_1
Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
End of enumeration elements list.
Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONBASETHRDENA : Indicates how processor enters Thread mode
bits : 0 - 0 (1 bit)
USERSETMPEND : Enables unprivileged software access to STIR register
bits : 1 - 1 (1 bit)
UNALIGN_TRP : Enables unaligned access traps
bits : 3 - 3 (1 bit)
Enumeration: UNALIGN_TRPSelect
0 : VALUE_0
Do not trap unaligned halfword and word accesses
1 : VALUE_1
Trap unaligned halfword and word accesses
End of enumeration elements list.
DIV_0_TRP : Enables divide by 0 trap
bits : 4 - 4 (1 bit)
BFHFNMIGN : Ignore LDM/STM BusFault for -1/-2 priority handlers
bits : 8 - 8 (1 bit)
STKALIGN : Indicates stack alignment on exception entry
bits : 9 - 9 (1 bit)
Enumeration: STKALIGNSelect
0 : VALUE_0
4-byte aligned
1 : VALUE_1
8-byte aligned
End of enumeration elements list.
System Handler Priority Register 1
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of system handler 4, MemManage
bits : 0 - 7 (8 bit)
PRI_5 : Priority of system handler 5, BusFault
bits : 8 - 15 (8 bit)
PRI_6 : Priority of system handler 6, UsageFault
bits : 16 - 23 (8 bit)
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of system handler 11, SVCall
bits : 24 - 31 (8 bit)
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of system handler 14, PendSV
bits : 16 - 23 (8 bit)
PRI_15 : Priority of system handler 15, SysTick exception
bits : 24 - 31 (8 bit)
System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : MemManage exception active bit
bits : 0 - 0 (1 bit)
BUSFAULTACT : BusFault exception active bit
bits : 1 - 1 (1 bit)
USGFAULTACT : UsageFault exception active bit
bits : 3 - 3 (1 bit)
SVCALLACT : SVCall active bit
bits : 7 - 7 (1 bit)
MONITORACT : DebugMonitor exception active bit
bits : 8 - 8 (1 bit)
PENDSVACT : PendSV exception active bit
bits : 10 - 10 (1 bit)
SYSTICKACT : SysTick exception active bit
bits : 11 - 11 (1 bit)
USGFAULTPENDED : UsageFault exception pending bit
bits : 12 - 12 (1 bit)
MEMFAULTPENDED : MemManage exception pending bit
bits : 13 - 13 (1 bit)
BUSFAULTPENDED : BusFault exception pending bit
bits : 14 - 14 (1 bit)
SVCALLPENDED : SVCall pending bit
bits : 15 - 15 (1 bit)
MEMFAULTENA : MemManage enable bit
bits : 16 - 16 (1 bit)
BUSFAULTENA : BusFault enable bit
bits : 17 - 17 (1 bit)
USGFAULTENA : UsageFault enable bit
bits : 18 - 18 (1 bit)
Configurable Fault Status Register
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IACCVIOL : Instruction access violation
bits : 0 - 0 (1 bit)
DACCVIOL : Data access violation
bits : 1 - 1 (1 bit)
MUNSTKERR : MemManage Fault on unstacking for exception return
bits : 3 - 3 (1 bit)
MSTKERR : MemManage Fault on stacking for exception entry
bits : 4 - 4 (1 bit)
MLSPERR : MemManager Fault occured during FP lazy state preservation
bits : 5 - 5 (1 bit)
MMARVALID : MemManage Fault Address Register valid
bits : 7 - 7 (1 bit)
IBUSERR : Instruction bus error
bits : 8 - 8 (1 bit)
PRECISERR : Precise data bus error
bits : 9 - 9 (1 bit)
IMPRECISERR : Imprecise data bus error
bits : 10 - 10 (1 bit)
UNSTKERR : BusFault on unstacking for exception return
bits : 11 - 11 (1 bit)
STKERR : BusFault on stacking for exception entry
bits : 12 - 12 (1 bit)
LSPERR : BusFault occured during FP lazy state preservation
bits : 13 - 13 (1 bit)
BFARVALID : BusFault Address Register valid
bits : 15 - 15 (1 bit)
UNDEFINSTR : Undefined instruction UsageFault
bits : 16 - 16 (1 bit)
INVSTATE : Invalid state UsageFault
bits : 17 - 17 (1 bit)
INVPC : Invalid PC load UsageFault
bits : 18 - 18 (1 bit)
NOCP : No coprocessor UsageFault
bits : 19 - 19 (1 bit)
UNALIGNED : Unaligned access UsageFault
bits : 24 - 24 (1 bit)
DIVBYZERO : Divide by zero UsageFault
bits : 25 - 25 (1 bit)
HardFault Status Register
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTTBL : BusFault on a Vector Table read during exception processing
bits : 1 - 1 (1 bit)
FORCED : Forced Hard Fault
bits : 30 - 30 (1 bit)
DEBUGEVT : Debug: always write 0
bits : 31 - 31 (1 bit)
Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED :
bits : 0 - 0 (1 bit)
BKPT :
bits : 1 - 1 (1 bit)
DWTTRAP :
bits : 2 - 2 (1 bit)
VCATCH :
bits : 3 - 3 (1 bit)
EXTERNAL :
bits : 4 - 4 (1 bit)
MemManage Fault Address Register
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address that generated the MemManage fault
bits : 0 - 31 (32 bit)
BusFault Address Register
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Address that generated the BusFault
bits : 0 - 31 (32 bit)
Auxiliary Fault Status Register
address_offset : 0xD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMPDEF : AUXFAULT input signals
bits : 0 - 31 (32 bit)
Processor Feature Register
address_offset : 0xD40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Processor Feature Register
address_offset : 0xD44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Debug Feature Register
address_offset : 0xD48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Auxiliary Feature Register
address_offset : 0xD4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature Register
address_offset : 0xD50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature Register
address_offset : 0xD54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature Register
address_offset : 0xD58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature Register
address_offset : 0xD5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0xD60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0xD64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0xD68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0xD6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Instruction Set Attributes Register
address_offset : 0xD70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Coprocessor Access Control Register
address_offset : 0xD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP10 : Access privileges for coprocessor 10
bits : 20 - 21 (2 bit)
Enumeration: CP10Select
0 : DENIED
Access denied
1 : PRIV
Privileged access only
3 : FULL
Full access
End of enumeration elements list.
CP11 : Access privileges for coprocessor 11
bits : 22 - 23 (2 bit)
Enumeration: CP11Select
0 : DENIED
Access denied
1 : PRIV
Privileged access only
3 : FULL
Full access
End of enumeration elements list.
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