\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Enable Clear
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKRDY : Clock Ready Interrupt Enable
bits : 0 - 0 (1 bit)
AHB Mask
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPB0_ : HPB0 AHB Clock Mask
bits : 0 - 0 (1 bit)
HPB1_ : HPB1 AHB Clock Mask
bits : 1 - 1 (1 bit)
HPB2_ : HPB2 AHB Clock Mask
bits : 2 - 2 (1 bit)
HPB3_ : HPB3 AHB Clock Mask
bits : 3 - 3 (1 bit)
DSU_ : DSU AHB Clock Mask
bits : 4 - 4 (1 bit)
HMATRIX_ : HMATRIX AHB Clock Mask
bits : 5 - 5 (1 bit)
NVMCTRL_ : NVMCTRL AHB Clock Mask
bits : 6 - 6 (1 bit)
HSRAM_ : HSRAM AHB Clock Mask
bits : 7 - 7 (1 bit)
CMCC_ : CMCC AHB Clock Mask
bits : 8 - 8 (1 bit)
DMAC_ : DMAC AHB Clock Mask
bits : 9 - 9 (1 bit)
USB_ : USB AHB Clock Mask
bits : 10 - 10 (1 bit)
BKUPRAM_ : BKUPRAM AHB Clock Mask
bits : 11 - 11 (1 bit)
PAC_ : PAC AHB Clock Mask
bits : 12 - 12 (1 bit)
QSPI_ : QSPI AHB Clock Mask
bits : 13 - 13 (1 bit)
GMAC_ : GMAC AHB Clock Mask
bits : 14 - 14 (1 bit)
SDHC0_ : SDHC0 AHB Clock Mask
bits : 15 - 15 (1 bit)
ICM_ : ICM AHB Clock Mask
bits : 19 - 19 (1 bit)
PUKCC_ : PUKCC AHB Clock Mask
bits : 20 - 20 (1 bit)
QSPI_2X_ : QSPI_2X AHB Clock Mask
bits : 21 - 21 (1 bit)
NVMCTRL_SMEEPROM_ : NVMCTRL_SMEEPROM AHB Clock Mask
bits : 22 - 22 (1 bit)
NVMCTRL_CACHE_ : NVMCTRL_CACHE AHB Clock Mask
bits : 23 - 23 (1 bit)
APBA Mask
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAC_ : PAC APB Clock Enable
bits : 0 - 0 (1 bit)
PM_ : PM APB Clock Enable
bits : 1 - 1 (1 bit)
MCLK_ : MCLK APB Clock Enable
bits : 2 - 2 (1 bit)
RSTC_ : RSTC APB Clock Enable
bits : 3 - 3 (1 bit)
OSCCTRL_ : OSCCTRL APB Clock Enable
bits : 4 - 4 (1 bit)
OSC32KCTRL_ : OSC32KCTRL APB Clock Enable
bits : 5 - 5 (1 bit)
SUPC_ : SUPC APB Clock Enable
bits : 6 - 6 (1 bit)
GCLK_ : GCLK APB Clock Enable
bits : 7 - 7 (1 bit)
WDT_ : WDT APB Clock Enable
bits : 8 - 8 (1 bit)
RTC_ : RTC APB Clock Enable
bits : 9 - 9 (1 bit)
EIC_ : EIC APB Clock Enable
bits : 10 - 10 (1 bit)
FREQM_ : FREQM APB Clock Enable
bits : 11 - 11 (1 bit)
SERCOM0_ : SERCOM0 APB Clock Enable
bits : 12 - 12 (1 bit)
SERCOM1_ : SERCOM1 APB Clock Enable
bits : 13 - 13 (1 bit)
TC0_ : TC0 APB Clock Enable
bits : 14 - 14 (1 bit)
TC1_ : TC1 APB Clock Enable
bits : 15 - 15 (1 bit)
APBB Mask
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_ : USB APB Clock Enable
bits : 0 - 0 (1 bit)
DSU_ : DSU APB Clock Enable
bits : 1 - 1 (1 bit)
NVMCTRL_ : NVMCTRL APB Clock Enable
bits : 2 - 2 (1 bit)
PORT_ : PORT APB Clock Enable
bits : 4 - 4 (1 bit)
HMATRIX_ : HMATRIX APB Clock Enable
bits : 6 - 6 (1 bit)
EVSYS_ : EVSYS APB Clock Enable
bits : 7 - 7 (1 bit)
SERCOM2_ : SERCOM2 APB Clock Enable
bits : 9 - 9 (1 bit)
SERCOM3_ : SERCOM3 APB Clock Enable
bits : 10 - 10 (1 bit)
TCC0_ : TCC0 APB Clock Enable
bits : 11 - 11 (1 bit)
TCC1_ : TCC1 APB Clock Enable
bits : 12 - 12 (1 bit)
TC2_ : TC2 APB Clock Enable
bits : 13 - 13 (1 bit)
TC3_ : TC3 APB Clock Enable
bits : 14 - 14 (1 bit)
RAMECC_ : RAMECC APB Clock Enable
bits : 16 - 16 (1 bit)
APBC Mask
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GMAC_ : GMAC APB Clock Enable
bits : 2 - 2 (1 bit)
TCC2_ : TCC2 APB Clock Enable
bits : 3 - 3 (1 bit)
TCC3_ : TCC3 APB Clock Enable
bits : 4 - 4 (1 bit)
TC4_ : TC4 APB Clock Enable
bits : 5 - 5 (1 bit)
TC5_ : TC5 APB Clock Enable
bits : 6 - 6 (1 bit)
PDEC_ : PDEC APB Clock Enable
bits : 7 - 7 (1 bit)
AC_ : AC APB Clock Enable
bits : 8 - 8 (1 bit)
AES_ : AES APB Clock Enable
bits : 9 - 9 (1 bit)
TRNG_ : TRNG APB Clock Enable
bits : 10 - 10 (1 bit)
ICM_ : ICM APB Clock Enable
bits : 11 - 11 (1 bit)
QSPI_ : QSPI APB Clock Enable
bits : 13 - 13 (1 bit)
CCL_ : CCL APB Clock Enable
bits : 14 - 14 (1 bit)
Interrupt Enable Set
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKRDY : Clock Ready Interrupt Enable
bits : 0 - 0 (1 bit)
APBD Mask
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SERCOM4_ : SERCOM4 APB Clock Enable
bits : 0 - 0 (1 bit)
SERCOM5_ : SERCOM5 APB Clock Enable
bits : 1 - 1 (1 bit)
TCC4_ : TCC4 APB Clock Enable
bits : 4 - 4 (1 bit)
ADC0_ : ADC0 APB Clock Enable
bits : 7 - 7 (1 bit)
ADC1_ : ADC1 APB Clock Enable
bits : 8 - 8 (1 bit)
DAC_ : DAC APB Clock Enable
bits : 9 - 9 (1 bit)
I2S_ : I2S APB Clock Enable
bits : 10 - 10 (1 bit)
PCC_ : PCC APB Clock Enable
bits : 11 - 11 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKRDY : Clock Ready
bits : 0 - 0 (1 bit)
HS Clock Division
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DIV : CPU Clock Division Factor
bits : 0 - 7 (8 bit)
Enumeration: DIVSelect
1 : DIV1
Divide by 1
End of enumeration elements list.
CPU Clock Division
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Low-Power Clock Division Factor
bits : 0 - 7 (8 bit)
Enumeration: DIVSelect
1 : DIV1
Divide by 1
2 : DIV2
Divide by 2
4 : DIV4
Divide by 4
8 : DIV8
Divide by 8
16 : DIV16
Divide by 16
32 : DIV32
Divide by 32
64 : DIV64
Divide by 64
128 : DIV128
Divide by 128
End of enumeration elements list.
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