Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x360 byte (0x0)
mem_usage : registers
protection : not protected
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[1]-CHANNEL[0]-CHPRILVL
CHANNEL[1]-CHANNEL[0]-CHEVCTRL
CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Control
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
DMAENABLE : DMA Enable
bits : 1 - 1 (1 bit)
LVLEN0 : Priority Level 0 Enable
bits : 8 - 8 (1 bit)
LVLEN1 : Priority Level 1 Enable
bits : 9 - 9 (1 bit)
LVLEN2 : Priority Level 2 Enable
bits : 10 - 10 (1 bit)
LVLEN3 : Priority Level 3 Enable
bits : 11 - 11 (1 bit)
Channel n Control A
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Software Trigger Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRIG0 : Channel 0 Software Trigger
bits : 0 - 0 (1 bit)
SWTRIG1 : Channel 1 Software Trigger
bits : 1 - 1 (1 bit)
SWTRIG2 : Channel 2 Software Trigger
bits : 2 - 2 (1 bit)
SWTRIG3 : Channel 3 Software Trigger
bits : 3 - 3 (1 bit)
SWTRIG4 : Channel 4 Software Trigger
bits : 4 - 4 (1 bit)
SWTRIG5 : Channel 5 Software Trigger
bits : 5 - 5 (1 bit)
SWTRIG6 : Channel 6 Software Trigger
bits : 6 - 6 (1 bit)
SWTRIG7 : Channel 7 Software Trigger
bits : 7 - 7 (1 bit)
SWTRIG8 : Channel 8 Software Trigger
bits : 8 - 8 (1 bit)
SWTRIG9 : Channel 9 Software Trigger
bits : 9 - 9 (1 bit)
SWTRIG10 : Channel 10 Software Trigger
bits : 10 - 10 (1 bit)
SWTRIG11 : Channel 11 Software Trigger
bits : 11 - 11 (1 bit)
SWTRIG12 : Channel 12 Software Trigger
bits : 12 - 12 (1 bit)
SWTRIG13 : Channel 13 Software Trigger
bits : 13 - 13 (1 bit)
SWTRIG14 : Channel 14 Software Trigger
bits : 14 - 14 (1 bit)
SWTRIG15 : Channel 15 Software Trigger
bits : 15 - 15 (1 bit)
SWTRIG16 : Channel 16 Software Trigger
bits : 16 - 16 (1 bit)
SWTRIG17 : Channel 17 Software Trigger
bits : 17 - 17 (1 bit)
SWTRIG18 : Channel 18 Software Trigger
bits : 18 - 18 (1 bit)
SWTRIG19 : Channel 19 Software Trigger
bits : 19 - 19 (1 bit)
SWTRIG20 : Channel 20 Software Trigger
bits : 20 - 20 (1 bit)
SWTRIG21 : Channel 21 Software Trigger
bits : 21 - 21 (1 bit)
SWTRIG22 : Channel 22 Software Trigger
bits : 22 - 22 (1 bit)
SWTRIG23 : Channel 23 Software Trigger
bits : 23 - 23 (1 bit)
SWTRIG24 : Channel 24 Software Trigger
bits : 24 - 24 (1 bit)
SWTRIG25 : Channel 25 Software Trigger
bits : 25 - 25 (1 bit)
SWTRIG26 : Channel 26 Software Trigger
bits : 26 - 26 (1 bit)
SWTRIG27 : Channel 27 Software Trigger
bits : 27 - 27 (1 bit)
SWTRIG28 : Channel 28 Software Trigger
bits : 28 - 28 (1 bit)
SWTRIG29 : Channel 29 Software Trigger
bits : 29 - 29 (1 bit)
SWTRIG30 : Channel 30 Software Trigger
bits : 30 - 30 (1 bit)
SWTRIG31 : Channel 31 Software Trigger
bits : 31 - 31 (1 bit)
Channel n Control A
address_offset : 0x10E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x10E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x10E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x10E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x10EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x10ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x10EE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x10EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x1260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x1264 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x1265 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x1266 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x126C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x126D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x126E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x126F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x13F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x13F4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x13F5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x13F6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x13FC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x13FD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x13FE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x13FF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Priority Control 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LVLPRI0 : Level 0 Channel Priority Number
bits : 0 - 4 (5 bit)
QOS0 : Level 0 Quality of Service
bits : 5 - 6 (2 bit)
Enumeration: QOS0Select
0 : REGULAR
Regular delivery
1 : SHORTAGE
Bandwidth shortage
2 : SENSITIVE
Latency sensitive
3 : CRITICAL
Latency critical
End of enumeration elements list.
RRLVLEN0 : Level 0 Round-Robin Scheduling Enable
bits : 7 - 7 (1 bit)
LVLPRI1 : Level 1 Channel Priority Number
bits : 8 - 12 (5 bit)
QOS1 : Level 1 Quality of Service
bits : 13 - 14 (2 bit)
Enumeration: QOS1Select
0 : REGULAR
Regular delivery
1 : SHORTAGE
Bandwidth shortage
2 : SENSITIVE
Latency sensitive
3 : CRITICAL
Latency critical
End of enumeration elements list.
RRLVLEN1 : Level 1 Round-Robin Scheduling Enable
bits : 15 - 15 (1 bit)
LVLPRI2 : Level 2 Channel Priority Number
bits : 16 - 20 (5 bit)
QOS2 : Level 2 Quality of Service
bits : 21 - 22 (2 bit)
Enumeration: QOS2Select
0 : REGULAR
Regular delivery
1 : SHORTAGE
Bandwidth shortage
2 : SENSITIVE
Latency sensitive
3 : CRITICAL
Latency critical
End of enumeration elements list.
RRLVLEN2 : Level 2 Round-Robin Scheduling Enable
bits : 23 - 23 (1 bit)
LVLPRI3 : Level 3 Channel Priority Number
bits : 24 - 28 (5 bit)
QOS3 : Level 3 Quality of Service
bits : 29 - 30 (2 bit)
Enumeration: QOS3Select
0 : REGULAR
Regular delivery
1 : SHORTAGE
Bandwidth shortage
2 : SENSITIVE
Latency sensitive
3 : CRITICAL
Latency critical
End of enumeration elements list.
RRLVLEN3 : Level 3 Round-Robin Scheduling Enable
bits : 31 - 31 (1 bit)
Channel n Control A
address_offset : 0x1590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x1594 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x1595 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x1596 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x159C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x159D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x159E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x159F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x164 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x165 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x16D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x16E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x16F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x1740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x1744 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x1745 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x1746 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x174C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x174D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x174E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x174F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x1900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x1904 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x1905 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x1906 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x190C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x190D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x190E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x190F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x1AD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x1AD4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x1AD5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x1AD6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x1ADC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x1ADD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x1ADE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x1ADF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x1CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x1CB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x1CB5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x1CB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x1CBC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x1CBD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x1CBE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x1CBF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Control A
address_offset : 0x1EA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x1EA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x1EA5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x1EA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x1EAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x1EAD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x1EAE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x1EAF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x1EC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x1ED Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x1EE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x1EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
CRC Control
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCBEATSIZE : CRC Beat Size
bits : 0 - 1 (2 bit)
Enumeration: CRCBEATSIZESelect
0 : BYTE
8-bit bus transfer
1 : HWORD
16-bit bus transfer
2 : WORD
32-bit bus transfer
End of enumeration elements list.
CRCPOLY : CRC Polynomial Type
bits : 2 - 3 (2 bit)
Enumeration: CRCPOLYSelect
0 : CRC16
CRC-16 (CRC-CCITT)
1 : CRC32
CRC32 (IEEE 802.3)
End of enumeration elements list.
CRCSRC : CRC Input Source
bits : 8 - 13 (6 bit)
Enumeration: CRCSRCSelect
0 : DISABLE
CRC Disabled
1 : IO
I/O interface
End of enumeration elements list.
CRCMODE : CRC Operating Mode
bits : 14 - 15 (2 bit)
Enumeration: CRCMODESelect
0 : DEFAULT
Default operating mode
2 : CRCMON
Memory CRC monitor operating mode
3 : CRCGEN
Memory CRC generation operating mode
End of enumeration elements list.
Interrupt Pending
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Channel ID
bits : 0 - 4 (5 bit)
TERR : Transfer Error
bits : 8 - 8 (1 bit)
TCMPL : Transfer Complete
bits : 9 - 9 (1 bit)
SUSP : Channel Suspend
bits : 10 - 10 (1 bit)
CRCERR : CRC Error
bits : 12 - 12 (1 bit)
FERR : Fetch Error
bits : 13 - 13 (1 bit)
BUSY : Busy
bits : 14 - 14 (1 bit)
PEND : Pending
bits : 15 - 15 (1 bit)
Channel n Control A
address_offset : 0x20A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x20A4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x20A5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x20A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x20AC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x20AD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x20AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x20AF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x22B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x22B4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x22B5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x22B6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x22BC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x22BD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x22BE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x22BF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Interrupt Status
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHINT0 : Channel 0 Pending Interrupt
bits : 0 - 0 (1 bit)
CHINT1 : Channel 1 Pending Interrupt
bits : 1 - 1 (1 bit)
CHINT2 : Channel 2 Pending Interrupt
bits : 2 - 2 (1 bit)
CHINT3 : Channel 3 Pending Interrupt
bits : 3 - 3 (1 bit)
CHINT4 : Channel 4 Pending Interrupt
bits : 4 - 4 (1 bit)
CHINT5 : Channel 5 Pending Interrupt
bits : 5 - 5 (1 bit)
CHINT6 : Channel 6 Pending Interrupt
bits : 6 - 6 (1 bit)
CHINT7 : Channel 7 Pending Interrupt
bits : 7 - 7 (1 bit)
CHINT8 : Channel 8 Pending Interrupt
bits : 8 - 8 (1 bit)
CHINT9 : Channel 9 Pending Interrupt
bits : 9 - 9 (1 bit)
CHINT10 : Channel 10 Pending Interrupt
bits : 10 - 10 (1 bit)
CHINT11 : Channel 11 Pending Interrupt
bits : 11 - 11 (1 bit)
CHINT12 : Channel 12 Pending Interrupt
bits : 12 - 12 (1 bit)
CHINT13 : Channel 13 Pending Interrupt
bits : 13 - 13 (1 bit)
CHINT14 : Channel 14 Pending Interrupt
bits : 14 - 14 (1 bit)
CHINT15 : Channel 15 Pending Interrupt
bits : 15 - 15 (1 bit)
CHINT16 : Channel 16 Pending Interrupt
bits : 16 - 16 (1 bit)
CHINT17 : Channel 17 Pending Interrupt
bits : 17 - 17 (1 bit)
CHINT18 : Channel 18 Pending Interrupt
bits : 18 - 18 (1 bit)
CHINT19 : Channel 19 Pending Interrupt
bits : 19 - 19 (1 bit)
CHINT20 : Channel 20 Pending Interrupt
bits : 20 - 20 (1 bit)
CHINT21 : Channel 21 Pending Interrupt
bits : 21 - 21 (1 bit)
CHINT22 : Channel 22 Pending Interrupt
bits : 22 - 22 (1 bit)
CHINT23 : Channel 23 Pending Interrupt
bits : 23 - 23 (1 bit)
CHINT24 : Channel 24 Pending Interrupt
bits : 24 - 24 (1 bit)
CHINT25 : Channel 25 Pending Interrupt
bits : 25 - 25 (1 bit)
CHINT26 : Channel 26 Pending Interrupt
bits : 26 - 26 (1 bit)
CHINT27 : Channel 27 Pending Interrupt
bits : 27 - 27 (1 bit)
CHINT28 : Channel 28 Pending Interrupt
bits : 28 - 28 (1 bit)
CHINT29 : Channel 29 Pending Interrupt
bits : 29 - 29 (1 bit)
CHINT30 : Channel 30 Pending Interrupt
bits : 30 - 30 (1 bit)
CHINT31 : Channel 31 Pending Interrupt
bits : 31 - 31 (1 bit)
Channel n Control A
address_offset : 0x24D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x24D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x24D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x24D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x24DC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x24DD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x24DE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x24DF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control A
address_offset : 0x2700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x2704 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x2705 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x2706 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x270C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x270D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x270E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x270F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control B
address_offset : 0x274 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x275 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x276 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x27C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x27D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x27E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x27F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Busy Channels
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSYCH0 : Busy Channel 0
bits : 0 - 0 (1 bit)
BUSYCH1 : Busy Channel 1
bits : 1 - 1 (1 bit)
BUSYCH2 : Busy Channel 2
bits : 2 - 2 (1 bit)
BUSYCH3 : Busy Channel 3
bits : 3 - 3 (1 bit)
BUSYCH4 : Busy Channel 4
bits : 4 - 4 (1 bit)
BUSYCH5 : Busy Channel 5
bits : 5 - 5 (1 bit)
BUSYCH6 : Busy Channel 6
bits : 6 - 6 (1 bit)
BUSYCH7 : Busy Channel 7
bits : 7 - 7 (1 bit)
BUSYCH8 : Busy Channel 8
bits : 8 - 8 (1 bit)
BUSYCH9 : Busy Channel 9
bits : 9 - 9 (1 bit)
BUSYCH10 : Busy Channel 10
bits : 10 - 10 (1 bit)
BUSYCH11 : Busy Channel 11
bits : 11 - 11 (1 bit)
BUSYCH12 : Busy Channel 12
bits : 12 - 12 (1 bit)
BUSYCH13 : Busy Channel 13
bits : 13 - 13 (1 bit)
BUSYCH14 : Busy Channel 14
bits : 14 - 14 (1 bit)
BUSYCH15 : Busy Channel 15
bits : 15 - 15 (1 bit)
BUSYCH16 : Busy Channel 16
bits : 16 - 16 (1 bit)
BUSYCH17 : Busy Channel 17
bits : 17 - 17 (1 bit)
BUSYCH18 : Busy Channel 18
bits : 18 - 18 (1 bit)
BUSYCH19 : Busy Channel 19
bits : 19 - 19 (1 bit)
BUSYCH20 : Busy Channel 20
bits : 20 - 20 (1 bit)
BUSYCH21 : Busy Channel 21
bits : 21 - 21 (1 bit)
BUSYCH22 : Busy Channel 22
bits : 22 - 22 (1 bit)
BUSYCH23 : Busy Channel 23
bits : 23 - 23 (1 bit)
BUSYCH24 : Busy Channel 24
bits : 24 - 24 (1 bit)
BUSYCH25 : Busy Channel 25
bits : 25 - 25 (1 bit)
BUSYCH26 : Busy Channel 26
bits : 26 - 26 (1 bit)
BUSYCH27 : Busy Channel 27
bits : 27 - 27 (1 bit)
BUSYCH28 : Busy Channel 28
bits : 28 - 28 (1 bit)
BUSYCH29 : Busy Channel 29
bits : 29 - 29 (1 bit)
BUSYCH30 : Busy Channel 30
bits : 30 - 30 (1 bit)
BUSYCH31 : Busy Channel 31
bits : 31 - 31 (1 bit)
Pending Channels
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PENDCH0 : Pending Channel 0
bits : 0 - 0 (1 bit)
PENDCH1 : Pending Channel 1
bits : 1 - 1 (1 bit)
PENDCH2 : Pending Channel 2
bits : 2 - 2 (1 bit)
PENDCH3 : Pending Channel 3
bits : 3 - 3 (1 bit)
PENDCH4 : Pending Channel 4
bits : 4 - 4 (1 bit)
PENDCH5 : Pending Channel 5
bits : 5 - 5 (1 bit)
PENDCH6 : Pending Channel 6
bits : 6 - 6 (1 bit)
PENDCH7 : Pending Channel 7
bits : 7 - 7 (1 bit)
PENDCH8 : Pending Channel 8
bits : 8 - 8 (1 bit)
PENDCH9 : Pending Channel 9
bits : 9 - 9 (1 bit)
PENDCH10 : Pending Channel 10
bits : 10 - 10 (1 bit)
PENDCH11 : Pending Channel 11
bits : 11 - 11 (1 bit)
PENDCH12 : Pending Channel 12
bits : 12 - 12 (1 bit)
PENDCH13 : Pending Channel 13
bits : 13 - 13 (1 bit)
PENDCH14 : Pending Channel 14
bits : 14 - 14 (1 bit)
PENDCH15 : Pending Channel 15
bits : 15 - 15 (1 bit)
PENDCH16 : Pending Channel 16
bits : 16 - 16 (1 bit)
PENDCH17 : Pending Channel 17
bits : 17 - 17 (1 bit)
PENDCH18 : Pending Channel 18
bits : 18 - 18 (1 bit)
PENDCH19 : Pending Channel 19
bits : 19 - 19 (1 bit)
PENDCH20 : Pending Channel 20
bits : 20 - 20 (1 bit)
PENDCH21 : Pending Channel 21
bits : 21 - 21 (1 bit)
PENDCH22 : Pending Channel 22
bits : 22 - 22 (1 bit)
PENDCH23 : Pending Channel 23
bits : 23 - 23 (1 bit)
PENDCH24 : Pending Channel 24
bits : 24 - 24 (1 bit)
PENDCH25 : Pending Channel 25
bits : 25 - 25 (1 bit)
PENDCH26 : Pending Channel 26
bits : 26 - 26 (1 bit)
PENDCH27 : Pending Channel 27
bits : 27 - 27 (1 bit)
PENDCH28 : Pending Channel 28
bits : 28 - 28 (1 bit)
PENDCH29 : Pending Channel 29
bits : 29 - 29 (1 bit)
PENDCH30 : Pending Channel 30
bits : 30 - 30 (1 bit)
PENDCH31 : Pending Channel 31
bits : 31 - 31 (1 bit)
Active Channel and Levels
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LVLEX0 : Level 0 Channel Trigger Request Executing
bits : 0 - 0 (1 bit)
LVLEX1 : Level 1 Channel Trigger Request Executing
bits : 1 - 1 (1 bit)
LVLEX2 : Level 2 Channel Trigger Request Executing
bits : 2 - 2 (1 bit)
LVLEX3 : Level 3 Channel Trigger Request Executing
bits : 3 - 3 (1 bit)
ID : Active Channel ID
bits : 8 - 12 (5 bit)
ABUSY : Active Channel Busy
bits : 15 - 15 (1 bit)
BTCNT : Active Channel Block Transfer Count
bits : 16 - 31 (16 bit)
Channel n Control A
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x314 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x315 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x316 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x31C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x31D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x31E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x31F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Descriptor Memory Section Base Address
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASEADDR : Descriptor Memory Base Address
bits : 0 - 31 (32 bit)
Write-Back Memory Section Base Address
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRBADDR : Write-Back Memory Base Address
bits : 0 - 31 (32 bit)
Channel n Control A
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x3C4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x3C5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x3C6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x3CC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x3CD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x3CE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x3CF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
CRC Data Input
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCDATAIN : CRC Data Input
bits : 0 - 31 (32 bit)
Channel n Control B
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0x0 : NOACT
No action
0x1 : SUSPEND
Channel suspend operation
0x2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Control A
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x44 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Control A
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x484 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x485 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x486 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x48C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x48D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x48E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x48F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Priority Level
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Control A
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x554 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x555 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x556 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x55C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x55D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x55E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x55F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Event Control
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Control A
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x634 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x635 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x636 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x63C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x63D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x63E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x63F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x724 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x725 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x726 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x72C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x72D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x72E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x72F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
CRC Checksum
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCCHKSUM : CRC Checksum
bits : 0 - 31 (32 bit)
Channel n Control A
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x824 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x825 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x826 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x82C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x82D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x82E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x82F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control A
address_offset : 0x930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0x934 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x935 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x936 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x93C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x93D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x93E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x93F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control B
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0x95 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0x96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x9D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x9E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0x9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0xA50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0xA54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0xA55 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0xA56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xA5C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xA5D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xA5E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0xA5F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0xB84 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0xB85 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0xB86 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xB8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xB8D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xB8E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0xB8F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
CRC Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCBUSY : CRC Module Busy
bits : 0 - 0 (1 bit)
CRCZERO : CRC Zero
bits : 1 - 1 (1 bit)
CRCERR : CRC Error
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Control A
address_offset : 0xCC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0xCC4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0xCC5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0xCC6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xCCC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xCCD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xCCE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0xCCF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Debug Control
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRUN : Debug Run
bits : 0 - 0 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Control A
address_offset : 0xE10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0xE14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0xE15 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0xE16 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xE1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xE1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xE1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0xE1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Status
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Control A
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0xF5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Control A
address_offset : 0xF70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Channel Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Channel Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Channel Run in Standby
bits : 6 - 6 (1 bit)
TRIGSRC : Trigger Source
bits : 8 - 14 (7 bit)
Enumeration: TRIGSRCSelect
0 : DISABLE
Only software/event triggers
End of enumeration elements list.
TRIGACT : Trigger Action
bits : 20 - 21 (2 bit)
Enumeration: TRIGACTSelect
0 : BLOCK
One trigger required for each block transfer
2 : BURST
One trigger required for each burst transfer
3 : TRANSACTION
One trigger required for each transaction
End of enumeration elements list.
BURSTLEN : Burst Length
bits : 24 - 27 (4 bit)
Enumeration: BURSTLENSelect
0 : SINGLE
Single-beat burst length
1 : 2BEAT
2-beats burst length
2 : 3BEAT
3-beats burst length
3 : 4BEAT
4-beats burst length
4 : 5BEAT
5-beats burst length
5 : 6BEAT
6-beats burst length
6 : 7BEAT
7-beats burst length
7 : 8BEAT
8-beats burst length
8 : 9BEAT
9-beats burst length
9 : 10BEAT
10-beats burst length
10 : 11BEAT
11-beats burst length
11 : 12BEAT
12-beats burst length
12 : 13BEAT
13-beats burst length
13 : 14BEAT
14-beats burst length
14 : 15BEAT
15-beats burst length
15 : 16BEAT
16-beats burst length
End of enumeration elements list.
THRESHOLD : FIFO Threshold
bits : 28 - 29 (2 bit)
Enumeration: THRESHOLDSelect
0 : 1BEAT
Destination write starts after each beat source address read
1 : 2BEATS
Destination write starts after 2-beats source address read
2 : 4BEATS
Destination write starts after 4-beats source address read
3 : 8BEATS
Destination write starts after 8-beats source address read
End of enumeration elements list.
Channel n Control B
address_offset : 0xF74 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : Software Command
bits : 0 - 1 (2 bit)
Enumeration: CMDSelect
0 : NOACT
No action
1 : SUSPEND
Channel suspend operation
2 : RESUME
Channel resume operation
End of enumeration elements list.
Channel n Priority Level
address_offset : 0xF75 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRILVL : Channel Priority Level
bits : 0 - 1 (2 bit)
Enumeration: PRILVLSelect
0 : LVL0
Channel Priority Level 0 (Lowest Level)
1 : LVL1
Channel Priority Level 1
2 : LVL2
Channel Priority Level 2
3 : LVL3
Channel Priority Level 3 (Highest Level)
End of enumeration elements list.
Channel n Event Control
address_offset : 0xF76 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVACT : Channel Event Input Action
bits : 0 - 2 (3 bit)
Enumeration: EVACTSelect
0 : NOACT
No action
1 : TRIG
Transfer and periodic transfer trigger
2 : CTRIG
Conditional transfer trigger
3 : CBLOCK
Conditional block transfer
4 : SUSPEND
Channel suspend operation
5 : RESUME
Channel resume operation
6 : SSKIP
Skip next block suspend action
7 : INCPRI
Increase priority
End of enumeration elements list.
EVOMODE : Channel Event Output Mode
bits : 4 - 5 (2 bit)
Enumeration: EVOMODESelect
0 : DEFAULT
Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
1 : TRIGACT
Ongoing trigger action
End of enumeration elements list.
EVIE : Channel Event Input Enable
bits : 6 - 6 (1 bit)
EVOE : Channel Event Output Enable
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xF7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xF7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xF7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0xF7F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xFC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xFD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error Interrupt Enable
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete Interrupt Enable
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend Interrupt Enable
bits : 2 - 2 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xFE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TERR : Channel Transfer Error
bits : 0 - 0 (1 bit)
TCMPL : Channel Transfer Complete
bits : 1 - 1 (1 bit)
SUSP : Channel Suspend
bits : 2 - 2 (1 bit)
Channel n Status
address_offset : 0xFF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEND : Channel Pending
bits : 0 - 0 (1 bit)
BUSY : Channel Busy
bits : 1 - 1 (1 bit)
FERR : Channel Fetch Error
bits : 2 - 2 (1 bit)
CRCERR : Channel CRC Error
bits : 3 - 3 (1 bit)
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