Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
DEVICE_ENDPOINT[0]-EPSTATUSCLR
DEVICE_ENDPOINT[0]-EPSTATUSSET
DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG
HOST_PIPE[1]-HOST_PIPE[0]-PCFG
HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL
DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR
HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR
DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET
HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET
DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS
HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS
DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG
HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG
DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR
HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR
DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET
HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET
DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG
HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG
HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL
DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR
HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR
DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET
HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET
DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS
HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS
DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG
HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG
DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR
HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR
DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET
HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET
DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG
HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG
HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL
DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR
HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR
DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET
HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET
DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS
HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS
DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG
HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG
DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR
HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR
DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET
HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET
DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG
HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG
HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL
HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR
HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET
HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS
HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG
HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR
HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET
HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG
HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL
HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR
HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET
HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS
HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG
HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR
HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET
HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG
HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL
HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS
HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG
HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR
HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET
USB is Device - - Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby Mode
bits : 2 - 2 (1 bit)
MODE : Operating Mode
bits : 7 - 7 (1 bit)
Enumeration: MODESelect
0 : DEVICE
Device Mode
1 : HOST
Host Mode
End of enumeration elements list.
USB is Host - - Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby Mode
bits : 2 - 2 (1 bit)
MODE : Operating Mode
bits : 7 - 7 (1 bit)
Enumeration: MODESelect
0 : DEVICE
Device Mode
1 : HOST
Host Mode
End of enumeration elements list.
Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
ENABLE : Enable
bits : 1 - 1 (1 bit)
RUNSTDBY : Run in Standby Mode
bits : 2 - 2 (1 bit)
MODE : Operating Mode
bits : 7 - 7 (1 bit)
Enumeration: MODESelect
0 : DEVICE
Device Mode
1 : HOST
Host Mode
End of enumeration elements list.
DEVICE_ENDPOINT End Point Configuration
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
USB is Device - - DEVICE Device Frame Number
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
FNUM : Frame Number
bits : 3 - 13 (11 bit)
FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)
USB is Host - - HOST Host Frame Number
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
FNUM : Frame Number
bits : 3 - 13 (11 bit)
HOST Host Frame Number
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFNUM : Micro Frame Number
bits : 0 - 2 (3 bit)
FNUM : Frame Number
bits : 3 - 13 (11 bit)
FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)
DEVICE_ENDPOINT End Point Configuration
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0x100 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0x104 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0x105 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x109 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
USB is Host - - HOST Host Frame Length
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FLENHIGH : Frame Length
bits : 0 - 7 (8 bit)
HOST Host Frame Length
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FLENHIGH : Frame Length
bits : 0 - 7 (8 bit)
USB is Device - - DEVICE Device Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUSPEND : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)
MSOF : Micro Start of Frame Interrupt Enable in High Speed Mode
bits : 1 - 1 (1 bit)
SOF : Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
EORST : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up Interrupt Enable
bits : 4 - 4 (1 bit)
EORSM : End Of Resume Interrupt Enable
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume Interrupt Enable
bits : 6 - 6 (1 bit)
RAMACER : Ram Access Interrupt Enable
bits : 7 - 7 (1 bit)
LPMNYET : Link Power Management Not Yet Interrupt Enable
bits : 8 - 8 (1 bit)
LPMSUSP : Link Power Management Suspend Interrupt Enable
bits : 9 - 9 (1 bit)
USB is Host - - HOST Host Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSOF : Host Start Of Frame Interrupt Disable
bits : 2 - 2 (1 bit)
RST : BUS Reset Interrupt Disable
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up Interrupt Disable
bits : 4 - 4 (1 bit)
DNRSM : DownStream to Device Interrupt Disable
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume from Device Interrupt Disable
bits : 6 - 6 (1 bit)
RAMACER : Ram Access Interrupt Disable
bits : 7 - 7 (1 bit)
DCONN : Device Connection Interrupt Disable
bits : 8 - 8 (1 bit)
DDISC : Device Disconnection Interrupt Disable
bits : 9 - 9 (1 bit)
HOST Host Interrupt Enable Clear
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUSPEND : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)
MSOF : Micro Start of Frame Interrupt Enable in High Speed Mode
bits : 1 - 1 (1 bit)
SOF : Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
HSOF : Host Start Of Frame Interrupt Disable
bits : 2 - 2 (1 bit)
EORST : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)
RST : BUS Reset Interrupt Disable
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up Interrupt Disable
bits : 4 - 4 (1 bit)
EORSM : End Of Resume Interrupt Enable
bits : 5 - 5 (1 bit)
DNRSM : DownStream to Device Interrupt Disable
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume from Device Interrupt Disable
bits : 6 - 6 (1 bit)
RAMACER : Ram Access Interrupt Disable
bits : 7 - 7 (1 bit)
LPMNYET : Link Power Management Not Yet Interrupt Enable
bits : 8 - 8 (1 bit)
DCONN : Device Connection Interrupt Disable
bits : 8 - 8 (1 bit)
LPMSUSP : Link Power Management Suspend Interrupt Enable
bits : 9 - 9 (1 bit)
DDISC : Device Disconnection Interrupt Disable
bits : 9 - 9 (1 bit)
USB is Device - - DEVICE Device Interrupt Enable Set
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUSPEND : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)
MSOF : Micro Start of Frame Interrupt Enable in High Speed Mode
bits : 1 - 1 (1 bit)
SOF : Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
EORST : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up Interrupt Enable
bits : 4 - 4 (1 bit)
EORSM : End Of Resume Interrupt Enable
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume Interrupt Enable
bits : 6 - 6 (1 bit)
RAMACER : Ram Access Interrupt Enable
bits : 7 - 7 (1 bit)
LPMNYET : Link Power Management Not Yet Interrupt Enable
bits : 8 - 8 (1 bit)
LPMSUSP : Link Power Management Suspend Interrupt Enable
bits : 9 - 9 (1 bit)
USB is Host - - HOST Host Interrupt Enable Set
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSOF : Host Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
RST : Bus Reset Interrupt Enable
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up Interrupt Enable
bits : 4 - 4 (1 bit)
DNRSM : DownStream to the Device Interrupt Enable
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume fromthe device Interrupt Enable
bits : 6 - 6 (1 bit)
RAMACER : Ram Access Interrupt Enable
bits : 7 - 7 (1 bit)
DCONN : Link Power Management Interrupt Enable
bits : 8 - 8 (1 bit)
DDISC : Device Disconnection Interrupt Enable
bits : 9 - 9 (1 bit)
HOST Host Interrupt Enable Set
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUSPEND : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)
MSOF : Micro Start of Frame Interrupt Enable in High Speed Mode
bits : 1 - 1 (1 bit)
SOF : Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
HSOF : Host Start Of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
EORST : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)
RST : Bus Reset Interrupt Enable
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up Interrupt Enable
bits : 4 - 4 (1 bit)
EORSM : End Of Resume Interrupt Enable
bits : 5 - 5 (1 bit)
DNRSM : DownStream to the Device Interrupt Enable
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume fromthe device Interrupt Enable
bits : 6 - 6 (1 bit)
RAMACER : Ram Access Interrupt Enable
bits : 7 - 7 (1 bit)
LPMNYET : Link Power Management Not Yet Interrupt Enable
bits : 8 - 8 (1 bit)
DCONN : Link Power Management Interrupt Enable
bits : 8 - 8 (1 bit)
LPMSUSP : Link Power Management Suspend Interrupt Enable
bits : 9 - 9 (1 bit)
DDISC : Device Disconnection Interrupt Enable
bits : 9 - 9 (1 bit)
USB is Device - - DEVICE Device Interrupt Flag
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUSPEND : Suspend
bits : 0 - 0 (1 bit)
MSOF : Micro Start of Frame in High Speed Mode
bits : 1 - 1 (1 bit)
SOF : Start Of Frame
bits : 2 - 2 (1 bit)
EORST : End of Reset
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up
bits : 4 - 4 (1 bit)
EORSM : End Of Resume
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume
bits : 6 - 6 (1 bit)
RAMACER : Ram Access
bits : 7 - 7 (1 bit)
LPMNYET : Link Power Management Not Yet
bits : 8 - 8 (1 bit)
LPMSUSP : Link Power Management Suspend
bits : 9 - 9 (1 bit)
USB is Host - - HOST Host Interrupt Flag
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSOF : Host Start Of Frame
bits : 2 - 2 (1 bit)
RST : Bus Reset
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up
bits : 4 - 4 (1 bit)
DNRSM : Downstream
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume from the Device
bits : 6 - 6 (1 bit)
RAMACER : Ram Access
bits : 7 - 7 (1 bit)
DCONN : Device Connection
bits : 8 - 8 (1 bit)
DDISC : Device Disconnection
bits : 9 - 9 (1 bit)
HOST Host Interrupt Flag
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUSPEND : Suspend
bits : 0 - 0 (1 bit)
MSOF : Micro Start of Frame in High Speed Mode
bits : 1 - 1 (1 bit)
SOF : Start Of Frame
bits : 2 - 2 (1 bit)
HSOF : Host Start Of Frame
bits : 2 - 2 (1 bit)
EORST : End of Reset
bits : 3 - 3 (1 bit)
RST : Bus Reset
bits : 3 - 3 (1 bit)
WAKEUP : Wake Up
bits : 4 - 4 (1 bit)
EORSM : End Of Resume
bits : 5 - 5 (1 bit)
DNRSM : Downstream
bits : 5 - 5 (1 bit)
UPRSM : Upstream Resume from the Device
bits : 6 - 6 (1 bit)
RAMACER : Ram Access
bits : 7 - 7 (1 bit)
LPMNYET : Link Power Management Not Yet
bits : 8 - 8 (1 bit)
DCONN : Device Connection
bits : 8 - 8 (1 bit)
LPMSUSP : Link Power Management Suspend
bits : 9 - 9 (1 bit)
DDISC : Device Disconnection
bits : 9 - 9 (1 bit)
USB is Device - - Synchronization Busy
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)
USB is Host - - Synchronization Busy
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)
Synchronization Busy
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)
ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)
USB is Device - - DEVICE End Point Interrupt Summary
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPINT0 : End Point 0 Interrupt
bits : 0 - 0 (1 bit)
EPINT1 : End Point 1 Interrupt
bits : 1 - 1 (1 bit)
EPINT2 : End Point 2 Interrupt
bits : 2 - 2 (1 bit)
EPINT3 : End Point 3 Interrupt
bits : 3 - 3 (1 bit)
EPINT4 : End Point 4 Interrupt
bits : 4 - 4 (1 bit)
EPINT5 : End Point 5 Interrupt
bits : 5 - 5 (1 bit)
EPINT6 : End Point 6 Interrupt
bits : 6 - 6 (1 bit)
EPINT7 : End Point 7 Interrupt
bits : 7 - 7 (1 bit)
USB is Host - - HOST Pipe Interrupt Summary
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPINT0 : Pipe 0 Interrupt
bits : 0 - 0 (1 bit)
EPINT1 : Pipe 1 Interrupt
bits : 1 - 1 (1 bit)
EPINT2 : Pipe 2 Interrupt
bits : 2 - 2 (1 bit)
EPINT3 : Pipe 3 Interrupt
bits : 3 - 3 (1 bit)
EPINT4 : Pipe 4 Interrupt
bits : 4 - 4 (1 bit)
EPINT5 : Pipe 5 Interrupt
bits : 5 - 5 (1 bit)
EPINT6 : Pipe 6 Interrupt
bits : 6 - 6 (1 bit)
EPINT7 : Pipe 7 Interrupt
bits : 7 - 7 (1 bit)
DEVICE End Point Interrupt Summary
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPINT0 : End Point 0 Interrupt
bits : 0 - 0 (1 bit)
EPINT1 : End Point 1 Interrupt
bits : 1 - 1 (1 bit)
EPINT2 : End Point 2 Interrupt
bits : 2 - 2 (1 bit)
EPINT3 : End Point 3 Interrupt
bits : 3 - 3 (1 bit)
EPINT4 : End Point 4 Interrupt
bits : 4 - 4 (1 bit)
EPINT5 : End Point 5 Interrupt
bits : 5 - 5 (1 bit)
EPINT6 : End Point 6 Interrupt
bits : 6 - 6 (1 bit)
EPINT7 : End Point 7 Interrupt
bits : 7 - 7 (1 bit)
HOST Pipe Interrupt Summary
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPINT0 : Pipe 0 Interrupt
bits : 0 - 0 (1 bit)
EPINT1 : Pipe 1 Interrupt
bits : 1 - 1 (1 bit)
EPINT2 : Pipe 2 Interrupt
bits : 2 - 2 (1 bit)
EPINT3 : Pipe 3 Interrupt
bits : 3 - 3 (1 bit)
EPINT4 : Pipe 4 Interrupt
bits : 4 - 4 (1 bit)
EPINT5 : Pipe 5 Interrupt
bits : 5 - 5 (1 bit)
EPINT6 : Pipe 6 Interrupt
bits : 6 - 6 (1 bit)
EPINT7 : Pipe 7 Interrupt
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Configuration
address_offset : 0x220 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0x220 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0x223 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x224 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0x224 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x225 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0x225 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x226 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0x226 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x227 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0x227 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x228 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x228 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x229 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x229 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
USB is Device - - Descriptor Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DESCADD : Descriptor Address Value
bits : 0 - 31 (32 bit)
USB is Host - - Descriptor Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DESCADD : Descriptor Address Value
bits : 0 - 31 (32 bit)
Descriptor Address
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DESCADD : Descriptor Address Value
bits : 0 - 31 (32 bit)
USB is Device - - USB PAD Calibration
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRANSP : USB Pad Transp calibration
bits : 0 - 4 (5 bit)
TRANSN : USB Pad Transn calibration
bits : 6 - 10 (5 bit)
TRIM : USB Pad Trim calibration
bits : 12 - 14 (3 bit)
USB is Host - - USB PAD Calibration
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRANSP : USB Pad Transp calibration
bits : 0 - 4 (5 bit)
TRANSN : USB Pad Transn calibration
bits : 6 - 10 (5 bit)
TRIM : USB Pad Trim calibration
bits : 12 - 14 (3 bit)
USB PAD Calibration
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRANSP : USB Pad Transp calibration
bits : 0 - 4 (5 bit)
TRANSN : USB Pad Transn calibration
bits : 6 - 10 (5 bit)
TRIM : USB Pad Trim calibration
bits : 12 - 14 (3 bit)
USB is Device - - USB Quality Of Service
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQOS : Configuration Quality of Service
bits : 0 - 1 (2 bit)
DQOS : Data Quality of Service
bits : 2 - 3 (2 bit)
USB is Host - - USB Quality Of Service
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQOS : Configuration Quality of Service
bits : 0 - 1 (2 bit)
DQOS : Data Quality of Service
bits : 2 - 3 (2 bit)
USB Quality Of Service
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CQOS : Configuration Quality of Service
bits : 0 - 1 (2 bit)
DQOS : Data Quality of Service
bits : 2 - 3 (2 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Configuration
address_offset : 0x360 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0x360 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0x363 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x364 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0x364 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x365 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0x365 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x366 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0x366 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x367 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0x367 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x368 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x368 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x369 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x369 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Configuration
address_offset : 0x4C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0x4C0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0x4C3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x4C4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0x4C4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x4C5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0x4C5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x4C6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0x4C6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x4C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0x4C7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x4C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x4C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x4C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x4C9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Configuration
address_offset : 0x640 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0x640 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0x643 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x644 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0x644 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x645 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0x645 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x646 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0x646 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x647 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0x647 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x648 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x648 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x649 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x649 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Configuration
address_offset : 0x7E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0x7E0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0x7E3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x7E4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0x7E4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x7E5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0x7E5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x7E6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0x7E6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x7E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0x7E7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x7E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x7E8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x7E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x7E9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
USB is Device - - DEVICE Control B
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DETACH : Detach
bits : 0 - 0 (1 bit)
UPRSM : Upstream Resume
bits : 1 - 1 (1 bit)
SPDCONF : Speed Configuration
bits : 2 - 3 (2 bit)
Enumeration: SPDCONFSelect
0 : FS
FS : Full Speed
1 : LS
LS : Low Speed
2 : HS
HS : High Speed capable
3 : HSTM
HSTM: High Speed Test Mode (force high-speed mode for test mode)
End of enumeration elements list.
NREPLY : No Reply
bits : 4 - 4 (1 bit)
TSTJ : Test mode J
bits : 5 - 5 (1 bit)
TSTK : Test mode K
bits : 6 - 6 (1 bit)
TSTPCKT : Test packet mode
bits : 7 - 7 (1 bit)
OPMODE2 : Specific Operational Mode
bits : 8 - 8 (1 bit)
GNAK : Global NAK
bits : 9 - 9 (1 bit)
LPMHDSK : Link Power Management Handshake
bits : 10 - 11 (2 bit)
Enumeration: LPMHDSKSelect
0 : NO
No handshake. LPM is not supported
1 : ACK
ACK
2 : NYET
NYET
3 : STALL
STALL
End of enumeration elements list.
USB is Host - - HOST Control B
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESUME : Send USB Resume
bits : 1 - 1 (1 bit)
SPDCONF : Speed Configuration for Host
bits : 2 - 3 (2 bit)
Enumeration: SPDCONFSelect
0 : NORMAL
Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.
3 : FS
Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.
End of enumeration elements list.
AUTORESUME : Auto Resume Enable
bits : 4 - 4 (1 bit)
TSTJ : Test mode J
bits : 5 - 5 (1 bit)
TSTK : Test mode K
bits : 6 - 6 (1 bit)
SOFE : Start of Frame Generation Enable
bits : 8 - 8 (1 bit)
BUSRESET : Send USB Reset
bits : 9 - 9 (1 bit)
VBUSOK : VBUS is OK
bits : 10 - 10 (1 bit)
L1RESUME : Send L1 Resume
bits : 11 - 11 (1 bit)
HOST Control B
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DETACH : Detach
bits : 0 - 0 (1 bit)
UPRSM : Upstream Resume
bits : 1 - 1 (1 bit)
RESUME : Send USB Resume
bits : 1 - 1 (1 bit)
SPDCONF : Speed Configuration for Host
bits : 2 - 3 (2 bit)
Enumeration: SPDCONFSelect
0x3 : FS
Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.
0x1 : LS
LS : Low Speed
0x2 : HS
HS : High Speed capable
0x3 : HSTM
HSTM: High Speed Test Mode (force high-speed mode for test mode)
0x0 : NORMAL
Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.
End of enumeration elements list.
NREPLY : No Reply
bits : 4 - 4 (1 bit)
AUTORESUME : Auto Resume Enable
bits : 4 - 4 (1 bit)
TSTJ : Test mode J
bits : 5 - 5 (1 bit)
TSTK : Test mode K
bits : 6 - 6 (1 bit)
TSTPCKT : Test packet mode
bits : 7 - 7 (1 bit)
OPMODE2 : Specific Operational Mode
bits : 8 - 8 (1 bit)
SOFE : Start of Frame Generation Enable
bits : 8 - 8 (1 bit)
GNAK : Global NAK
bits : 9 - 9 (1 bit)
BUSRESET : Send USB Reset
bits : 9 - 9 (1 bit)
LPMHDSK : Link Power Management Handshake
bits : 10 - 11 (2 bit)
Enumeration: LPMHDSKSelect
0 : NO
No handshake. LPM is not supported
1 : ACK
ACK
2 : NYET
NYET
3 : STALL
STALL
End of enumeration elements list.
VBUSOK : VBUS is OK
bits : 10 - 10 (1 bit)
L1RESUME : Send L1 Resume
bits : 11 - 11 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Configuration
address_offset : 0x9A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0x9A0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0x9A3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0x9A4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0x9A4 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0x9A5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0x9A5 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0x9A6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0x9A6 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0x9A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0x9A7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0x9A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0x9A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0x9A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0x9A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
USB is Device - - DEVICE Device Address
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADD : Device Address
bits : 0 - 6 (7 bit)
ADDEN : Device Address Enable
bits : 7 - 7 (1 bit)
USB is Host - - HOST Host Start Of Frame Control
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLENC : Frame Length Control
bits : 0 - 3 (4 bit)
FLENCE : Frame Length Control Enable
bits : 7 - 7 (1 bit)
DEVICE Device Address
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADD : Device Address
bits : 0 - 6 (7 bit)
ADDEN : Device Address Enable
bits : 7 - 7 (1 bit)
HOST Host Start Of Frame Control
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLENC : Frame Length Control
bits : 0 - 3 (4 bit)
FLENCE : Frame Length Control Enable
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Configuration
address_offset : 0xB80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPTYPE0 : End Point Type0
bits : 0 - 2 (3 bit)
EPTYPE1 : End Point Type1
bits : 4 - 6 (3 bit)
NYETDIS : NYET Token Disable
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Configuration
address_offset : 0xB80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTOKEN : Pipe Token
bits : 0 - 1 (2 bit)
BK : Pipe Bank
bits : 2 - 2 (1 bit)
PTYPE : Pipe Type
bits : 3 - 5 (3 bit)
HOST_PIPE Bus Access Period of Pipe
address_offset : 0xB83 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITINTERVAL : Bit Interval
bits : 0 - 7 (8 bit)
DEVICE_ENDPOINT End Point Pipe Status Clear
address_offset : 0xB84 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Clear
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Clear
bits : 1 - 1 (1 bit)
CURBK : Current Bank Clear
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Clear
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Clear
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Clear
address_offset : 0xB84 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle clear
bits : 0 - 0 (1 bit)
CURBK : Curren Bank clear
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Clear
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Clear
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Clear
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status Set
address_offset : 0xB85 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle OUT Set
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle IN Set
bits : 1 - 1 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request Set
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request Set
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status Set
address_offset : 0xB85 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle Set
bits : 0 - 0 (1 bit)
CURBK : Current Bank Set
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze Set
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 Ready Set
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 Ready Set
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Pipe Status
address_offset : 0xB86 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGLOUT : Data Toggle Out
bits : 0 - 0 (1 bit)
DTGLIN : Data Toggle In
bits : 1 - 1 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
STALLRQ0 : Stall 0 Request
bits : 4 - 4 (1 bit)
STALLRQ1 : Stall 1 Request
bits : 5 - 5 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
HOST_PIPE End Point Pipe Status
address_offset : 0xB86 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DTGL : Data Toggle
bits : 0 - 0 (1 bit)
CURBK : Current Bank
bits : 2 - 2 (1 bit)
PFREEZE : Pipe Freeze
bits : 4 - 4 (1 bit)
BK0RDY : Bank 0 ready
bits : 6 - 6 (1 bit)
BK1RDY : Bank 1 ready
bits : 7 - 7 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Flag
address_offset : 0xB87 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1
bits : 3 - 3 (1 bit)
RXSTP : Received Setup
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag
address_offset : 0xB87 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Flag
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Flag
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Flag
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Flag
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Flag
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Flag
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Clear Flag
address_offset : 0xB88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Disable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Disable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Disable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/Out Interrupt Disable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/Out Interrupt Disable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Clear
address_offset : 0xB88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Disable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Disable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Disable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Disable
bits : 4 - 4 (1 bit)
STALL : Stall Inetrrupt Disable
bits : 5 - 5 (1 bit)
DEVICE_ENDPOINT End Point Interrupt Set Flag
address_offset : 0xB89 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL0 : Error Flow 0 Interrupt Enable
bits : 2 - 2 (1 bit)
TRFAIL1 : Error Flow 1 Interrupt Enable
bits : 3 - 3 (1 bit)
RXSTP : Received Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL0 : Stall 0 In/out Interrupt enable
bits : 5 - 5 (1 bit)
STALL1 : Stall 1 In/out Interrupt enable
bits : 6 - 6 (1 bit)
HOST_PIPE Pipe Interrupt Flag Set
address_offset : 0xB89 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPT0 : Transfer Complete 0 Interrupt Enable
bits : 0 - 0 (1 bit)
TRCPT1 : Transfer Complete 1 Interrupt Enable
bits : 1 - 1 (1 bit)
TRFAIL : Error Flow Interrupt Enable
bits : 2 - 2 (1 bit)
PERR : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
TXSTP : Transmit Setup Interrupt Enable
bits : 4 - 4 (1 bit)
STALL : Stall Interrupt Enable
bits : 5 - 5 (1 bit)
USB is Device - - DEVICE Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPEED : Speed Status
bits : 2 - 3 (2 bit)
Enumeration: SPEEDSelect
0 : FS
Full-speed mode
1 : LS
Low-speed mode
2 : HS
High-speed mode
End of enumeration elements list.
LINESTATE : USB Line State Status
bits : 6 - 7 (2 bit)
Enumeration: LINESTATESelect
0 : 0
SE0/RESET
1 : 1
FS-J or LS-K State
2 : 2
FS-K or LS-J State
End of enumeration elements list.
USB is Host - - HOST Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPEED : Speed Status
bits : 2 - 3 (2 bit)
LINESTATE : USB Line State Status
bits : 6 - 7 (2 bit)
HOST Status
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPEED : Speed Status
bits : 2 - 3 (2 bit)
Enumeration: SPEEDSelect
0x0 : FS
Full-speed mode
0x1 : LS
Low-speed mode
0x2 : HS
High-speed mode
End of enumeration elements list.
LINESTATE : USB Line State Status
bits : 6 - 7 (2 bit)
Enumeration: LINESTATESelect
0x0 : 0
SE0/RESET
0x1 : 1
FS-J or LS-K State
0x2 : 2
FS-K or LS-J State
End of enumeration elements list.
USB is Device - - Finite State Machine Status
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FSMSTATE : Fine State Machine Status
bits : 0 - 6 (7 bit)
Enumeration: FSMSTATESelect
1 : OFF
OFF (L3). It corresponds to the powered-off, disconnected, and disabled state
2 : ON
ON (L0). It corresponds to the Idle and Active states
4 : SUSPEND
SUSPEND (L2)
8 : SLEEP
SLEEP (L1)
16 : DNRESUME
DNRESUME. Down Stream Resume.
32 : UPRESUME
UPRESUME. Up Stream Resume.
64 : RESET
RESET. USB lines Reset.
End of enumeration elements list.
USB is Host - - Finite State Machine Status
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FSMSTATE : Fine State Machine Status
bits : 0 - 6 (7 bit)
Enumeration: FSMSTATESelect
1 : OFF
OFF (L3). It corresponds to the powered-off, disconnected, and disabled state
2 : ON
ON (L0). It corresponds to the Idle and Active states
4 : SUSPEND
SUSPEND (L2)
8 : SLEEP
SLEEP (L1)
16 : DNRESUME
DNRESUME. Down Stream Resume.
32 : UPRESUME
UPRESUME. Up Stream Resume.
64 : RESET
RESET. USB lines Reset.
End of enumeration elements list.
Finite State Machine Status
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FSMSTATE : Fine State Machine Status
bits : 0 - 6 (7 bit)
Enumeration: FSMSTATESelect
0x1 : OFF
OFF (L3). It corresponds to the powered-off, disconnected, and disabled state
0x2 : ON
ON (L0). It corresponds to the Idle and Active states
0x4 : SUSPEND
SUSPEND (L2)
0x8 : SLEEP
SLEEP (L1)
0x10 : DNRESUME
DNRESUME. Down Stream Resume.
0x20 : UPRESUME
UPRESUME. Up Stream Resume.
0x40 : RESET
RESET. USB lines Reset.
End of enumeration elements list.
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