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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4A byte (0x0)
mem_usage : registers
protection : not protected

Registers

ADC_CTRLA

CTRLA

ADC_GAINCORR

GAINCORR

ADC_OFFSETCORR

OFFSETCORR

ADC_SWTRIG

SWTRIG

ADC_EVCTRL

EVCTRL

ADC_INTENCLR

INTENCLR

ADC_INTENSET

INTENSET

ADC_INTFLAG

INTFLAG

ADC_STATUS

STATUS

ADC_DBGCTRL

DBGCTRL

ADC_SYNCBUSY

SYNCBUSY

ADC_DSEQDATA

DSEQDATA

ADC_DSEQCTRL

DSEQCTRL

ADC_DSEQSTAT

DSEQSTAT

ADC_INPUTCTRL

INPUTCTRL

ADC_RESULT

RESULT

ADC_RESS

RESS

ADC_CALIB

CALIB

ADC_CTRLB

CTRLB

ADC_REFCTRL

REFCTRL

ADC_AVGCTRL

AVGCTRL

ADC_SAMPCTRL

SAMPCTRL

ADC_WINLT

WINLT

ADC_WINUT

WINUT


ADC_CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CTRLA ADC_CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE DUALSEL SLAVEEN RUNSTDBY ONDEMAND PRESCALER R2R

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

DUALSEL : Dual Mode Trigger Selection
bits : 3 - 4 (2 bit)

Enumeration: DUALSELSelect

0 : BOTH

Start event or software trigger will start a conversion on both ADCs

1 : INTERLEAVE

START event or software trigger will alternatingly start a conversion on ADC0 and ADC1

End of enumeration elements list.

SLAVEEN : Slave Enable
bits : 5 - 5 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler Configuration
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0 : DIV2

Peripheral clock divided by 2

1 : DIV4

Peripheral clock divided by 4

2 : DIV8

Peripheral clock divided by 8

3 : DIV16

Peripheral clock divided by 16

4 : DIV32

Peripheral clock divided by 32

5 : DIV64

Peripheral clock divided by 64

6 : DIV128

Peripheral clock divided by 128

7 : DIV256

Peripheral clock divided by 256

End of enumeration elements list.

R2R : Rail to Rail Operation Enable
bits : 15 - 15 (1 bit)


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE DUALSEL SLAVEEN RUNSTDBY ONDEMAND PRESCALER R2R

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)

DUALSEL : Dual Mode Trigger Selection
bits : 3 - 4 (2 bit)

Enumeration: DUALSELSelect

0 : BOTH

Start event or software trigger will start a conversion on both ADCs

1 : INTERLEAVE

START event or software trigger will alternatingly start a conversion on ADC0 and ADC1

End of enumeration elements list.

SLAVEEN : Slave Enable
bits : 5 - 5 (1 bit)

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)

PRESCALER : Prescaler Configuration
bits : 8 - 10 (3 bit)

Enumeration: PRESCALERSelect

0 : DIV2

Peripheral clock divided by 2

1 : DIV4

Peripheral clock divided by 4

2 : DIV8

Peripheral clock divided by 8

3 : DIV16

Peripheral clock divided by 16

4 : DIV32

Peripheral clock divided by 32

5 : DIV64

Peripheral clock divided by 64

6 : DIV128

Peripheral clock divided by 128

7 : DIV256

Peripheral clock divided by 256

End of enumeration elements list.

R2R : Rail to Rail Operation Enable
bits : 15 - 15 (1 bit)


ADC_GAINCORR

Gain Correction
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_GAINCORR ADC_GAINCORR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAINCORR

GAINCORR : Gain Correction Value
bits : 0 - 11 (12 bit)


GAINCORR

Gain Correction
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAINCORR GAINCORR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAINCORR

GAINCORR : Gain Correction Value
bits : 0 - 11 (12 bit)


ADC_OFFSETCORR

Offset Correction
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_OFFSETCORR ADC_OFFSETCORR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSETCORR

OFFSETCORR : Offset Correction Value
bits : 0 - 11 (12 bit)


OFFSETCORR

Offset Correction
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFSETCORR OFFSETCORR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSETCORR

OFFSETCORR : Offset Correction Value
bits : 0 - 11 (12 bit)


ADC_SWTRIG

Software Trigger
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SWTRIG ADC_SWTRIG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLUSH START

FLUSH : ADC Conversion Flush
bits : 0 - 0 (1 bit)

START : Start ADC Conversion
bits : 1 - 1 (1 bit)


SWTRIG

Software Trigger
address_offset : 0x14 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWTRIG SWTRIG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLUSH START

FLUSH : ADC Conversion Flush
bits : 0 - 0 (1 bit)

START : Start ADC Conversion
bits : 1 - 1 (1 bit)


ADC_EVCTRL

Event Control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_EVCTRL ADC_EVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLUSHEI STARTEI FLUSHINV STARTINV RESRDYEO WINMONEO

FLUSHEI : Flush Event Input Enable
bits : 0 - 0 (1 bit)

STARTEI : Start Conversion Event Input Enable
bits : 1 - 1 (1 bit)

FLUSHINV : Flush Event Invert Enable
bits : 2 - 2 (1 bit)

STARTINV : Start Conversion Event Invert Enable
bits : 3 - 3 (1 bit)

RESRDYEO : Result Ready Event Out
bits : 4 - 4 (1 bit)

WINMONEO : Window Monitor Event Out
bits : 5 - 5 (1 bit)


EVCTRL

Event Control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 FLUSHEI STARTEI FLUSHINV STARTINV RESRDYEO WINMONEO

FLUSHEI : Flush Event Input Enable
bits : 0 - 0 (1 bit)

STARTEI : Start Conversion Event Input Enable
bits : 1 - 1 (1 bit)

FLUSHINV : Flush Event Invert Enable
bits : 2 - 2 (1 bit)

STARTINV : Start Conversion Event Invert Enable
bits : 3 - 3 (1 bit)

RESRDYEO : Result Ready Event Out
bits : 4 - 4 (1 bit)

WINMONEO : Window Monitor Event Out
bits : 5 - 5 (1 bit)


ADC_INTENCLR

Interrupt Enable Clear
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_INTENCLR ADC_INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESRDY OVERRUN WINMON

RESRDY : Result Ready Interrupt Disable
bits : 0 - 0 (1 bit)

OVERRUN : Overrun Interrupt Disable
bits : 1 - 1 (1 bit)

WINMON : Window Monitor Interrupt Disable
bits : 2 - 2 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x2C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESRDY OVERRUN WINMON

RESRDY : Result Ready Interrupt Disable
bits : 0 - 0 (1 bit)

OVERRUN : Overrun Interrupt Disable
bits : 1 - 1 (1 bit)

WINMON : Window Monitor Interrupt Disable
bits : 2 - 2 (1 bit)


ADC_INTENSET

Interrupt Enable Set
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_INTENSET ADC_INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESRDY OVERRUN WINMON

RESRDY : Result Ready Interrupt Enable
bits : 0 - 0 (1 bit)

OVERRUN : Overrun Interrupt Enable
bits : 1 - 1 (1 bit)

WINMON : Window Monitor Interrupt Enable
bits : 2 - 2 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x2D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESRDY OVERRUN WINMON

RESRDY : Result Ready Interrupt Enable
bits : 0 - 0 (1 bit)

OVERRUN : Overrun Interrupt Enable
bits : 1 - 1 (1 bit)

WINMON : Window Monitor Interrupt Enable
bits : 2 - 2 (1 bit)


ADC_INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_INTFLAG ADC_INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESRDY OVERRUN WINMON

RESRDY : Result Ready Interrupt Flag
bits : 0 - 0 (1 bit)

OVERRUN : Overrun Interrupt Flag
bits : 1 - 1 (1 bit)

WINMON : Window Monitor Interrupt Flag
bits : 2 - 2 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESRDY OVERRUN WINMON

RESRDY : Result Ready Interrupt Flag
bits : 0 - 0 (1 bit)

OVERRUN : Overrun Interrupt Flag
bits : 1 - 1 (1 bit)

WINMON : Window Monitor Interrupt Flag
bits : 2 - 2 (1 bit)


ADC_STATUS

Status
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_STATUS ADC_STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADCBUSY WCC

ADCBUSY : ADC Busy Status
bits : 0 - 0 (1 bit)

WCC : Window Comparator Counter
bits : 2 - 7 (6 bit)


STATUS

Status
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADCBUSY WCC

ADCBUSY : ADC Busy Status
bits : 0 - 0 (1 bit)

WCC : Window Comparator Counter
bits : 2 - 7 (6 bit)


ADC_DBGCTRL

Debug Control
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DBGCTRL ADC_DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run
bits : 0 - 0 (1 bit)


DBGCTRL

Debug Control
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run
bits : 0 - 0 (1 bit)


ADC_SYNCBUSY

Synchronization Busy
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_SYNCBUSY ADC_SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE INPUTCTRL CTRLB REFCTRL AVGCTRL SAMPCTRL WINLT WINUT GAINCORR OFFSETCORR SWTRIG

SWRST : SWRST Synchronization Busy
bits : 0 - 0 (1 bit)

ENABLE : ENABLE Synchronization Busy
bits : 1 - 1 (1 bit)

INPUTCTRL : Input Control Synchronization Busy
bits : 2 - 2 (1 bit)

CTRLB : Control B Synchronization Busy
bits : 3 - 3 (1 bit)

REFCTRL : Reference Control Synchronization Busy
bits : 4 - 4 (1 bit)

AVGCTRL : Average Control Synchronization Busy
bits : 5 - 5 (1 bit)

SAMPCTRL : Sampling Time Control Synchronization Busy
bits : 6 - 6 (1 bit)

WINLT : Window Monitor Lower Threshold Synchronization Busy
bits : 7 - 7 (1 bit)

WINUT : Window Monitor Upper Threshold Synchronization Busy
bits : 8 - 8 (1 bit)

GAINCORR : Gain Correction Synchronization Busy
bits : 9 - 9 (1 bit)

OFFSETCORR : Offset Correction Synchronization Busy
bits : 10 - 10 (1 bit)

SWTRIG : Software Trigger Synchronization Busy
bits : 11 - 11 (1 bit)


SYNCBUSY

Synchronization Busy
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE INPUTCTRL CTRLB REFCTRL AVGCTRL SAMPCTRL WINLT WINUT GAINCORR OFFSETCORR SWTRIG

SWRST : SWRST Synchronization Busy
bits : 0 - 0 (1 bit)

ENABLE : ENABLE Synchronization Busy
bits : 1 - 1 (1 bit)

INPUTCTRL : Input Control Synchronization Busy
bits : 2 - 2 (1 bit)

CTRLB : Control B Synchronization Busy
bits : 3 - 3 (1 bit)

REFCTRL : Reference Control Synchronization Busy
bits : 4 - 4 (1 bit)

AVGCTRL : Average Control Synchronization Busy
bits : 5 - 5 (1 bit)

SAMPCTRL : Sampling Time Control Synchronization Busy
bits : 6 - 6 (1 bit)

WINLT : Window Monitor Lower Threshold Synchronization Busy
bits : 7 - 7 (1 bit)

WINUT : Window Monitor Upper Threshold Synchronization Busy
bits : 8 - 8 (1 bit)

GAINCORR : Gain Correction Synchronization Busy
bits : 9 - 9 (1 bit)

OFFSETCORR : Offset Correction Synchronization Busy
bits : 10 - 10 (1 bit)

SWTRIG : Software Trigger Synchronization Busy
bits : 11 - 11 (1 bit)


ADC_DSEQDATA

DMA Sequencial Data
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DSEQDATA ADC_DSEQDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DMA Sequential Data
bits : 0 - 31 (32 bit)


DSEQDATA

DMA Sequencial Data
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DSEQDATA DSEQDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DMA Sequential Data
bits : 0 - 31 (32 bit)


ADC_DSEQCTRL

DMA Sequential Control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_DSEQCTRL ADC_DSEQCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPUTCTRL CTRLB REFCTRL AVGCTRL SAMPCTRL WINLT WINUT GAINCORR OFFSETCORR AUTOSTART

INPUTCTRL : Input Control
bits : 0 - 0 (1 bit)

CTRLB : Control B
bits : 1 - 1 (1 bit)

REFCTRL : Reference Control
bits : 2 - 2 (1 bit)

AVGCTRL : Average Control
bits : 3 - 3 (1 bit)

SAMPCTRL : Sampling Time Control
bits : 4 - 4 (1 bit)

WINLT : Window Monitor Lower Threshold
bits : 5 - 5 (1 bit)

WINUT : Window Monitor Upper Threshold
bits : 6 - 6 (1 bit)

GAINCORR : Gain Correction
bits : 7 - 7 (1 bit)

OFFSETCORR : Offset Correction
bits : 8 - 8 (1 bit)

AUTOSTART : ADC Auto-Start Conversion
bits : 31 - 31 (1 bit)


DSEQCTRL

DMA Sequential Control
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSEQCTRL DSEQCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPUTCTRL CTRLB REFCTRL AVGCTRL SAMPCTRL WINLT WINUT GAINCORR OFFSETCORR AUTOSTART

INPUTCTRL : Input Control
bits : 0 - 0 (1 bit)

CTRLB : Control B
bits : 1 - 1 (1 bit)

REFCTRL : Reference Control
bits : 2 - 2 (1 bit)

AVGCTRL : Average Control
bits : 3 - 3 (1 bit)

SAMPCTRL : Sampling Time Control
bits : 4 - 4 (1 bit)

WINLT : Window Monitor Lower Threshold
bits : 5 - 5 (1 bit)

WINUT : Window Monitor Upper Threshold
bits : 6 - 6 (1 bit)

GAINCORR : Gain Correction
bits : 7 - 7 (1 bit)

OFFSETCORR : Offset Correction
bits : 8 - 8 (1 bit)

AUTOSTART : ADC Auto-Start Conversion
bits : 31 - 31 (1 bit)


ADC_DSEQSTAT

DMA Sequencial Status
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_DSEQSTAT ADC_DSEQSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPUTCTRL CTRLB REFCTRL AVGCTRL SAMPCTRL WINLT WINUT GAINCORR OFFSETCORR BUSY

INPUTCTRL : Input Control
bits : 0 - 0 (1 bit)

CTRLB : Control B
bits : 1 - 1 (1 bit)

REFCTRL : Reference Control
bits : 2 - 2 (1 bit)

AVGCTRL : Average Control
bits : 3 - 3 (1 bit)

SAMPCTRL : Sampling Time Control
bits : 4 - 4 (1 bit)

WINLT : Window Monitor Lower Threshold
bits : 5 - 5 (1 bit)

WINUT : Window Monitor Upper Threshold
bits : 6 - 6 (1 bit)

GAINCORR : Gain Correction
bits : 7 - 7 (1 bit)

OFFSETCORR : Offset Correction
bits : 8 - 8 (1 bit)

BUSY : DMA Sequencing Busy
bits : 31 - 31 (1 bit)


DSEQSTAT

DMA Sequencial Status
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSEQSTAT DSEQSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPUTCTRL CTRLB REFCTRL AVGCTRL SAMPCTRL WINLT WINUT GAINCORR OFFSETCORR BUSY

INPUTCTRL : Input Control
bits : 0 - 0 (1 bit)

CTRLB : Control B
bits : 1 - 1 (1 bit)

REFCTRL : Reference Control
bits : 2 - 2 (1 bit)

AVGCTRL : Average Control
bits : 3 - 3 (1 bit)

SAMPCTRL : Sampling Time Control
bits : 4 - 4 (1 bit)

WINLT : Window Monitor Lower Threshold
bits : 5 - 5 (1 bit)

WINUT : Window Monitor Upper Threshold
bits : 6 - 6 (1 bit)

GAINCORR : Gain Correction
bits : 7 - 7 (1 bit)

OFFSETCORR : Offset Correction
bits : 8 - 8 (1 bit)

BUSY : DMA Sequencing Busy
bits : 31 - 31 (1 bit)


ADC_INPUTCTRL

Input Control
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_INPUTCTRL ADC_INPUTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUXPOS DIFFMODE MUXNEG DSEQSTOP

MUXPOS : Positive Mux Input Selection
bits : 0 - 4 (5 bit)

Enumeration: MUXPOSSelect

0 : AIN0

ADC AIN0 Pin

1 : AIN1

ADC AIN1 Pin

2 : AIN2

ADC AIN2 Pin

3 : AIN3

ADC AIN3 Pin

4 : AIN4

ADC AIN4 Pin

5 : AIN5

ADC AIN5 Pin

6 : AIN6

ADC AIN6 Pin

7 : AIN7

ADC AIN7 Pin

8 : AIN8

ADC AIN8 Pin

9 : AIN9

ADC AIN9 Pin

10 : AIN10

ADC AIN10 Pin

11 : AIN11

ADC AIN11 Pin

12 : AIN12

ADC AIN12 Pin

13 : AIN13

ADC AIN13 Pin

14 : AIN14

ADC AIN14 Pin

15 : AIN15

ADC AIN15 Pin

16 : AIN16

ADC AIN16 Pin

17 : AIN17

ADC AIN17 Pin

18 : AIN18

ADC AIN18 Pin

19 : AIN19

ADC AIN19 Pin

20 : AIN20

ADC AIN20 Pin

21 : AIN21

ADC AIN21 Pin

22 : AIN22

ADC AIN22 Pin

23 : AIN23

ADC AIN23 Pin

24 : SCALEDCOREVCC

1/4 Scaled Core Supply

25 : SCALEDVBAT

1/4 Scaled VBAT Supply

26 : SCALEDIOVCC

1/4 Scaled I/O Supply

27 : BANDGAP

Bandgap Voltage

28 : PTAT

Temperature Sensor

29 : CTAT

Temperature Sensor

30 : DAC

DAC Output

31 : PTC

PTC output (only on ADC0)

End of enumeration elements list.

DIFFMODE : Differential Mode
bits : 7 - 7 (1 bit)

MUXNEG : Negative Mux Input Selection
bits : 8 - 12 (5 bit)

Enumeration: MUXNEGSelect

0 : AIN0

ADC AIN0 Pin

1 : AIN1

ADC AIN1 Pin

2 : AIN2

ADC AIN2 Pin

3 : AIN3

ADC AIN3 Pin

4 : AIN4

ADC AIN4 Pin

5 : AIN5

ADC AIN5 Pin

6 : AIN6

ADC AIN6 Pin

7 : AIN7

ADC AIN7 Pin

24 : GND

Internal Ground

End of enumeration elements list.

DSEQSTOP : Stop DMA Sequencing
bits : 15 - 15 (1 bit)


INPUTCTRL

Input Control
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INPUTCTRL INPUTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUXPOS DIFFMODE MUXNEG DSEQSTOP

MUXPOS : Positive Mux Input Selection
bits : 0 - 4 (5 bit)

Enumeration: MUXPOSSelect

0x0 : AIN0

ADC AIN0 Pin

0x1 : AIN1

ADC AIN1 Pin

0x2 : AIN2

ADC AIN2 Pin

0x3 : AIN3

ADC AIN3 Pin

0x4 : AIN4

ADC AIN4 Pin

0x5 : AIN5

ADC AIN5 Pin

0x6 : AIN6

ADC AIN6 Pin

0x7 : AIN7

ADC AIN7 Pin

0x8 : AIN8

ADC AIN8 Pin

0x9 : AIN9

ADC AIN9 Pin

0xA : AIN10

ADC AIN10 Pin

0xB : AIN11

ADC AIN11 Pin

0xC : AIN12

ADC AIN12 Pin

0xD : AIN13

ADC AIN13 Pin

0xE : AIN14

ADC AIN14 Pin

0xF : AIN15

ADC AIN15 Pin

0x10 : AIN16

ADC AIN16 Pin

0x11 : AIN17

ADC AIN17 Pin

0x12 : AIN18

ADC AIN18 Pin

0x13 : AIN19

ADC AIN19 Pin

0x14 : AIN20

ADC AIN20 Pin

0x15 : AIN21

ADC AIN21 Pin

0x16 : AIN22

ADC AIN22 Pin

0x17 : AIN23

ADC AIN23 Pin

0x18 : SCALEDCOREVCC

1/4 Scaled Core Supply

0x19 : SCALEDVBAT

1/4 Scaled VBAT Supply

0x1A : SCALEDIOVCC

1/4 Scaled I/O Supply

0x1B : BANDGAP

Bandgap Voltage

0x1C : PTAT

Temperature Sensor TSENSP

0x1D : CTAT

Temperature Sensor TSENSC

0x1E : DAC

DAC Output

0x1F : PTC

PTC output (only on ADC0)

End of enumeration elements list.

DIFFMODE : Differential Mode
bits : 7 - 7 (1 bit)

MUXNEG : Negative Mux Input Selection
bits : 8 - 12 (5 bit)

Enumeration: MUXNEGSelect

0x0 : AIN0

ADC AIN0 Pin

0x1 : AIN1

ADC AIN1 Pin

0x2 : AIN2

ADC AIN2 Pin

0x3 : AIN3

ADC AIN3 Pin

0x4 : AIN4

ADC AIN4 Pin

0x5 : AIN5

ADC AIN5 Pin

0x6 : AIN6

ADC AIN6 Pin

0x7 : AIN7

ADC AIN7 Pin

0x18 : GND

Internal Ground

End of enumeration elements list.

DSEQSTOP : Stop DMA Sequencing
bits : 15 - 15 (1 bit)


ADC_RESULT

Result Conversion Value
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_RESULT ADC_RESULT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Result Conversion Value
bits : 0 - 15 (16 bit)


RESULT

Result Conversion Value
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESULT RESULT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Result Conversion Value
bits : 0 - 15 (16 bit)


ADC_RESS

Last Sample Result
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ADC_RESS ADC_RESS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESS

RESS : Last ADC conversion result
bits : 0 - 15 (16 bit)


RESS

Last Sample Result
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RESS RESS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESS

RESS : Last ADC conversion result
bits : 0 - 15 (16 bit)


ADC_CALIB

Calibration
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CALIB ADC_CALIB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIASCOMP BIASR2R BIASREFBUF

BIASCOMP : Bias Comparator Scaling
bits : 0 - 2 (3 bit)

BIASR2R : Bias R2R Ampli scaling
bits : 4 - 6 (3 bit)

BIASREFBUF : Bias Reference Buffer Scaling
bits : 8 - 10 (3 bit)


CALIB

Calibration
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALIB CALIB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIASCOMP BIASR2R BIASREFBUF

BIASCOMP : Bias Comparator Scaling
bits : 0 - 2 (3 bit)

BIASR2R : Bias R2R Ampli scaling
bits : 4 - 6 (3 bit)

BIASREFBUF : Bias Reference Buffer Scaling
bits : 8 - 10 (3 bit)


ADC_CTRLB

Control B
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_CTRLB ADC_CTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEFTADJ FREERUN CORREN RESSEL WINMODE WINSS

LEFTADJ : Left-Adjusted Result
bits : 0 - 0 (1 bit)

FREERUN : Free Running Mode
bits : 1 - 1 (1 bit)

CORREN : Digital Correction Logic Enable
bits : 2 - 2 (1 bit)

RESSEL : Conversion Result Resolution
bits : 3 - 4 (2 bit)

Enumeration: RESSELSelect

0 : 12BIT

12-bit result

1 : 16BIT

For averaging mode output

2 : 10BIT

10-bit result

3 : 8BIT

8-bit result

End of enumeration elements list.

WINMODE : Window Monitor Mode
bits : 8 - 10 (3 bit)

Enumeration: WINMODESelect

0 : DISABLE

No window mode (default)

1 : MODE1

RESULT > WINLT

2 : MODE2

RESULT < WINUT

3 : MODE3

WINLT < RESULT < WINUT

4 : MODE4

!(WINLT < RESULT < WINUT)

End of enumeration elements list.

WINSS : Window Single Sample
bits : 11 - 11 (1 bit)


CTRLB

Control B
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLB CTRLB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEFTADJ FREERUN CORREN RESSEL WINMODE WINSS

LEFTADJ : Left-Adjusted Result
bits : 0 - 0 (1 bit)

FREERUN : Free Running Mode
bits : 1 - 1 (1 bit)

CORREN : Digital Correction Logic Enable
bits : 2 - 2 (1 bit)

RESSEL : Conversion Result Resolution
bits : 3 - 4 (2 bit)

Enumeration: RESSELSelect

0x0 : 12BIT

12-bit result

0x1 : 16BIT

For averaging mode output

0x2 : 10BIT

10-bit result

0x3 : 8BIT

8-bit result

End of enumeration elements list.

WINMODE : Window Monitor Mode
bits : 8 - 10 (3 bit)

Enumeration: WINMODESelect

0 : DISABLE

No window mode (default)

1 : MODE1

RESULT > WINLT

2 : MODE2

RESULT < WINUT

3 : MODE3

WINLT < RESULT < WINUT

4 : MODE4

!(WINLT < RESULT < WINUT)

End of enumeration elements list.

WINSS : Window Single Sample
bits : 11 - 11 (1 bit)


ADC_REFCTRL

Reference Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_REFCTRL ADC_REFCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 REFSEL REFCOMP

REFSEL : Reference Selection
bits : 0 - 3 (4 bit)

Enumeration: REFSELSelect

0 : INTREF

Internal Bandgap Reference

2 : INTVCC0

1/2 VDDANA

3 : INTVCC1

VDDANA

4 : AREFA

External Reference

5 : AREFB

External Reference

6 : AREFC

External Reference (only on ADC1)

End of enumeration elements list.

REFCOMP : Reference Buffer Offset Compensation Enable
bits : 7 - 7 (1 bit)


REFCTRL

Reference Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFCTRL REFCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 REFSEL REFCOMP

REFSEL : Reference Selection
bits : 0 - 3 (4 bit)

Enumeration: REFSELSelect

0x0 : INTREF

Internal Bandgap Reference

0x2 : INTVCC0

1/2 VDDANA

0x3 : INTVCC1

VDDANA

0x4 : AREFA

External Reference A

0x5 : AREFB

External Reference B

0x6 : AREFC

External Reference C (only on ADC1)

End of enumeration elements list.

REFCOMP : Reference Buffer Offset Compensation Enable
bits : 7 - 7 (1 bit)


ADC_AVGCTRL

Average Control
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_AVGCTRL ADC_AVGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SAMPLENUM ADJRES

SAMPLENUM : Number of Samples to be Collected
bits : 0 - 3 (4 bit)

Enumeration: SAMPLENUMSelect

0 : 1

1 sample

1 : 2

2 samples

2 : 4

4 samples

3 : 8

8 samples

4 : 16

16 samples

5 : 32

32 samples

6 : 64

64 samples

7 : 128

128 samples

8 : 256

256 samples

9 : 512

512 samples

10 : 1024

1024 samples

End of enumeration elements list.

ADJRES : Adjusting Result / Division Coefficient
bits : 4 - 6 (3 bit)


AVGCTRL

Average Control
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AVGCTRL AVGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SAMPLENUM ADJRES

SAMPLENUM : Number of Samples to be Collected
bits : 0 - 3 (4 bit)

Enumeration: SAMPLENUMSelect

0x0 : 1

1 sample

0x1 : 2

2 samples

0x2 : 4

4 samples

0x3 : 8

8 samples

0x4 : 16

16 samples

0x5 : 32

32 samples

0x6 : 64

64 samples

0x7 : 128

128 samples

0x8 : 256

256 samples

0x9 : 512

512 samples

0xA : 1024

1024 samples

End of enumeration elements list.

ADJRES : Adjusting Result / Division Coefficient
bits : 4 - 6 (3 bit)


ADC_SAMPCTRL

Sample Time Control
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_SAMPCTRL ADC_SAMPCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SAMPLEN OFFCOMP

SAMPLEN : Sampling Time Length
bits : 0 - 5 (6 bit)

OFFCOMP : Comparator Offset Compensation Enable
bits : 7 - 7 (1 bit)


SAMPCTRL

Sample Time Control
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAMPCTRL SAMPCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SAMPLEN OFFCOMP

SAMPLEN : Sampling Time Length
bits : 0 - 5 (6 bit)

OFFCOMP : Comparator Offset Compensation Enable
bits : 7 - 7 (1 bit)


ADC_WINLT

Window Monitor Lower Threshold
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_WINLT ADC_WINLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINLT

WINLT : Window Lower Threshold
bits : 0 - 15 (16 bit)


WINLT

Window Monitor Lower Threshold
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WINLT WINLT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINLT

WINLT : Window Lower Threshold
bits : 0 - 15 (16 bit)


ADC_WINUT

Window Monitor Upper Threshold
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADC_WINUT ADC_WINUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINUT

WINUT : Window Upper Threshold
bits : 0 - 15 (16 bit)


WINUT

Window Monitor Upper Threshold
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WINUT WINUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WINUT

WINUT : Window Upper Threshold
bits : 0 - 15 (16 bit)



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