\n
address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCCNTENA :
bits : 0 - 0 (1 bit)
POSTPRESET :
bits : 1 - 4 (4 bit)
POSTINIT :
bits : 5 - 8 (4 bit)
CYCTAP :
bits : 9 - 9 (1 bit)
SYNCTAP :
bits : 10 - 11 (2 bit)
PCSAMPLENA :
bits : 12 - 12 (1 bit)
EXCTRCENA :
bits : 16 - 16 (1 bit)
CPIEVTENA :
bits : 17 - 17 (1 bit)
EXCEVTENA :
bits : 18 - 18 (1 bit)
SLEEPEVTENA :
bits : 19 - 19 (1 bit)
LSUEVTENA :
bits : 20 - 20 (1 bit)
FOLDEVTENA :
bits : 21 - 21 (1 bit)
CYCEVTENA :
bits : 22 - 22 (1 bit)
NOPRFCNT :
bits : 24 - 24 (1 bit)
NOCYCCNT :
bits : 25 - 25 (1 bit)
NOEXTTRIG :
bits : 26 - 26 (1 bit)
NOTRCPKT :
bits : 27 - 27 (1 bit)
NUMCOMP :
bits : 28 - 31 (4 bit)
Sleep Count Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPCNT :
bits : 0 - 7 (8 bit)
LSU Count Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSUCNT :
bits : 0 - 7 (8 bit)
Folded-instruction Count Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FOLDCNT :
bits : 0 - 7 (8 bit)
Program Counter Sample Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Comparator Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask Register 0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK :
bits : 0 - 4 (5 bit)
Function Register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNCTION :
bits : 0 - 3 (4 bit)
EMITRANGE :
bits : 5 - 5 (1 bit)
CYCMATCH :
bits : 7 - 7 (1 bit)
DATAVMATCH :
bits : 8 - 8 (1 bit)
LNK1ENA :
bits : 9 - 9 (1 bit)
DATAVSIZE :
bits : 10 - 11 (2 bit)
DATAVADDR0 :
bits : 12 - 15 (4 bit)
DATAVADDR1 :
bits : 16 - 19 (4 bit)
MATCHED :
bits : 24 - 24 (1 bit)
Comparator Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK :
bits : 0 - 4 (5 bit)
Function Register 1
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNCTION :
bits : 0 - 3 (4 bit)
EMITRANGE :
bits : 5 - 5 (1 bit)
CYCMATCH :
bits : 7 - 7 (1 bit)
DATAVMATCH :
bits : 8 - 8 (1 bit)
LNK1ENA :
bits : 9 - 9 (1 bit)
DATAVSIZE :
bits : 10 - 11 (2 bit)
DATAVADDR0 :
bits : 12 - 15 (4 bit)
DATAVADDR1 :
bits : 16 - 19 (4 bit)
MATCHED :
bits : 24 - 24 (1 bit)
Cycle Count Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Comparator Register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask Register 2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK :
bits : 0 - 4 (5 bit)
Function Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNCTION :
bits : 0 - 3 (4 bit)
EMITRANGE :
bits : 5 - 5 (1 bit)
CYCMATCH :
bits : 7 - 7 (1 bit)
DATAVMATCH :
bits : 8 - 8 (1 bit)
LNK1ENA :
bits : 9 - 9 (1 bit)
DATAVSIZE :
bits : 10 - 11 (2 bit)
DATAVADDR0 :
bits : 12 - 15 (4 bit)
DATAVADDR1 :
bits : 16 - 19 (4 bit)
MATCHED :
bits : 24 - 24 (1 bit)
Comparator Register 3
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Mask Register 3
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK :
bits : 0 - 4 (5 bit)
Function Register 3
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNCTION :
bits : 0 - 3 (4 bit)
EMITRANGE :
bits : 5 - 5 (1 bit)
CYCMATCH :
bits : 7 - 7 (1 bit)
DATAVMATCH :
bits : 8 - 8 (1 bit)
LNK1ENA :
bits : 9 - 9 (1 bit)
DATAVSIZE :
bits : 10 - 11 (2 bit)
DATAVADDR0 :
bits : 12 - 15 (4 bit)
DATAVADDR1 :
bits : 16 - 19 (4 bit)
MATCHED :
bits : 24 - 24 (1 bit)
CPI Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPICNT :
bits : 0 - 7 (8 bit)
Exception Overhead Count Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXCCNT :
bits : 0 - 7 (8 bit)
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