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MPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected

Registers

TYPE

RASR

RBAR_A1

RASR_A1

RBAR_A2

RASR_A2

RBAR_A3

RASR_A3

CTRL

RNR

RBAR


TYPE

MPU Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TYPE TYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEPARATE DREGION IREGION

SEPARATE : Separate instruction and Data Memory MapsRegions
bits : 0 - 0 (1 bit)

DREGION : Number of Data Regions
bits : 8 - 15 (8 bit)

IREGION : Number of Instruction Regions
bits : 16 - 23 (8 bit)


RASR

MPU Region Attribute and Size Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RASR RASR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region Enable
bits : 0 - 0 (1 bit)

SIZE : Region Size
bits : 1 - 1 (1 bit)

SRD : Sub-region disable
bits : 8 - 15 (8 bit)

B : Bufferable bit
bits : 16 - 16 (1 bit)

C : Cacheable bit
bits : 17 - 17 (1 bit)

S : Shareable bit
bits : 18 - 18 (1 bit)

TEX : TEX bit
bits : 19 - 21 (3 bit)

AP : Access Permission
bits : 24 - 26 (3 bit)

XN : Execute Never Attribute
bits : 28 - 28 (1 bit)


RBAR_A1

MPU Alias 1 Region Base Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBAR_A1 RBAR_A1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : Region number
bits : 0 - 3 (4 bit)

VALID : Region number valid
bits : 4 - 4 (1 bit)

ADDR : Region base address
bits : 5 - 31 (27 bit)


RASR_A1

MPU Alias 1 Region Attribute and Size Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RASR_A1 RASR_A1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region Enable
bits : 0 - 0 (1 bit)

SIZE : Region Size
bits : 1 - 1 (1 bit)

SRD : Sub-region disable
bits : 8 - 15 (8 bit)

B : Bufferable bit
bits : 16 - 16 (1 bit)

C : Cacheable bit
bits : 17 - 17 (1 bit)

S : Shareable bit
bits : 18 - 18 (1 bit)

TEX : TEX bit
bits : 19 - 21 (3 bit)

AP : Access Permission
bits : 24 - 26 (3 bit)

XN : Execute Never Attribute
bits : 28 - 28 (1 bit)


RBAR_A2

MPU Alias 2 Region Base Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBAR_A2 RBAR_A2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : Region number
bits : 0 - 3 (4 bit)

VALID : Region number valid
bits : 4 - 4 (1 bit)

ADDR : Region base address
bits : 5 - 31 (27 bit)


RASR_A2

MPU Alias 2 Region Attribute and Size Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RASR_A2 RASR_A2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region Enable
bits : 0 - 0 (1 bit)

SIZE : Region Size
bits : 1 - 1 (1 bit)

SRD : Sub-region disable
bits : 8 - 15 (8 bit)

B : Bufferable bit
bits : 16 - 16 (1 bit)

C : Cacheable bit
bits : 17 - 17 (1 bit)

S : Shareable bit
bits : 18 - 18 (1 bit)

TEX : TEX bit
bits : 19 - 21 (3 bit)

AP : Access Permission
bits : 24 - 26 (3 bit)

XN : Execute Never Attribute
bits : 28 - 28 (1 bit)


RBAR_A3

MPU Alias 3 Region Base Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBAR_A3 RBAR_A3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : Region number
bits : 0 - 3 (4 bit)

VALID : Region number valid
bits : 4 - 4 (1 bit)

ADDR : Region base address
bits : 5 - 31 (27 bit)


RASR_A3

MPU Alias 3 Region Attribute and Size Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RASR_A3 RASR_A3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region Enable
bits : 0 - 0 (1 bit)

SIZE : Region Size
bits : 1 - 1 (1 bit)

SRD : Sub-region disable
bits : 8 - 15 (8 bit)

B : Bufferable bit
bits : 16 - 16 (1 bit)

C : Cacheable bit
bits : 17 - 17 (1 bit)

S : Shareable bit
bits : 18 - 18 (1 bit)

TEX : TEX bit
bits : 19 - 21 (3 bit)

AP : Access Permission
bits : 24 - 26 (3 bit)

XN : Execute Never Attribute
bits : 28 - 28 (1 bit)


CTRL

MPU Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE HFNMIENA PRIVDEFENA

ENABLE : MPU Enable
bits : 0 - 0 (1 bit)

HFNMIENA : Enable Hard Fault and NMI handlers
bits : 1 - 1 (1 bit)

PRIVDEFENA : Enables privileged software access to default memory map
bits : 2 - 2 (1 bit)


RNR

MPU Region Number Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNR RNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION

REGION : Region referenced by RBAR and RASR
bits : 0 - 7 (8 bit)


RBAR

MPU Region Base Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RBAR RBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : Region number
bits : 0 - 3 (4 bit)

VALID : Region number valid
bits : 4 - 4 (1 bit)

ADDR : Region base address
bits : 5 - 31 (27 bit)



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