\n

RAMECC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INTENCLR

INTENSET

INTFLAG

STATUS

ERRADDR

DBGCTRL


INTENCLR

Interrupt Enable Clear
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SINGLEE DUALE

SINGLEE : Single Bit ECC Error Interrupt Enable Clear
bits : 0 - 0 (1 bit)

DUALE : Dual Bit ECC Error Interrupt Enable Clear
bits : 1 - 1 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SINGLEE DUALE

SINGLEE : Single Bit ECC Error Interrupt Enable Set
bits : 0 - 0 (1 bit)

DUALE : Dual Bit ECC Error Interrupt Enable Set
bits : 1 - 1 (1 bit)


INTFLAG

Interrupt Flag
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SINGLEE DUALE

SINGLEE : Single Bit ECC Error Interrupt
bits : 0 - 0 (1 bit)

DUALE : Dual Bit ECC Error Interrupt
bits : 1 - 1 (1 bit)


STATUS

Status
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ECCDIS

ECCDIS : ECC Disable
bits : 0 - 0 (1 bit)


ERRADDR

Error Address
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERRADDR ERRADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRADDR

ERRADDR : Error Address
bits : 0 - 16 (17 bit)


DBGCTRL

Debug Control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ECCDIS ECCELOG

ECCDIS : ECC Disable
bits : 0 - 0 (1 bit)

ECCELOG : ECC Error Log
bits : 1 - 1 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.