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FPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MVFR0

MVFR1

FPCCR

FPCAR

FPDSCR


MVFR0

Media and FP Feature Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MVFR0 MVFR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A_SIMD_registers Single_precision Double_precision FP_excep_trapping Divide Square_root Short_vectors FP_rounding_modes

A_SIMD_registers :
bits : 0 - 3 (4 bit)

Single_precision :
bits : 4 - 7 (4 bit)

Double_precision :
bits : 8 - 11 (4 bit)

FP_excep_trapping :
bits : 12 - 15 (4 bit)

Divide :
bits : 16 - 19 (4 bit)

Square_root :
bits : 20 - 23 (4 bit)

Short_vectors :
bits : 24 - 27 (4 bit)

FP_rounding_modes :
bits : 28 - 31 (4 bit)


MVFR1

Media and FP Feature Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MVFR1 MVFR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FtZ_mode D_NaN_mode FP_HPFP FP_fused_MAC

FtZ_mode :
bits : 0 - 3 (4 bit)

D_NaN_mode :
bits : 4 - 7 (4 bit)

FP_HPFP :
bits : 24 - 27 (4 bit)

FP_fused_MAC :
bits : 28 - 31 (4 bit)


FPCCR

Floating-Point Context Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCCR FPCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSPACT USER THREAD HFRDY MMRDY BFRDY MONRDY LSPEN ASPEN

LSPACT :
bits : 0 - 0 (1 bit)

USER :
bits : 1 - 1 (1 bit)

THREAD :
bits : 3 - 3 (1 bit)

HFRDY :
bits : 4 - 4 (1 bit)

MMRDY :
bits : 5 - 5 (1 bit)

BFRDY :
bits : 6 - 6 (1 bit)

MONRDY :
bits : 8 - 8 (1 bit)

LSPEN :
bits : 30 - 30 (1 bit)

ASPEN :
bits : 31 - 31 (1 bit)


FPCAR

Floating-Point Context Address Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCAR FPCAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Address for FP registers in exception stack frame
bits : 3 - 31 (29 bit)


FPDSCR

Floating-Point Default Status Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPDSCR FPDSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMODE FZ DN AHP

RMODE : Default value for FPSCR.RMODE
bits : 22 - 23 (2 bit)

Enumeration: RMODESelect

0 : RN

Round to Nearest

1 : RP

Round towards Positive Infinity

2 : RM

Round towards Negative Infinity

3 : RZ

Round towards Zero

End of enumeration elements list.

FZ : Default value for FPSCR.FZ
bits : 24 - 24 (1 bit)

DN : Default value for FPSCR.DN
bits : 25 - 25 (1 bit)

AHP : Default value for FPSCR.AHP
bits : 26 - 26 (1 bit)



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