\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Debug Halting Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C_DEBUGEN :
bits : 0 - 0 (1 bit)
C_HALT :
bits : 1 - 1 (1 bit)
C_STEP :
bits : 2 - 2 (1 bit)
C_MASKINTS :
bits : 3 - 3 (1 bit)
C_SNAPSTALL :
bits : 5 - 5 (1 bit)
S_REGRDY :
bits : 16 - 16 (1 bit)
access : read-only
DBGKEY :
bits : 16 - 31 (16 bit)
access : write-only
S_HALT :
bits : 17 - 17 (1 bit)
access : read-only
S_SLEEP :
bits : 18 - 18 (1 bit)
access : read-only
S_LOCKUP :
bits : 19 - 19 (1 bit)
access : read-only
S_RETIRE_ST :
bits : 24 - 24 (1 bit)
access : read-only
S_RESET_ST :
bits : 25 - 25 (1 bit)
access : read-only
Debug Core Register Selector Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
REGSEL :
bits : 0 - 4 (5 bit)
REGWnR :
bits : 16 - 16 (1 bit)
Debug Core Register Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Debug Exception and Monitor Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VC_CORERESET :
bits : 0 - 0 (1 bit)
VC_MMERR :
bits : 4 - 4 (1 bit)
VC_NOCPERR :
bits : 5 - 5 (1 bit)
VC_CHKERR :
bits : 6 - 6 (1 bit)
VC_STATERR :
bits : 7 - 7 (1 bit)
VC_BUSERR :
bits : 8 - 8 (1 bit)
VC_INTERR :
bits : 9 - 9 (1 bit)
VC_HARDERR :
bits : 10 - 10 (1 bit)
MON_EN :
bits : 16 - 16 (1 bit)
MON_PEND :
bits : 17 - 17 (1 bit)
MON_STEP :
bits : 18 - 18 (1 bit)
MON_REQ :
bits : 19 - 19 (1 bit)
TRCENA :
bits : 24 - 24 (1 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.