\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
Control A
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOWS : Auto Wait State Enable
bits : 2 - 2 (1 bit)
SUSPEN : Suspend Enable
bits : 3 - 3 (1 bit)
WMODE : Write Mode
bits : 4 - 5 (2 bit)
Enumeration: WMODESelect
0 : MAN
Manual Write
1 : ADW
Automatic Double Word Write
2 : AQW
Automatic Quad Word
3 : AP
Automatic Page Write
End of enumeration elements list.
PRM : Power Reduction Mode during Sleep
bits : 6 - 7 (2 bit)
Enumeration: PRMSelect
0 : SEMIAUTO
NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access.
1 : FULLAUTO
NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode.
3 : MANUAL
NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access.
End of enumeration elements list.
RWS : NVM Read Wait States
bits : 8 - 11 (4 bit)
AHBNS0 : Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated
bits : 12 - 12 (1 bit)
AHBNS1 : Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated
bits : 13 - 13 (1 bit)
CACHEDIS0 : AHB0 Cache Disable
bits : 14 - 14 (1 bit)
CACHEDIS1 : AHB1 Cache Disable
bits : 15 - 15 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : Command Done
bits : 0 - 0 (1 bit)
ADDRE : Address Error
bits : 1 - 1 (1 bit)
PROGE : Programming Error
bits : 2 - 2 (1 bit)
LOCKE : Lock Error
bits : 3 - 3 (1 bit)
ECCSE : ECC Single Error
bits : 4 - 4 (1 bit)
ECCDE : ECC Dual Error
bits : 5 - 5 (1 bit)
NVME : NVM Error
bits : 6 - 6 (1 bit)
SUSP : Suspended Write Or Erase Operation
bits : 7 - 7 (1 bit)
SEESFULL : Active SEES Full
bits : 8 - 8 (1 bit)
SEESOVF : Active SEES Overflow
bits : 9 - 9 (1 bit)
SEEWRC : SEE Write Completed
bits : 10 - 10 (1 bit)
Status
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READY : Ready to accept a command
bits : 0 - 0 (1 bit)
PRM : Power Reduction Mode
bits : 1 - 1 (1 bit)
LOAD : NVM Page Buffer Active Loading
bits : 2 - 2 (1 bit)
SUSP : NVM Write Or Erase Operation Is Suspended
bits : 3 - 3 (1 bit)
AFIRST : BANKA First
bits : 4 - 4 (1 bit)
BPDIS : Boot Loader Protection Disable
bits : 5 - 5 (1 bit)
BOOTPROT : Boot Loader Protection Size
bits : 8 - 11 (4 bit)
Enumeration: BOOTPROTSelect
15 : 0
0 kbytes
14 : 8
8 kbytes
13 : 16
16 kbytes
12 : 24
24 kbytes
11 : 32
32 kbytes
10 : 40
40 kbytes
9 : 48
48 kbytes
8 : 56
56 kbytes
7 : 64
64 kbytes
6 : 72
72 kbytes
5 : 80
80 kbytes
4 : 88
88 kbytes
3 : 96
96 kbytes
2 : 104
104 kbytes
1 : 112
112 kbytes
0 : 120
120 kbytes
End of enumeration elements list.
Address
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : NVM Address
bits : 0 - 23 (24 bit)
Lock Section
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUNLOCK : Region Un-Lock Bits
bits : 0 - 31 (32 bit)
Page Buffer Load Data x
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Page Buffer Data
bits : 0 - 31 (32 bit)
Page Buffer Load Data x
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Page Buffer Data
bits : 0 - 31 (32 bit)
ECC Error Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Error Address
bits : 0 - 23 (24 bit)
TYPEL : Low Double-Word Error Type
bits : 28 - 29 (2 bit)
Enumeration: TYPELSelect
0 : None
No Error Detected Since Last Read
1 : Single
At Least One Single Error Detected Since last Read
2 : Dual
At Least One Dual Error Detected Since Last Read
End of enumeration elements list.
TYPEH : High Double-Word Error Type
bits : 30 - 31 (2 bit)
Enumeration: TYPEHSelect
0 : None
No Error Detected Since Last Read
1 : Single
At Least One Single Error Detected Since last Read
2 : Dual
At Least One Dual Error Detected Since Last Read
End of enumeration elements list.
Debug Control
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECCDIS : Debugger ECC Read Disable
bits : 0 - 0 (1 bit)
ECCELOG : Debugger ECC Error Tracking Mode
bits : 1 - 1 (1 bit)
SmartEEPROM Configuration Register
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WMODE : Write Mode
bits : 0 - 0 (1 bit)
Enumeration: WMODESelect
0 : UNBUFFERED
A NVM write command is issued after each write in the pagebuffer
1 : BUFFERED
A NVM write command is issued when a write to a new page is requested
End of enumeration elements list.
APRDIS : Automatic Page Reallocation Disable
bits : 1 - 1 (1 bit)
SmartEEPROM Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ASEES : Active SmartEEPROM Sector
bits : 0 - 0 (1 bit)
LOAD : Page Buffer Loaded
bits : 1 - 1 (1 bit)
BUSY : Busy
bits : 2 - 2 (1 bit)
LOCK : SmartEEPROM Write Access Is Locked
bits : 3 - 3 (1 bit)
RLOCK : SmartEEPROM Write Access To Register Address Space Is Locked
bits : 4 - 4 (1 bit)
SBLK : Blocks Number In a Sector
bits : 8 - 11 (4 bit)
PSZ : SmartEEPROM Page Size
bits : 16 - 18 (3 bit)
Page Buffer Load Data x
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Page Buffer Data
bits : 0 - 31 (32 bit)
Control B
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CMD : Command
bits : 0 - 6 (7 bit)
Enumeration: CMDSelect
0 : EP
Erase Page - Only supported in the USER and AUX pages.
1 : EB
Erase Block - Erases the block addressed by the ADDR register, not supported in the user page
3 : WP
Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page
4 : WQW
Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register.
16 : SWRST
Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers
17 : LR
Lock Region - Locks the region containing the address location in the ADDR register.
18 : UR
Unlock Region - Unlocks the region containing the address location in the ADDR register.
19 : SPRM
Sets the power reduction mode.
20 : CPRM
Clears the power reduction mode.
21 : PBC
Page Buffer Clear - Clears the page buffer.
22 : SSB
Set Security Bit
23 : BKSWRST
Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK
24 : CELCK
Chip Erase Lock - DSU.CE command is not available
25 : CEULCK
Chip Erase Unlock - DSU.CE command is available
26 : SBPDIS
Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence
27 : CBPDIS
Clears STATUS.BPDIS, Boot loader protection is not discarded
48 : ASEES0
Activate SmartEEPROM Sector 0, deactivate Sector 1
49 : ASEES1
Activate SmartEEPROM Sector 1, deactivate Sector 0
50 : SEERALOC
Starts SmartEEPROM sector reallocation algorithm
51 : SEEFLUSH
Flush SMEE data when in buffered mode
52 : LSEE
Lock access to SmartEEPROM data from any mean
53 : USEE
Unlock access to SmartEEPROM data
54 : LSEER
Lock access to the SmartEEPROM Register Address Space (above 64KB)
55 : USEER
Unlock access to the SmartEEPROM Register Address Space (above 64KB)
End of enumeration elements list.
CMDEX : Command Execution
bits : 8 - 15 (8 bit)
Enumeration: CMDEXSelect
165 : KEY
Execution Key
End of enumeration elements list.
Page Buffer Load Data x
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Page Buffer Data
bits : 0 - 31 (32 bit)
NVM Parameter
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NVMP : NVM Pages
bits : 0 - 15 (16 bit)
PSZ : Page Size
bits : 16 - 18 (3 bit)
Enumeration: PSZSelect
0 : 8
8 bytes
1 : 16
16 bytes
2 : 32
32 bytes
3 : 64
64 bytes
4 : 128
128 bytes
5 : 256
256 bytes
6 : 512
512 bytes
7 : 1024
1024 bytes
End of enumeration elements list.
SEE : SmartEEPROM Supported
bits : 31 - 31 (1 bit)
Enumeration: SEESelect
10 : A
163840 bytes
9 : 9
147456 bytes
8 : 8
131072 bytes
7 : 7
114688 bytes
6 : 6
98304 bytes
5 : 5
81920 bytes
4 : 4
65536 bytes
3 : 3
49152 bytes
2 : 2
32768 bytes
1 : 1
16384 bytes
0 : 0
0 bytes
End of enumeration elements list.
Interrupt Enable Clear
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : Command Done Interrupt Clear
bits : 0 - 0 (1 bit)
ADDRE : Address Error
bits : 1 - 1 (1 bit)
PROGE : Programming Error Interrupt Clear
bits : 2 - 2 (1 bit)
LOCKE : Lock Error Interrupt Clear
bits : 3 - 3 (1 bit)
ECCSE : ECC Single Error Interrupt Clear
bits : 4 - 4 (1 bit)
ECCDE : ECC Dual Error Interrupt Clear
bits : 5 - 5 (1 bit)
NVME : NVM Error Interrupt Clear
bits : 6 - 6 (1 bit)
SUSP : Suspended Write Or Erase Interrupt Clear
bits : 7 - 7 (1 bit)
SEESFULL : Active SEES Full Interrupt Clear
bits : 8 - 8 (1 bit)
SEESOVF : Active SEES Overflow Interrupt Clear
bits : 9 - 9 (1 bit)
SEEWRC : SEE Write Completed Interrupt Clear
bits : 10 - 10 (1 bit)
Interrupt Enable Set
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : Command Done Interrupt Enable
bits : 0 - 0 (1 bit)
ADDRE : Address Error Interrupt Enable
bits : 1 - 1 (1 bit)
PROGE : Programming Error Interrupt Enable
bits : 2 - 2 (1 bit)
LOCKE : Lock Error Interrupt Enable
bits : 3 - 3 (1 bit)
ECCSE : ECC Single Error Interrupt Enable
bits : 4 - 4 (1 bit)
ECCDE : ECC Dual Error Interrupt Enable
bits : 5 - 5 (1 bit)
NVME : NVM Error Interrupt Enable
bits : 6 - 6 (1 bit)
SUSP : Suspended Write Or Erase Interrupt Enable
bits : 7 - 7 (1 bit)
SEESFULL : Active SEES Full Interrupt Enable
bits : 8 - 8 (1 bit)
SEESOVF : Active SEES Overflow Interrupt Enable
bits : 9 - 9 (1 bit)
SEEWRC : SEE Write Completed Interrupt Enable
bits : 10 - 10 (1 bit)
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