Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected
PR[1]-MATRIX_PR[0]-MATRIX_PRAS
PR[1]-MATRIX_PR[0]-MATRIX_PRBS
PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS
PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS
PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS
PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS
PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS
PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS
PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS
PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS
PR[6]-MATRIX_PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS
PR[6]-MATRIX_PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS
Master Configuration Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Configuration Register 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Configuration Register 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Remap Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCB0 : Remap Command Bit for Master 0
bits : 0 - 0 (1 bit)
RCB1 : Remap Command Bit for Master 1
bits : 1 - 1 (1 bit)
RCB2 : Remap Command Bit for Master 2
bits : 2 - 2 (1 bit)
RCB3 : Remap Command Bit for Master 3
bits : 3 - 3 (1 bit)
RCB4 : Remap Command Bit for Master 4
bits : 4 - 4 (1 bit)
RCB5 : Remap Command Bit for Master 5
bits : 5 - 5 (1 bit)
RCB6 : Remap Command Bit for Master 6
bits : 6 - 6 (1 bit)
RCB8 : Remap Command Bit for Master 8
bits : 8 - 8 (1 bit)
RCB9 : Remap Command Bit for Master 9
bits : 9 - 9 (1 bit)
RCB10 : Remap Command Bit for Master 10
bits : 10 - 10 (1 bit)
RCB11 : Remap Command Bit for Master 11
bits : 11 - 11 (1 bit)
Master Configuration Register 0
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Priority Register A for Slave 0
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Slave Configuration Register 0
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Priority Register B for Slave 0
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
CAN0 Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAN0DMABA : CAN0 DMA Base Address
bits : 16 - 31 (16 bit)
System I/O Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSIO4 : PB4 or TDI Assignment
bits : 4 - 4 (1 bit)
SYSIO5 : PB5 or TDO/TRACESWO Assignment
bits : 5 - 5 (1 bit)
SYSIO6 : PB6 or TMS/SWDIO Assignment
bits : 6 - 6 (1 bit)
SYSIO7 : PB7 or TCK/SWCLK Assignment
bits : 7 - 7 (1 bit)
SYSIO12 : PB12 or ERASE Assignment
bits : 12 - 12 (1 bit)
SMC NAND Flash Chip Select Configuration Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMC_NFCS0 : SMC NAND Flash Chip Select 0 Assignment
bits : 0 - 0 (1 bit)
SMC_NFCS1 : SMC NAND Flash Chip Select 1 Assignment
bits : 1 - 1 (1 bit)
SMC_NFCS2 : SMC NAND Flash Chip Select 2 Assignment
bits : 2 - 2 (1 bit)
SMC_NFCS3 : SMC NAND Flash Chip Select 3 Assignment
bits : 3 - 3 (1 bit)
SDRAMEN : SDRAM Enable
bits : 4 - 4 (1 bit)
Master Configuration Register 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Slave Configuration Register 0
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Master Configuration Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Configuration Register 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Priority Register A for Slave 0
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Priority Register B for Slave 0
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
Slave Configuration Register 0
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Write Protection Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
5062996 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
Slave Configuration Register 0
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Master Configuration Register 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Priority Register A for Slave 0
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Priority Register B for Slave 0
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
Master Configuration Register 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Slave Configuration Register 0
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Master Configuration Register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Configuration Register 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Slave Configuration Register 0
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Master Configuration Register 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Priority Register A for Slave 0
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Priority Register B for Slave 0
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
Slave Configuration Register 0
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Priority Register A for Slave 0
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Priority Register B for Slave 0
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
Master Configuration Register 0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Configuration Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Configuration Register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Priority Register A for Slave 0
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Priority Register B for Slave 0
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
Slave Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Priority Register A for Slave 0
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Priority Register B for Slave 0
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
Slave Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register 0
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Slave Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Priority Register A for Slave 0
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Priority Register B for Slave 0
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
Slave Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
0x1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
0x2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Configuration Register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Slave Configuration Register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Priority Register A for Slave 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
Priority Register A for Slave 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Priority Register B for Slave 0
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
Priority Register B for Slave 0
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Priority Register B for Slave 1
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master Configuration Register 0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Priority Register A for Slave 2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Priority Register B for Slave 2
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Priority Register B for Slave 3
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Priority Register B for Slave 4
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 5
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Priority Register B for Slave 5
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 6
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Master Configuration Register 0
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Priority Register B for Slave 6
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Priority Register A for Slave 7
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Priority Register B for Slave 7
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master Configuration Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Master Configuration Register 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
0x1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
0x2 : 4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
0x3 : 8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
0x4 : 16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
0x5 : 32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
0x6 : 64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
0x7 : 128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Priority Register A for Slave 8
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
Slave Configuration Register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
Enumeration: DEFMSTR_TYPESelect
0 : NONE
No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1 : LAST
Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again.
2 : FIXED
Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again.
End of enumeration elements list.
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
Priority Register B for Slave 8
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
M8PR : Master 8 Priority
bits : 0 - 1 (2 bit)
access : read-write
M9PR : Master 9 Priority
bits : 4 - 5 (2 bit)
access : read-write
M10PR : Master 10 Priority
bits : 8 - 9 (2 bit)
access : read-write
M11PR : Master 11 Priority
bits : 12 - 13 (2 bit)
access : read-write
Master Configuration Register 0
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
Enumeration: ULBTSelect
0 : UNLTD_LENGTH
Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave.
1 : SINGLE_ACCESS
Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence.
2 : _4BEAT_BURST
4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats.
3 : _8BEAT_BURST
8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats.
4 : _16BEAT_BURST
16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats.
5 : _32BEAT_BURST
32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats.
6 : _64BEAT_BURST
64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats.
7 : _128BEAT_BURST
128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.