Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFC byte (0x0)
mem_usage : registers
protection : not protected
Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBCK : Loop Back Mode (read/write)
bits : 4 - 4 (1 bit)
Enumeration: LBCKSelect
0 : DISABLED
Reset value. Loop Back mode is disabled.
1 : ENABLED
Loop Back mode is enabled (see Section 1.5.1.9).
End of enumeration elements list.
TX : Control of Transmit Pin (read/write)
bits : 5 - 6 (2 bit)
Enumeration: TXSelect
0 : RESET
Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time.
1 : SAMPLE_POINT_MONITORING
Sample Point can be monitored at pin CANTX.
2 : DOMINANT
Dominant ('0') level at pin CANTX.
3 : RECESSIVE
Recessive ('1') at pin CANTX.
End of enumeration elements list.
RX : Receive Pin (read-only)
bits : 7 - 7 (1 bit)
TDCV : Transceiver Delay Compensation Value (read-only)
bits : 8 - 13 (6 bit)
Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
LBCK : Loop Back Mode (read/write)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Reset value. Loop Back mode is disabled.
1 : ENABLED
Loop Back mode is enabled (see Section 1.5.1.9).
End of enumeration elements list.
TX : Control of Transmit Pin (read/write)
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0x0 : RESET
Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time.
0x1 : SAMPLE_POINT_MONITORING
Sample Point can be monitored at pin CANTX.
0x2 : DOMINANT
Dominant ('0') level at pin CANTX.
0x3 : RECESSIVE
Recessive ('1') at pin CANTX.
End of enumeration elements list.
RX : Receive Pin (read-only)
bits : 7 - 7 (1 bit)
access : read-write
TDCV : Transceiver Delay Compensation Value (read-only)
bits : 8 - 13 (6 bit)
access : read-write
RAM Watchdog Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDC : Watchdog Configuration (read/write)
bits : 0 - 7 (8 bit)
WDV : Watchdog Value (read-only)
bits : 8 - 15 (8 bit)
RAM Watchdog Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
WDC : Watchdog Configuration (read/write)
bits : 0 - 7 (8 bit)
access : read-write
WDV : Watchdog Value (read-only)
bits : 8 - 15 (8 bit)
access : read-write
CC Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialization (read/write)
bits : 0 - 0 (1 bit)
Enumeration: INITSelect
0 : DISABLED
Normal operation.
1 : ENABLED
Initialization is started.
End of enumeration elements list.
CCE : Configuration Change Enable (read/write, write protection)
bits : 1 - 1 (1 bit)
Enumeration: CCESelect
0 : PROTECTED
The processor has no write access to the protected configuration registers.
1 : CONFIGURABLE
The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1').
End of enumeration elements list.
ASM : Restricted Operation Mode (read/write, write protection against '1')
bits : 2 - 2 (1 bit)
Enumeration: ASMSelect
0 : NORMAL
Normal CAN operation.
1 : RESTRICTED
Restricted operation mode active.
End of enumeration elements list.
CSA : Clock Stop Acknowledge (read-only)
bits : 3 - 3 (1 bit)
CSR : Clock Stop Request (read/write)
bits : 4 - 4 (1 bit)
Enumeration: CSRSelect
0 : NO_CLOCK_STOP
No clock stop is requested.
1 : CLOCK_STOP
Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle.
End of enumeration elements list.
MON : Bus Monitoring Mode (read/write, write protection against '1')
bits : 5 - 5 (1 bit)
Enumeration: MONSelect
0 : DISABLED
Bus Monitoring mode is disabled.
1 : ENABLED
Bus Monitoring mode is enabled.
End of enumeration elements list.
DAR : Disable Automatic Retransmission (read/write, write protection)
bits : 6 - 6 (1 bit)
Enumeration: DARSelect
0 : AUTO_RETX
Automatic retransmission of messages not transmitted successfully enabled.
1 : NO_AUTO_RETX
Automatic retransmission disabled.
End of enumeration elements list.
TEST : Test Mode Enable (read/write, write protection against '1')
bits : 7 - 7 (1 bit)
Enumeration: TESTSelect
0 : DISABLED
Normal operation, MCAN_TEST register holds reset values.
1 : ENABLED
Test mode, write access to MCAN_TEST register enabled.
End of enumeration elements list.
CME : CAN Mode Enable (read/write, write protection)
bits : 8 - 9 (2 bit)
Enumeration: CMESelect
0 : ISO11898_1
CAN operation according to ISO11898-1 enabled
1 : FD
CAN FD operation enabled
End of enumeration elements list.
CMR : CAN Mode Request (read/write)
bits : 10 - 11 (2 bit)
Enumeration: CMRSelect
0 : NO_CHANGE
No mode change
1 : FD
Request CAN FD operation
2 : FD_BITRATE_SWITCH
Request CAN FD operation with bit rate switching
3 : ISO11898_1
Request CAN operation according ISO11898-1
End of enumeration elements list.
FDO : CAN FD Operation (read-only)
bits : 12 - 12 (1 bit)
FDBS : CAN FD Bit Rate Switching (read-only)
bits : 13 - 13 (1 bit)
TXP : Transmit Pause (read/write, write protection)
bits : 14 - 14 (1 bit)
CC Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INIT : Initialization (read/write)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Normal operation.
1 : ENABLED
Initialization is started.
End of enumeration elements list.
CCE : Configuration Change Enable (read/write, write protection)
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PROTECTED
The processor has no write access to the protected configuration registers.
1 : CONFIGURABLE
The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1').
End of enumeration elements list.
ASM : Restricted Operation Mode (read/write, write protection against '1')
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Normal CAN operation.
1 : RESTRICTED
Restricted operation mode active.
End of enumeration elements list.
CSA : Clock Stop Acknowledge (read-only)
bits : 3 - 3 (1 bit)
access : read-write
CSR : Clock Stop Request (read/write)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : NO_CLOCK_STOP
No clock stop is requested.
1 : CLOCK_STOP
Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle.
End of enumeration elements list.
MON : Bus Monitoring Mode (read/write, write protection against '1')
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Bus Monitoring mode is disabled.
1 : ENABLED
Bus Monitoring mode is enabled.
End of enumeration elements list.
DAR : Disable Automatic Retransmission (read/write, write protection)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : AUTO_RETX
Automatic retransmission of messages not transmitted successfully enabled.
1 : NO_AUTO_RETX
Automatic retransmission disabled.
End of enumeration elements list.
TEST : Test Mode Enable (read/write, write protection against '1')
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Normal operation, MCAN_TEST register holds reset values.
1 : ENABLED
Test mode, write access to MCAN_TEST register enabled.
End of enumeration elements list.
CME : CAN Mode Enable (read/write, write protection)
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : ISO11898_1
CAN operation according to ISO11898-1 enabled
1 : FD
CAN FD operation enabled
End of enumeration elements list.
CMR : CAN Mode Request (read/write)
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : NO_CHANGE
No mode change
0x1 : FD
Request CAN FD operation
0x2 : FD_BITRATE_SWITCH
Request CAN FD operation with bit rate switching
0x3 : ISO11898_1
Request CAN operation according ISO11898-1
End of enumeration elements list.
FDO : CAN FD Operation (read-only)
bits : 12 - 12 (1 bit)
access : read-write
FDBS : CAN FD Bit Rate Switching (read-only)
bits : 13 - 13 (1 bit)
access : read-write
TXP : Transmit Pause (read/write, write protection)
bits : 14 - 14 (1 bit)
access : read-write
Bit Timing and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SJW : (Re) Synchronization Jump Width
bits : 0 - 3 (4 bit)
TSEG2 : Time Segment After Sample Point
bits : 4 - 7 (4 bit)
TSEG1 : Time Segment Before Sample Point
bits : 8 - 13 (6 bit)
BRP : Baud Rate Prescaler
bits : 16 - 25 (10 bit)
Bit Timing and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SJW : (Re) Synchronization Jump Width
bits : 0 - 3 (4 bit)
access : read-write
TSEG2 : Time Segment After Sample Point
bits : 4 - 7 (4 bit)
access : read-write
TSEG1 : Time Segment Before Sample Point
bits : 8 - 13 (6 bit)
access : read-write
BRP : Baud Rate Prescaler
bits : 16 - 25 (10 bit)
access : read-write
Timestamp Counter Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Select
bits : 0 - 1 (2 bit)
Enumeration: TSSSelect
0 : ALWAYS_0
Timestamp counter value always 0x0000
1 : TCP_INC
Timestamp counter value incremented according to TCP
2 : EXT_TIMESTAMP
External timestamp counter value used
End of enumeration elements list.
TCP : Timestamp Counter Prescaler
bits : 16 - 19 (4 bit)
Timestamp Counter Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TSS : Timestamp Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : ALWAYS_0
Timestamp counter value always 0x0000
0x1 : TCP_INC
Timestamp counter value incremented according to TCP
0x2 : EXT_TIMESTAMP
External timestamp counter value used
End of enumeration elements list.
TCP : Timestamp Counter Prescaler
bits : 16 - 19 (4 bit)
access : read-write
Timestamp Counter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSC : Timestamp Counter (cleared on write)
bits : 0 - 15 (16 bit)
Timestamp Counter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TSC : Timestamp Counter (cleared on write)
bits : 0 - 15 (16 bit)
access : read-write
Timeout Counter Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
Enumeration: ETOCSelect
0 : NO_TIMEOUT
Timeout Counter disabled.
1 : TOS_CONTROLLED
Timeout Counter enabled.
End of enumeration elements list.
TOS : Timeout Select
bits : 1 - 2 (2 bit)
Enumeration: TOSSelect
0 : CONTINUOUS
Continuous operation
1 : TX_EV_TIMEOUT
Timeout controlled by Tx Event FIFO
2 : RX0_EV_TIMEOUT
Timeout controlled by Receive FIFO 0
3 : RX1_EV_TIMEOUT
Timeout controlled by Receive FIFO 1
End of enumeration elements list.
TOP : Timeout Period
bits : 16 - 31 (16 bit)
Timeout Counter Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_TIMEOUT
Timeout Counter disabled.
1 : TOS_CONTROLLED
Timeout Counter enabled.
End of enumeration elements list.
TOS : Timeout Select
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0x0 : CONTINUOUS
Continuous operation
0x1 : TX_EV_TIMEOUT
Timeout controlled by Tx Event FIFO
0x2 : RX0_EV_TIMEOUT
Timeout controlled by Receive FIFO 0
0x3 : RX1_EV_TIMEOUT
Timeout controlled by Receive FIFO 1
End of enumeration elements list.
TOP : Timeout Period
bits : 16 - 31 (16 bit)
access : read-write
Timeout Counter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC : Timeout Counter (cleared on write)
bits : 0 - 15 (16 bit)
Timeout Counter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TOC : Timeout Counter (cleared on write)
bits : 0 - 15 (16 bit)
access : read-write
Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
REC : Receive Error Counter
bits : 8 - 14 (7 bit)
RP : Receive Error Passive
bits : 15 - 15 (1 bit)
CEL : CAN Error Logging (cleared on read)
bits : 16 - 23 (8 bit)
Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read-only
REC : Receive Error Counter
bits : 8 - 14 (7 bit)
access : read-only
RP : Receive Error Passive
bits : 15 - 15 (1 bit)
access : read-only
CEL : CAN Error Logging (cleared on read)
bits : 16 - 23 (8 bit)
access : read-only
Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code (set to 111 on read)
bits : 0 - 2 (3 bit)
Enumeration: LECSelect
0 : NO_ERROR
No error occurred since LEC has been reset by successful reception or transmission.
1 : STUFF_ERROR
More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
2 : FORM_ERROR
A fixed format part of a received frame has the wrong format.
3 : ACK_ERROR
The message transmitted by the MCAN was not acknowledged by another node.
4 : BIT1_ERROR
During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.
5 : BIT0_ERROR
During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
6 : CRC_ERROR
The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
7 : NO_CHANGE
Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register.
End of enumeration elements list.
ACT : Activity
bits : 3 - 4 (2 bit)
Enumeration: ACTSelect
0 : SYNCHRONIZING
Node is synchronizing on CAN communication
1 : IDLE
Node is neither receiver nor transmitter
2 : RECEIVER
Node is operating as receiver
3 : TRANSMITTER
Node is operating as transmitter
End of enumeration elements list.
EP : Error Passive
bits : 5 - 5 (1 bit)
EW : Warning Status
bits : 6 - 6 (1 bit)
BO : Bus_Off Status
bits : 7 - 7 (1 bit)
FLEC : Fast Last Error Code (set to 111 on read)
bits : 8 - 10 (3 bit)
RESI : ESI Flag of Last Received CAN FD Message (cleared on read)
bits : 11 - 11 (1 bit)
RBRS : BRS Flag of Last Received CAN FD Message (cleared on read)
bits : 12 - 12 (1 bit)
REDL : Received a CAN FD Message (cleared on read)
bits : 13 - 13 (1 bit)
Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
LEC : Last Error Code (set to 111 on read)
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x0 : NO_ERROR
No error occurred since LEC has been reset by successful reception or transmission.
0x1 : STUFF_ERROR
More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x2 : FORM_ERROR
A fixed format part of a received frame has the wrong format.
0x3 : ACK_ERROR
The message transmitted by the MCAN was not acknowledged by another node.
0x4 : BIT1_ERROR
During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.
0x5 : BIT0_ERROR
During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
0x6 : CRC_ERROR
The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
0x7 : NO_CHANGE
Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register.
End of enumeration elements list.
ACT : Activity
bits : 3 - 4 (2 bit)
access : read-only
Enumeration:
0x0 : SYNCHRONIZING
Node is synchronizing on CAN communication
0x1 : IDLE
Node is neither receiver nor transmitter
0x2 : RECEIVER
Node is operating as receiver
0x3 : TRANSMITTER
Node is operating as transmitter
End of enumeration elements list.
EP : Error Passive
bits : 5 - 5 (1 bit)
access : read-only
EW : Warning Status
bits : 6 - 6 (1 bit)
access : read-only
BO : Bus_Off Status
bits : 7 - 7 (1 bit)
access : read-only
FLEC : Fast Last Error Code (set to 111 on read)
bits : 8 - 10 (3 bit)
access : read-only
RESI : ESI Flag of Last Received CAN FD Message (cleared on read)
bits : 11 - 11 (1 bit)
access : read-only
RBRS : BRS Flag of Last Received CAN FD Message (cleared on read)
bits : 12 - 12 (1 bit)
access : read-only
REDL : Received a CAN FD Message (cleared on read)
bits : 13 - 13 (1 bit)
access : read-only
Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0N : Receive FIFO 0 New Message
bits : 0 - 0 (1 bit)
RF0W : Receive FIFO 0 Watermark Reached
bits : 1 - 1 (1 bit)
RF0F : Receive FIFO 0 Full
bits : 2 - 2 (1 bit)
RF0L : Receive FIFO 0 Message Lost
bits : 3 - 3 (1 bit)
RF1N : Receive FIFO 1 New Message
bits : 4 - 4 (1 bit)
RF1W : Receive FIFO 1 Watermark Reached
bits : 5 - 5 (1 bit)
RF1F : Receive FIFO 1 Full
bits : 6 - 6 (1 bit)
RF1L : Receive FIFO 1 Message Lost
bits : 7 - 7 (1 bit)
HPM : High Priority Message
bits : 8 - 8 (1 bit)
TC : Transmission Completed
bits : 9 - 9 (1 bit)
TCF : Transmission Cancellation Finished
bits : 10 - 10 (1 bit)
TFE : Tx FIFO Empty
bits : 11 - 11 (1 bit)
TEFN : Tx Event FIFO New Entry
bits : 12 - 12 (1 bit)
TEFW : Tx Event FIFO Watermark Reached
bits : 13 - 13 (1 bit)
TEFF : Tx Event FIFO Full
bits : 14 - 14 (1 bit)
TEFL : Tx Event FIFO Element Lost
bits : 15 - 15 (1 bit)
TSW : Timestamp Wraparound
bits : 16 - 16 (1 bit)
MRAF : Message RAM Access Failure
bits : 17 - 17 (1 bit)
TOO : Timeout Occurred
bits : 18 - 18 (1 bit)
DRX : Message stored to Dedicated Receive Buffer
bits : 19 - 19 (1 bit)
ELO : Error Logging Overflow
bits : 22 - 22 (1 bit)
EP : Error Passive
bits : 23 - 23 (1 bit)
EW : Warning Status
bits : 24 - 24 (1 bit)
BO : Bus_Off Status
bits : 25 - 25 (1 bit)
WDI : Watchdog Interrupt
bits : 26 - 26 (1 bit)
CRCE : CRC Error
bits : 27 - 27 (1 bit)
BE : Bit Error
bits : 28 - 28 (1 bit)
ACKE : Acknowledge Error
bits : 29 - 29 (1 bit)
FOE : Format Error
bits : 30 - 30 (1 bit)
STE : Stuff Error
bits : 31 - 31 (1 bit)
Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0N : Receive FIFO 0 New Message
bits : 0 - 0 (1 bit)
access : read-write
RF0W : Receive FIFO 0 Watermark Reached
bits : 1 - 1 (1 bit)
access : read-write
RF0F : Receive FIFO 0 Full
bits : 2 - 2 (1 bit)
access : read-write
RF0L : Receive FIFO 0 Message Lost
bits : 3 - 3 (1 bit)
access : read-write
RF1N : Receive FIFO 1 New Message
bits : 4 - 4 (1 bit)
access : read-write
RF1W : Receive FIFO 1 Watermark Reached
bits : 5 - 5 (1 bit)
access : read-write
RF1F : Receive FIFO 1 Full
bits : 6 - 6 (1 bit)
access : read-write
RF1L : Receive FIFO 1 Message Lost
bits : 7 - 7 (1 bit)
access : read-write
HPM : High Priority Message
bits : 8 - 8 (1 bit)
access : read-write
TC : Transmission Completed
bits : 9 - 9 (1 bit)
access : read-write
TCF : Transmission Cancellation Finished
bits : 10 - 10 (1 bit)
access : read-write
TFE : Tx FIFO Empty
bits : 11 - 11 (1 bit)
access : read-write
TEFN : Tx Event FIFO New Entry
bits : 12 - 12 (1 bit)
access : read-write
TEFW : Tx Event FIFO Watermark Reached
bits : 13 - 13 (1 bit)
access : read-write
TEFF : Tx Event FIFO Full
bits : 14 - 14 (1 bit)
access : read-write
TEFL : Tx Event FIFO Element Lost
bits : 15 - 15 (1 bit)
access : read-write
TSW : Timestamp Wraparound
bits : 16 - 16 (1 bit)
access : read-write
MRAF : Message RAM Access Failure
bits : 17 - 17 (1 bit)
access : read-write
TOO : Timeout Occurred
bits : 18 - 18 (1 bit)
access : read-write
DRX : Message stored to Dedicated Receive Buffer
bits : 19 - 19 (1 bit)
access : read-write
ELO : Error Logging Overflow
bits : 22 - 22 (1 bit)
access : read-write
EP : Error Passive
bits : 23 - 23 (1 bit)
access : read-write
EW : Warning Status
bits : 24 - 24 (1 bit)
access : read-write
BO : Bus_Off Status
bits : 25 - 25 (1 bit)
access : read-write
WDI : Watchdog Interrupt
bits : 26 - 26 (1 bit)
access : read-write
CRCE : CRC Error
bits : 27 - 27 (1 bit)
access : read-write
BE : Bit Error
bits : 28 - 28 (1 bit)
access : read-write
ACKE : Acknowledge Error
bits : 29 - 29 (1 bit)
access : read-write
FOE : Format Error
bits : 30 - 30 (1 bit)
access : read-write
STE : Stuff Error
bits : 31 - 31 (1 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NE : Receive FIFO 0 New Message Interrupt Enable
bits : 0 - 0 (1 bit)
RF0WE : Receive FIFO 0 Watermark Reached Interrupt Enable
bits : 1 - 1 (1 bit)
RF0FE : Receive FIFO 0 Full Interrupt Enable
bits : 2 - 2 (1 bit)
RF0LE : Receive FIFO 0 Message Lost Interrupt Enable
bits : 3 - 3 (1 bit)
RF1NE : Receive FIFO 1 New Message Interrupt Enable
bits : 4 - 4 (1 bit)
RF1WE : Receive FIFO 1 Watermark Reached Interrupt Enable
bits : 5 - 5 (1 bit)
RF1FE : Receive FIFO 1 Full Interrupt Enable
bits : 6 - 6 (1 bit)
RF1LE : Receive FIFO 1 Message Lost Interrupt Enable
bits : 7 - 7 (1 bit)
HPME : High Priority Message Interrupt Enable
bits : 8 - 8 (1 bit)
TCE : Transmission Completed Interrupt Enable
bits : 9 - 9 (1 bit)
TCFE : Transmission Cancellation Finished Interrupt Enable
bits : 10 - 10 (1 bit)
TFEE : Tx FIFO Empty Interrupt Enable
bits : 11 - 11 (1 bit)
TEFNE : Tx Event FIFO New Entry Interrupt Enable
bits : 12 - 12 (1 bit)
TEFWE : Tx Event FIFO Watermark Reached Interrupt Enable
bits : 13 - 13 (1 bit)
TEFFE : Tx Event FIFO Full Interrupt Enable
bits : 14 - 14 (1 bit)
TEFLE : Tx Event FIFO Event Lost Interrupt Enable
bits : 15 - 15 (1 bit)
TSWE : Timestamp Wraparound Interrupt Enable
bits : 16 - 16 (1 bit)
MRAFE : Message RAM Access Failure Interrupt Enable
bits : 17 - 17 (1 bit)
TOOE : Timeout Occurred Interrupt Enable
bits : 18 - 18 (1 bit)
DRXE : Message stored to Dedicated Receive Buffer Interrupt Enable
bits : 19 - 19 (1 bit)
ELOE : Error Logging Overflow Interrupt Enable
bits : 22 - 22 (1 bit)
EPE : Error Passive Interrupt Enable
bits : 23 - 23 (1 bit)
EWE : Warning Status Interrupt Enable
bits : 24 - 24 (1 bit)
BOE : Bus_Off Status Interrupt Enable
bits : 25 - 25 (1 bit)
WDIE : Watchdog Interrupt Enable
bits : 26 - 26 (1 bit)
CRCEE : CRC Error Interrupt Enable
bits : 27 - 27 (1 bit)
BEE : Bit Error Interrupt Enable
bits : 28 - 28 (1 bit)
ACKEE : Acknowledge Error Interrupt Enable
bits : 29 - 29 (1 bit)
FOEE : Format Error Interrupt Enable
bits : 30 - 30 (1 bit)
STEE : Stuff Error Interrupt Enable
bits : 31 - 31 (1 bit)
Interrupt Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0NE : Receive FIFO 0 New Message Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
RF0WE : Receive FIFO 0 Watermark Reached Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
RF0FE : Receive FIFO 0 Full Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
RF0LE : Receive FIFO 0 Message Lost Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
RF1NE : Receive FIFO 1 New Message Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
RF1WE : Receive FIFO 1 Watermark Reached Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
RF1FE : Receive FIFO 1 Full Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
RF1LE : Receive FIFO 1 Message Lost Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
HPME : High Priority Message Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
TCE : Transmission Completed Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
TCFE : Transmission Cancellation Finished Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
TFEE : Tx FIFO Empty Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
TEFNE : Tx Event FIFO New Entry Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
TEFWE : Tx Event FIFO Watermark Reached Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
TEFFE : Tx Event FIFO Full Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
TEFLE : Tx Event FIFO Event Lost Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
TSWE : Timestamp Wraparound Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
MRAFE : Message RAM Access Failure Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
TOOE : Timeout Occurred Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
DRXE : Message stored to Dedicated Receive Buffer Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
ELOE : Error Logging Overflow Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
EPE : Error Passive Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
EWE : Warning Status Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
BOE : Bus_Off Status Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write
WDIE : Watchdog Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
CRCEE : CRC Error Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write
BEE : Bit Error Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write
ACKEE : Acknowledge Error Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write
FOEE : Format Error Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write
STEE : Stuff Error Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write
Interrupt Line Select Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RF0NL : Receive FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
RF0WL : Receive FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 1 (1 bit)
RF0FL : Receive FIFO 0 Full Interrupt Line
bits : 2 - 2 (1 bit)
RF0LL : Receive FIFO 0 Message Lost Interrupt Line
bits : 3 - 3 (1 bit)
RF1NL : Receive FIFO 1 New Message Interrupt Line
bits : 4 - 4 (1 bit)
RF1WL : Receive FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 5 (1 bit)
RF1FL : Receive FIFO 1 Full Interrupt Line
bits : 6 - 6 (1 bit)
RF1LL : Receive FIFO 1 Message Lost Interrupt Line
bits : 7 - 7 (1 bit)
HPML : High Priority Message Interrupt Line
bits : 8 - 8 (1 bit)
TCL : Transmission Completed Interrupt Line
bits : 9 - 9 (1 bit)
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 10 (1 bit)
TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 11 (1 bit)
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 12 (1 bit)
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 13 (1 bit)
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 14 (1 bit)
TEFLL : Tx Event FIFO Event Lost Interrupt Line
bits : 15 - 15 (1 bit)
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 16 (1 bit)
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 17 (1 bit)
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 18 (1 bit)
DRXL : Message stored to Dedicated Receive Buffer Interrupt Line
bits : 19 - 19 (1 bit)
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 22 (1 bit)
EPL : Error Passive Interrupt Line
bits : 23 - 23 (1 bit)
EWL : Warning Status Interrupt Line
bits : 24 - 24 (1 bit)
BOL : Bus_Off Status Interrupt Line
bits : 25 - 25 (1 bit)
WDIL : Watchdog Interrupt Line
bits : 26 - 26 (1 bit)
CRCEL : CRC Error Interrupt Line
bits : 27 - 27 (1 bit)
BEL : Bit Error Interrupt Line
bits : 28 - 28 (1 bit)
ACKEL : Acknowledge Error Interrupt Line
bits : 29 - 29 (1 bit)
FOEL : Format Error Interrupt Line
bits : 30 - 30 (1 bit)
STEL : Stuff Error Interrupt Line
bits : 31 - 31 (1 bit)
Interrupt Line Select Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RF0NL : Receive FIFO 0 New Message Interrupt Line
bits : 0 - 0 (1 bit)
access : read-write
RF0WL : Receive FIFO 0 Watermark Reached Interrupt Line
bits : 1 - 1 (1 bit)
access : read-write
RF0FL : Receive FIFO 0 Full Interrupt Line
bits : 2 - 2 (1 bit)
access : read-write
RF0LL : Receive FIFO 0 Message Lost Interrupt Line
bits : 3 - 3 (1 bit)
access : read-write
RF1NL : Receive FIFO 1 New Message Interrupt Line
bits : 4 - 4 (1 bit)
access : read-write
RF1WL : Receive FIFO 1 Watermark Reached Interrupt Line
bits : 5 - 5 (1 bit)
access : read-write
RF1FL : Receive FIFO 1 Full Interrupt Line
bits : 6 - 6 (1 bit)
access : read-write
RF1LL : Receive FIFO 1 Message Lost Interrupt Line
bits : 7 - 7 (1 bit)
access : read-write
HPML : High Priority Message Interrupt Line
bits : 8 - 8 (1 bit)
access : read-write
TCL : Transmission Completed Interrupt Line
bits : 9 - 9 (1 bit)
access : read-write
TCFL : Transmission Cancellation Finished Interrupt Line
bits : 10 - 10 (1 bit)
access : read-write
TFEL : Tx FIFO Empty Interrupt Line
bits : 11 - 11 (1 bit)
access : read-write
TEFNL : Tx Event FIFO New Entry Interrupt Line
bits : 12 - 12 (1 bit)
access : read-write
TEFWL : Tx Event FIFO Watermark Reached Interrupt Line
bits : 13 - 13 (1 bit)
access : read-write
TEFFL : Tx Event FIFO Full Interrupt Line
bits : 14 - 14 (1 bit)
access : read-write
TEFLL : Tx Event FIFO Event Lost Interrupt Line
bits : 15 - 15 (1 bit)
access : read-write
TSWL : Timestamp Wraparound Interrupt Line
bits : 16 - 16 (1 bit)
access : read-write
MRAFL : Message RAM Access Failure Interrupt Line
bits : 17 - 17 (1 bit)
access : read-write
TOOL : Timeout Occurred Interrupt Line
bits : 18 - 18 (1 bit)
access : read-write
DRXL : Message stored to Dedicated Receive Buffer Interrupt Line
bits : 19 - 19 (1 bit)
access : read-write
ELOL : Error Logging Overflow Interrupt Line
bits : 22 - 22 (1 bit)
access : read-write
EPL : Error Passive Interrupt Line
bits : 23 - 23 (1 bit)
access : read-write
EWL : Warning Status Interrupt Line
bits : 24 - 24 (1 bit)
access : read-write
BOL : Bus_Off Status Interrupt Line
bits : 25 - 25 (1 bit)
access : read-write
WDIL : Watchdog Interrupt Line
bits : 26 - 26 (1 bit)
access : read-write
CRCEL : CRC Error Interrupt Line
bits : 27 - 27 (1 bit)
access : read-write
BEL : Bit Error Interrupt Line
bits : 28 - 28 (1 bit)
access : read-write
ACKEL : Acknowledge Error Interrupt Line
bits : 29 - 29 (1 bit)
access : read-write
FOEL : Format Error Interrupt Line
bits : 30 - 30 (1 bit)
access : read-write
STEL : Stuff Error Interrupt Line
bits : 31 - 31 (1 bit)
access : read-write
Interrupt Line Enable Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EINT0 : Enable Interrupt Line 0
bits : 0 - 0 (1 bit)
EINT1 : Enable Interrupt Line 1
bits : 1 - 1 (1 bit)
Interrupt Line Enable Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EINT0 : Enable Interrupt Line 0
bits : 0 - 0 (1 bit)
access : read-write
EINT1 : Enable Interrupt Line 1
bits : 1 - 1 (1 bit)
access : read-write
Customer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSV : Customer-specific Value
bits : 0 - 31 (32 bit)
Customer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CSV : Customer-specific Value
bits : 0 - 31 (32 bit)
access : read-write
Global Filter Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RRFE : Reject Remote Frames Extended
bits : 0 - 0 (1 bit)
Enumeration: RRFESelect
0 : FILTER
Filter remote frames with 29-bit extended IDs.
1 : REJECT
Reject all remote frames with 29-bit extended IDs.
End of enumeration elements list.
RRFS : Reject Remote Frames Standard
bits : 1 - 1 (1 bit)
Enumeration: RRFSSelect
0 : FILTER
Filter remote frames with 11-bit standard IDs.
1 : REJECT
Reject all remote frames with 11-bit standard IDs.
End of enumeration elements list.
ANFE : Accept Non-matching Frames Extended
bits : 2 - 3 (2 bit)
Enumeration: ANFESelect
0 : RX_FIFO_0
Message stored in Receive FIFO 0
1 : RX_FIFO_1
Message stored in Receive FIFO 1
End of enumeration elements list.
ANFS : Accept Non-matching Frames Standard
bits : 4 - 5 (2 bit)
Enumeration: ANFSSelect
0 : RX_FIFO_0
Message stored in Receive FIFO 0
1 : RX_FIFO_1
Message stored in Receive FIFO 1
End of enumeration elements list.
Global Filter Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RRFE : Reject Remote Frames Extended
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : FILTER
Filter remote frames with 29-bit extended IDs.
1 : REJECT
Reject all remote frames with 29-bit extended IDs.
End of enumeration elements list.
RRFS : Reject Remote Frames Standard
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : FILTER
Filter remote frames with 11-bit standard IDs.
1 : REJECT
Reject all remote frames with 11-bit standard IDs.
End of enumeration elements list.
ANFE : Accept Non-matching Frames Extended
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : RX_FIFO_0
Message stored in Receive FIFO 0
1 : RX_FIFO_1
Message stored in Receive FIFO 1
End of enumeration elements list.
ANFS : Accept Non-matching Frames Standard
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : RX_FIFO_0
Message stored in Receive FIFO 0
1 : RX_FIFO_1
Message stored in Receive FIFO 1
End of enumeration elements list.
Standard ID Filter Configuration Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLSSA : Filter List Standard Start Address
bits : 2 - 15 (14 bit)
LSS : List Size Standard
bits : 16 - 23 (8 bit)
Standard ID Filter Configuration Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FLSSA : Filter List Standard Start Address
bits : 2 - 15 (14 bit)
access : read-write
LSS : List Size Standard
bits : 16 - 23 (8 bit)
access : read-write
Extended ID Filter Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLESA : Filter List Extended Start Address
bits : 2 - 15 (14 bit)
LSE : List Size Extended
bits : 16 - 22 (7 bit)
Extended ID Filter Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FLESA : Filter List Extended Start Address
bits : 2 - 15 (14 bit)
access : read-write
LSE : List Size Extended
bits : 16 - 22 (7 bit)
access : read-write
Extended ID AND Mask Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIDM : Extended ID Mask
bits : 0 - 28 (29 bit)
Extended ID AND Mask Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EIDM : Extended ID Mask
bits : 0 - 28 (29 bit)
access : read-write
High Priority Message Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BIDX : Buffer Index
bits : 0 - 5 (6 bit)
MSI : Message Storage Indicator
bits : 6 - 7 (2 bit)
Enumeration: MSISelect
0 : NO_FIFO_SEL
No FIFO selected.
1 : LOST
FIFO message.
2 : FIFO_0
Message stored in FIFO 0.
3 : FIFO_1
Message stored in FIFO 1.
End of enumeration elements list.
FIDX : Filter Index
bits : 8 - 14 (7 bit)
FLST : Filter List
bits : 15 - 15 (1 bit)
High Priority Message Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
BIDX : Buffer Index
bits : 0 - 5 (6 bit)
access : read-only
MSI : Message Storage Indicator
bits : 6 - 7 (2 bit)
access : read-only
Enumeration:
0x0 : NO_FIFO_SEL
No FIFO selected.
0x1 : LOST
FIFO message.
0x2 : FIFO_0
Message stored in FIFO 0.
0x3 : FIFO_1
Message stored in FIFO 1.
End of enumeration elements list.
FIDX : Filter Index
bits : 8 - 14 (7 bit)
access : read-only
FLST : Filter List
bits : 15 - 15 (1 bit)
access : read-only
New Data 1 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND0 : New Data
bits : 0 - 0 (1 bit)
ND1 : New Data
bits : 1 - 1 (1 bit)
ND2 : New Data
bits : 2 - 2 (1 bit)
ND3 : New Data
bits : 3 - 3 (1 bit)
ND4 : New Data
bits : 4 - 4 (1 bit)
ND5 : New Data
bits : 5 - 5 (1 bit)
ND6 : New Data
bits : 6 - 6 (1 bit)
ND7 : New Data
bits : 7 - 7 (1 bit)
ND8 : New Data
bits : 8 - 8 (1 bit)
ND9 : New Data
bits : 9 - 9 (1 bit)
ND10 : New Data
bits : 10 - 10 (1 bit)
ND11 : New Data
bits : 11 - 11 (1 bit)
ND12 : New Data
bits : 12 - 12 (1 bit)
ND13 : New Data
bits : 13 - 13 (1 bit)
ND14 : New Data
bits : 14 - 14 (1 bit)
ND15 : New Data
bits : 15 - 15 (1 bit)
ND16 : New Data
bits : 16 - 16 (1 bit)
ND17 : New Data
bits : 17 - 17 (1 bit)
ND18 : New Data
bits : 18 - 18 (1 bit)
ND19 : New Data
bits : 19 - 19 (1 bit)
ND20 : New Data
bits : 20 - 20 (1 bit)
ND21 : New Data
bits : 21 - 21 (1 bit)
ND22 : New Data
bits : 22 - 22 (1 bit)
ND23 : New Data
bits : 23 - 23 (1 bit)
ND24 : New Data
bits : 24 - 24 (1 bit)
ND25 : New Data
bits : 25 - 25 (1 bit)
ND26 : New Data
bits : 26 - 26 (1 bit)
ND27 : New Data
bits : 27 - 27 (1 bit)
ND28 : New Data
bits : 28 - 28 (1 bit)
ND29 : New Data
bits : 29 - 29 (1 bit)
ND30 : New Data
bits : 30 - 30 (1 bit)
ND31 : New Data
bits : 31 - 31 (1 bit)
New Data 1 Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ND0 : New Data
bits : 0 - 0 (1 bit)
access : read-write
ND1 : New Data
bits : 1 - 1 (1 bit)
access : read-write
ND2 : New Data
bits : 2 - 2 (1 bit)
access : read-write
ND3 : New Data
bits : 3 - 3 (1 bit)
access : read-write
ND4 : New Data
bits : 4 - 4 (1 bit)
access : read-write
ND5 : New Data
bits : 5 - 5 (1 bit)
access : read-write
ND6 : New Data
bits : 6 - 6 (1 bit)
access : read-write
ND7 : New Data
bits : 7 - 7 (1 bit)
access : read-write
ND8 : New Data
bits : 8 - 8 (1 bit)
access : read-write
ND9 : New Data
bits : 9 - 9 (1 bit)
access : read-write
ND10 : New Data
bits : 10 - 10 (1 bit)
access : read-write
ND11 : New Data
bits : 11 - 11 (1 bit)
access : read-write
ND12 : New Data
bits : 12 - 12 (1 bit)
access : read-write
ND13 : New Data
bits : 13 - 13 (1 bit)
access : read-write
ND14 : New Data
bits : 14 - 14 (1 bit)
access : read-write
ND15 : New Data
bits : 15 - 15 (1 bit)
access : read-write
ND16 : New Data
bits : 16 - 16 (1 bit)
access : read-write
ND17 : New Data
bits : 17 - 17 (1 bit)
access : read-write
ND18 : New Data
bits : 18 - 18 (1 bit)
access : read-write
ND19 : New Data
bits : 19 - 19 (1 bit)
access : read-write
ND20 : New Data
bits : 20 - 20 (1 bit)
access : read-write
ND21 : New Data
bits : 21 - 21 (1 bit)
access : read-write
ND22 : New Data
bits : 22 - 22 (1 bit)
access : read-write
ND23 : New Data
bits : 23 - 23 (1 bit)
access : read-write
ND24 : New Data
bits : 24 - 24 (1 bit)
access : read-write
ND25 : New Data
bits : 25 - 25 (1 bit)
access : read-write
ND26 : New Data
bits : 26 - 26 (1 bit)
access : read-write
ND27 : New Data
bits : 27 - 27 (1 bit)
access : read-write
ND28 : New Data
bits : 28 - 28 (1 bit)
access : read-write
ND29 : New Data
bits : 29 - 29 (1 bit)
access : read-write
ND30 : New Data
bits : 30 - 30 (1 bit)
access : read-write
ND31 : New Data
bits : 31 - 31 (1 bit)
access : read-write
New Data 2 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ND32 : New Data
bits : 0 - 0 (1 bit)
ND33 : New Data
bits : 1 - 1 (1 bit)
ND34 : New Data
bits : 2 - 2 (1 bit)
ND35 : New Data
bits : 3 - 3 (1 bit)
ND36 : New Data
bits : 4 - 4 (1 bit)
ND37 : New Data
bits : 5 - 5 (1 bit)
ND38 : New Data
bits : 6 - 6 (1 bit)
ND39 : New Data
bits : 7 - 7 (1 bit)
ND40 : New Data
bits : 8 - 8 (1 bit)
ND41 : New Data
bits : 9 - 9 (1 bit)
ND42 : New Data
bits : 10 - 10 (1 bit)
ND43 : New Data
bits : 11 - 11 (1 bit)
ND44 : New Data
bits : 12 - 12 (1 bit)
ND45 : New Data
bits : 13 - 13 (1 bit)
ND46 : New Data
bits : 14 - 14 (1 bit)
ND47 : New Data
bits : 15 - 15 (1 bit)
ND48 : New Data
bits : 16 - 16 (1 bit)
ND49 : New Data
bits : 17 - 17 (1 bit)
ND50 : New Data
bits : 18 - 18 (1 bit)
ND51 : New Data
bits : 19 - 19 (1 bit)
ND52 : New Data
bits : 20 - 20 (1 bit)
ND53 : New Data
bits : 21 - 21 (1 bit)
ND54 : New Data
bits : 22 - 22 (1 bit)
ND55 : New Data
bits : 23 - 23 (1 bit)
ND56 : New Data
bits : 24 - 24 (1 bit)
ND57 : New Data
bits : 25 - 25 (1 bit)
ND58 : New Data
bits : 26 - 26 (1 bit)
ND59 : New Data
bits : 27 - 27 (1 bit)
ND60 : New Data
bits : 28 - 28 (1 bit)
ND61 : New Data
bits : 29 - 29 (1 bit)
ND62 : New Data
bits : 30 - 30 (1 bit)
ND63 : New Data
bits : 31 - 31 (1 bit)
New Data 2 Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ND32 : New Data
bits : 0 - 0 (1 bit)
access : read-write
ND33 : New Data
bits : 1 - 1 (1 bit)
access : read-write
ND34 : New Data
bits : 2 - 2 (1 bit)
access : read-write
ND35 : New Data
bits : 3 - 3 (1 bit)
access : read-write
ND36 : New Data
bits : 4 - 4 (1 bit)
access : read-write
ND37 : New Data
bits : 5 - 5 (1 bit)
access : read-write
ND38 : New Data
bits : 6 - 6 (1 bit)
access : read-write
ND39 : New Data
bits : 7 - 7 (1 bit)
access : read-write
ND40 : New Data
bits : 8 - 8 (1 bit)
access : read-write
ND41 : New Data
bits : 9 - 9 (1 bit)
access : read-write
ND42 : New Data
bits : 10 - 10 (1 bit)
access : read-write
ND43 : New Data
bits : 11 - 11 (1 bit)
access : read-write
ND44 : New Data
bits : 12 - 12 (1 bit)
access : read-write
ND45 : New Data
bits : 13 - 13 (1 bit)
access : read-write
ND46 : New Data
bits : 14 - 14 (1 bit)
access : read-write
ND47 : New Data
bits : 15 - 15 (1 bit)
access : read-write
ND48 : New Data
bits : 16 - 16 (1 bit)
access : read-write
ND49 : New Data
bits : 17 - 17 (1 bit)
access : read-write
ND50 : New Data
bits : 18 - 18 (1 bit)
access : read-write
ND51 : New Data
bits : 19 - 19 (1 bit)
access : read-write
ND52 : New Data
bits : 20 - 20 (1 bit)
access : read-write
ND53 : New Data
bits : 21 - 21 (1 bit)
access : read-write
ND54 : New Data
bits : 22 - 22 (1 bit)
access : read-write
ND55 : New Data
bits : 23 - 23 (1 bit)
access : read-write
ND56 : New Data
bits : 24 - 24 (1 bit)
access : read-write
ND57 : New Data
bits : 25 - 25 (1 bit)
access : read-write
ND58 : New Data
bits : 26 - 26 (1 bit)
access : read-write
ND59 : New Data
bits : 27 - 27 (1 bit)
access : read-write
ND60 : New Data
bits : 28 - 28 (1 bit)
access : read-write
ND61 : New Data
bits : 29 - 29 (1 bit)
access : read-write
ND62 : New Data
bits : 30 - 30 (1 bit)
access : read-write
ND63 : New Data
bits : 31 - 31 (1 bit)
access : read-write
Receive FIFO 0 Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0SA : Receive FIFO 0 Start Address
bits : 2 - 15 (14 bit)
F0S : Receive FIFO 0 Start Address
bits : 16 - 22 (7 bit)
F0WM : Receive FIFO 0 Watermark
bits : 24 - 30 (7 bit)
F0OM : FIFO 0 Operation Mode
bits : 31 - 31 (1 bit)
Receive FIFO 0 Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0SA : Receive FIFO 0 Start Address
bits : 2 - 15 (14 bit)
access : read-write
F0S : Receive FIFO 0 Start Address
bits : 16 - 22 (7 bit)
access : read-write
F0WM : Receive FIFO 0 Watermark
bits : 24 - 30 (7 bit)
access : read-write
F0OM : FIFO 0 Operation Mode
bits : 31 - 31 (1 bit)
access : read-write
Receive FIFO 0 Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F0FL : Receive FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
F0GI : Receive FIFO 0 Get Index
bits : 8 - 13 (6 bit)
F0PI : Receive FIFO 0 Put Index
bits : 16 - 21 (6 bit)
F0F : Receive FIFO 0 Fill Level
bits : 24 - 24 (1 bit)
RF0L : Receive FIFO 0 Message Lost
bits : 25 - 25 (1 bit)
Receive FIFO 0 Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
F0FL : Receive FIFO 0 Fill Level
bits : 0 - 6 (7 bit)
access : read-only
F0GI : Receive FIFO 0 Get Index
bits : 8 - 13 (6 bit)
access : read-only
F0PI : Receive FIFO 0 Put Index
bits : 16 - 21 (6 bit)
access : read-only
F0F : Receive FIFO 0 Fill Level
bits : 24 - 24 (1 bit)
access : read-only
RF0L : Receive FIFO 0 Message Lost
bits : 25 - 25 (1 bit)
access : read-only
Receive FIFO 0 Acknowledge Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0AI : Receive FIFO 0 Acknowledge Index
bits : 0 - 5 (6 bit)
Receive FIFO 0 Acknowledge Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0AI : Receive FIFO 0 Acknowledge Index
bits : 0 - 5 (6 bit)
access : read-write
Receive Rx Buffer Configuration Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBSA : Receive Buffer Start Address
bits : 2 - 15 (14 bit)
Receive Rx Buffer Configuration Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RBSA : Receive Buffer Start Address
bits : 2 - 15 (14 bit)
access : read-write
Receive FIFO 1 Configuration Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1SA : Receive FIFO 1 Start Address
bits : 2 - 15 (14 bit)
F1S : Receive FIFO 1 Start Address
bits : 16 - 22 (7 bit)
F1WM : Receive FIFO 1 Watermark
bits : 24 - 30 (7 bit)
F1OM : FIFO 1 Operation Mode
bits : 31 - 31 (1 bit)
Receive FIFO 1 Configuration Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F1SA : Receive FIFO 1 Start Address
bits : 2 - 15 (14 bit)
access : read-write
F1S : Receive FIFO 1 Start Address
bits : 16 - 22 (7 bit)
access : read-write
F1WM : Receive FIFO 1 Watermark
bits : 24 - 30 (7 bit)
access : read-write
F1OM : FIFO 1 Operation Mode
bits : 31 - 31 (1 bit)
access : read-write
Receive FIFO 1 Status Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
F1FL : Receive FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
F1GI : Receive FIFO 1 Get Index
bits : 8 - 13 (6 bit)
F1PI : Receive FIFO 1 Put Index
bits : 16 - 21 (6 bit)
F1F : Receive FIFO 1 Fill Level
bits : 24 - 24 (1 bit)
RF1L : Receive FIFO 1 Message Lost
bits : 25 - 25 (1 bit)
DMS : Debug Message Status
bits : 30 - 31 (2 bit)
Enumeration: DMSSelect
0 : IDLE
Idle state, wait for reception of debug messages, DMA request is cleared.
1 : MSG_A
Debug message A received.
2 : MSG_AB
Debug messages A, B received.
3 : MSG_ABC
Debug messages A, B, C received, DMA request is set.
End of enumeration elements list.
Receive FIFO 1 Status Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
F1FL : Receive FIFO 1 Fill Level
bits : 0 - 6 (7 bit)
access : read-only
F1GI : Receive FIFO 1 Get Index
bits : 8 - 13 (6 bit)
access : read-only
F1PI : Receive FIFO 1 Put Index
bits : 16 - 21 (6 bit)
access : read-only
F1F : Receive FIFO 1 Fill Level
bits : 24 - 24 (1 bit)
access : read-only
RF1L : Receive FIFO 1 Message Lost
bits : 25 - 25 (1 bit)
access : read-only
DMS : Debug Message Status
bits : 30 - 31 (2 bit)
access : read-only
Enumeration:
0x0 : IDLE
Idle state, wait for reception of debug messages, DMA request is cleared.
0x1 : MSG_A
Debug message A received.
0x2 : MSG_AB
Debug messages A, B received.
0x3 : MSG_ABC
Debug messages A, B, C received, DMA request is set.
End of enumeration elements list.
Receive FIFO 1 Acknowledge Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F1AI : Receive FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
Receive FIFO 1 Acknowledge Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F1AI : Receive FIFO 1 Acknowledge Index
bits : 0 - 5 (6 bit)
access : read-write
Receive Buffer / FIFO Element Size Configuration Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
F0DS : Receive FIFO 0 Data Field Size
bits : 0 - 2 (3 bit)
Enumeration: F0DSSelect
0 : _8_BYTE
8-byte data field
1 : _12_BYTE
12-byte data field
2 : _16_BYTE
16-byte data field
3 : _20_BYTE
20-byte data field
4 : _24_BYTE
24-byte data field
5 : _32_BYTE
32-byte data field
6 : _48_BYTE
48-byte data field
7 : _64_BYTE
64-byte data field
End of enumeration elements list.
F1DS : Receive FIFO 1 Data Field Size
bits : 4 - 6 (3 bit)
Enumeration: F1DSSelect
0 : _8_BYTE
8-byte data field
1 : _12_BYTE
12-byte data field
2 : _16_BYTE
16-byte data field
3 : _20_BYTE
20-byte data field
4 : _24_BYTE
24-byte data field
5 : _32_BYTE
32-byte data field
6 : _48_BYTE
48-byte data field
7 : _64_BYTE
64-byte data field
End of enumeration elements list.
RBDS : Receive Buffer Data Field Size
bits : 8 - 10 (3 bit)
Enumeration: RBDSSelect
0 : _8_BYTE
8-byte data field
1 : _12_BYTE
12-byte data field
2 : _16_BYTE
16-byte data field
3 : _20_BYTE
20-byte data field
4 : _24_BYTE
24-byte data field
5 : _32_BYTE
32-byte data field
6 : _48_BYTE
48-byte data field
7 : _64_BYTE
64-byte data field
End of enumeration elements list.
Receive Buffer / FIFO Element Size Configuration Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
F0DS : Receive FIFO 0 Data Field Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8-byte data field
0x1 : 12_BYTE
12-byte data field
0x2 : 16_BYTE
16-byte data field
0x3 : 20_BYTE
20-byte data field
0x4 : 24_BYTE
24-byte data field
0x5 : 32_BYTE
32-byte data field
0x6 : 48_BYTE
48-byte data field
0x7 : 64_BYTE
64-byte data field
End of enumeration elements list.
F1DS : Receive FIFO 1 Data Field Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8-byte data field
0x1 : 12_BYTE
12-byte data field
0x2 : 16_BYTE
16-byte data field
0x3 : 20_BYTE
20-byte data field
0x4 : 24_BYTE
24-byte data field
0x5 : 32_BYTE
32-byte data field
0x6 : 48_BYTE
48-byte data field
0x7 : 64_BYTE
64-byte data field
End of enumeration elements list.
RBDS : Receive Buffer Data Field Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8-byte data field
0x1 : 12_BYTE
12-byte data field
0x2 : 16_BYTE
16-byte data field
0x3 : 20_BYTE
20-byte data field
0x4 : 24_BYTE
24-byte data field
0x5 : 32_BYTE
32-byte data field
0x6 : 48_BYTE
48-byte data field
0x7 : 64_BYTE
64-byte data field
End of enumeration elements list.
Fast Bit Timing and Prescaler Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSJW : Fast (Re) Synchronization Jump Width
bits : 0 - 1 (2 bit)
FTSEG2 : Fast Time Segment After Sample Point
bits : 4 - 6 (3 bit)
FTSEG1 : Fast Time Segment Before Sample Point
bits : 8 - 11 (4 bit)
FBRP : Fast Baud Rate Prescaler
bits : 16 - 20 (5 bit)
TDC : Transceiver Delay Compensation
bits : 23 - 23 (1 bit)
Enumeration: TDCSelect
0 : DISABLED
Transceiver Delay Compensation disabled.
1 : ENABLED
Transceiver Delay Compensation enabled.
End of enumeration elements list.
TDCO : Transceiver Delay Compensation Offset
bits : 24 - 28 (5 bit)
Fast Bit Timing and Prescaler Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
FSJW : Fast (Re) Synchronization Jump Width
bits : 0 - 1 (2 bit)
access : read-write
FTSEG2 : Fast Time Segment After Sample Point
bits : 4 - 6 (3 bit)
access : read-write
FTSEG1 : Fast Time Segment Before Sample Point
bits : 8 - 11 (4 bit)
access : read-write
FBRP : Fast Baud Rate Prescaler
bits : 16 - 20 (5 bit)
access : read-write
TDC : Transceiver Delay Compensation
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
Transceiver Delay Compensation disabled.
1 : ENABLED
Transceiver Delay Compensation enabled.
End of enumeration elements list.
TDCO : Transceiver Delay Compensation Offset
bits : 24 - 28 (5 bit)
access : read-write
Transmit Buffer Configuration Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBSA : Tx Buffers Start Address
bits : 2 - 15 (14 bit)
NDTB : Number of Dedicated Transmit Buffers
bits : 16 - 21 (6 bit)
TFQS : Transmit FIFO/Queue Size
bits : 24 - 29 (6 bit)
TFQM : Tx FIFO/Queue Mode
bits : 30 - 30 (1 bit)
Transmit Buffer Configuration Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TBSA : Tx Buffers Start Address
bits : 2 - 15 (14 bit)
access : read-write
NDTB : Number of Dedicated Transmit Buffers
bits : 16 - 21 (6 bit)
access : read-write
TFQS : Transmit FIFO/Queue Size
bits : 24 - 29 (6 bit)
access : read-write
TFQM : Tx FIFO/Queue Mode
bits : 30 - 30 (1 bit)
access : read-write
Transmit FIFO/Queue Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
TFGI : Tx FIFO Get Index
bits : 8 - 12 (5 bit)
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 20 (5 bit)
TFQF : Tx FIFO/Queue Full
bits : 21 - 21 (1 bit)
Transmit FIFO/Queue Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TFFL : Tx FIFO Free Level
bits : 0 - 5 (6 bit)
access : read-only
TFGI : Tx FIFO Get Index
bits : 8 - 12 (5 bit)
access : read-only
TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 20 (5 bit)
access : read-only
TFQF : Tx FIFO/Queue Full
bits : 21 - 21 (1 bit)
access : read-only
Transmit Buffer Element Size Configuration Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBDS : Tx Buffer Data Field Size
bits : 0 - 2 (3 bit)
Enumeration: TBDSSelect
0 : _8_BYTE
8-byte data field
1 : _12_BYTE
12-byte data field
2 : _16_BYTE
16-byte data field
3 : _20_BYTE
20-byte data field
4 : _24_BYTE
24-byte data field
5 : _32_BYTE
32-byte data field
6 : _48_BYTE
48- byte data field
7 : _64_BYTE
64-byte data field
End of enumeration elements list.
Transmit Buffer Element Size Configuration Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TBDS : Tx Buffer Data Field Size
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8-byte data field
0x1 : 12_BYTE
12-byte data field
0x2 : 16_BYTE
16-byte data field
0x3 : 20_BYTE
20-byte data field
0x4 : 24_BYTE
24-byte data field
0x5 : 32_BYTE
32-byte data field
0x6 : 48_BYTE
4- byte data field
0x7 : 64_BYTE
64-byte data field
End of enumeration elements list.
Transmit Buffer Request Pending Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TRP0 : Transmission Request Pending for Buffer 0
bits : 0 - 0 (1 bit)
TRP1 : Transmission Request Pending for Buffer 1
bits : 1 - 1 (1 bit)
TRP2 : Transmission Request Pending for Buffer 2
bits : 2 - 2 (1 bit)
TRP3 : Transmission Request Pending for Buffer 3
bits : 3 - 3 (1 bit)
TRP4 : Transmission Request Pending for Buffer 4
bits : 4 - 4 (1 bit)
TRP5 : Transmission Request Pending for Buffer 5
bits : 5 - 5 (1 bit)
TRP6 : Transmission Request Pending for Buffer 6
bits : 6 - 6 (1 bit)
TRP7 : Transmission Request Pending for Buffer 7
bits : 7 - 7 (1 bit)
TRP8 : Transmission Request Pending for Buffer 8
bits : 8 - 8 (1 bit)
TRP9 : Transmission Request Pending for Buffer 9
bits : 9 - 9 (1 bit)
TRP10 : Transmission Request Pending for Buffer 10
bits : 10 - 10 (1 bit)
TRP11 : Transmission Request Pending for Buffer 11
bits : 11 - 11 (1 bit)
TRP12 : Transmission Request Pending for Buffer 12
bits : 12 - 12 (1 bit)
TRP13 : Transmission Request Pending for Buffer 13
bits : 13 - 13 (1 bit)
TRP14 : Transmission Request Pending for Buffer 14
bits : 14 - 14 (1 bit)
TRP15 : Transmission Request Pending for Buffer 15
bits : 15 - 15 (1 bit)
TRP16 : Transmission Request Pending for Buffer 16
bits : 16 - 16 (1 bit)
TRP17 : Transmission Request Pending for Buffer 17
bits : 17 - 17 (1 bit)
TRP18 : Transmission Request Pending for Buffer 18
bits : 18 - 18 (1 bit)
TRP19 : Transmission Request Pending for Buffer 19
bits : 19 - 19 (1 bit)
TRP20 : Transmission Request Pending for Buffer 20
bits : 20 - 20 (1 bit)
TRP21 : Transmission Request Pending for Buffer 21
bits : 21 - 21 (1 bit)
TRP22 : Transmission Request Pending for Buffer 22
bits : 22 - 22 (1 bit)
TRP23 : Transmission Request Pending for Buffer 23
bits : 23 - 23 (1 bit)
TRP24 : Transmission Request Pending for Buffer 24
bits : 24 - 24 (1 bit)
TRP25 : Transmission Request Pending for Buffer 25
bits : 25 - 25 (1 bit)
TRP26 : Transmission Request Pending for Buffer 26
bits : 26 - 26 (1 bit)
TRP27 : Transmission Request Pending for Buffer 27
bits : 27 - 27 (1 bit)
TRP28 : Transmission Request Pending for Buffer 28
bits : 28 - 28 (1 bit)
TRP29 : Transmission Request Pending for Buffer 29
bits : 29 - 29 (1 bit)
TRP30 : Transmission Request Pending for Buffer 30
bits : 30 - 30 (1 bit)
TRP31 : Transmission Request Pending for Buffer 31
bits : 31 - 31 (1 bit)
Transmit Buffer Request Pending Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TRP0 : Transmission Request Pending for Buffer 0
bits : 0 - 0 (1 bit)
access : read-only
TRP1 : Transmission Request Pending for Buffer 1
bits : 1 - 1 (1 bit)
access : read-only
TRP2 : Transmission Request Pending for Buffer 2
bits : 2 - 2 (1 bit)
access : read-only
TRP3 : Transmission Request Pending for Buffer 3
bits : 3 - 3 (1 bit)
access : read-only
TRP4 : Transmission Request Pending for Buffer 4
bits : 4 - 4 (1 bit)
access : read-only
TRP5 : Transmission Request Pending for Buffer 5
bits : 5 - 5 (1 bit)
access : read-only
TRP6 : Transmission Request Pending for Buffer 6
bits : 6 - 6 (1 bit)
access : read-only
TRP7 : Transmission Request Pending for Buffer 7
bits : 7 - 7 (1 bit)
access : read-only
TRP8 : Transmission Request Pending for Buffer 8
bits : 8 - 8 (1 bit)
access : read-only
TRP9 : Transmission Request Pending for Buffer 9
bits : 9 - 9 (1 bit)
access : read-only
TRP10 : Transmission Request Pending for Buffer 10
bits : 10 - 10 (1 bit)
access : read-only
TRP11 : Transmission Request Pending for Buffer 11
bits : 11 - 11 (1 bit)
access : read-only
TRP12 : Transmission Request Pending for Buffer 12
bits : 12 - 12 (1 bit)
access : read-only
TRP13 : Transmission Request Pending for Buffer 13
bits : 13 - 13 (1 bit)
access : read-only
TRP14 : Transmission Request Pending for Buffer 14
bits : 14 - 14 (1 bit)
access : read-only
TRP15 : Transmission Request Pending for Buffer 15
bits : 15 - 15 (1 bit)
access : read-only
TRP16 : Transmission Request Pending for Buffer 16
bits : 16 - 16 (1 bit)
access : read-only
TRP17 : Transmission Request Pending for Buffer 17
bits : 17 - 17 (1 bit)
access : read-only
TRP18 : Transmission Request Pending for Buffer 18
bits : 18 - 18 (1 bit)
access : read-only
TRP19 : Transmission Request Pending for Buffer 19
bits : 19 - 19 (1 bit)
access : read-only
TRP20 : Transmission Request Pending for Buffer 20
bits : 20 - 20 (1 bit)
access : read-only
TRP21 : Transmission Request Pending for Buffer 21
bits : 21 - 21 (1 bit)
access : read-only
TRP22 : Transmission Request Pending for Buffer 22
bits : 22 - 22 (1 bit)
access : read-only
TRP23 : Transmission Request Pending for Buffer 23
bits : 23 - 23 (1 bit)
access : read-only
TRP24 : Transmission Request Pending for Buffer 24
bits : 24 - 24 (1 bit)
access : read-only
TRP25 : Transmission Request Pending for Buffer 25
bits : 25 - 25 (1 bit)
access : read-only
TRP26 : Transmission Request Pending for Buffer 26
bits : 26 - 26 (1 bit)
access : read-only
TRP27 : Transmission Request Pending for Buffer 27
bits : 27 - 27 (1 bit)
access : read-only
TRP28 : Transmission Request Pending for Buffer 28
bits : 28 - 28 (1 bit)
access : read-only
TRP29 : Transmission Request Pending for Buffer 29
bits : 29 - 29 (1 bit)
access : read-only
TRP30 : Transmission Request Pending for Buffer 30
bits : 30 - 30 (1 bit)
access : read-only
TRP31 : Transmission Request Pending for Buffer 31
bits : 31 - 31 (1 bit)
access : read-only
Transmit Buffer Add Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AR0 : Add Request for Transmit Buffer 0
bits : 0 - 0 (1 bit)
AR1 : Add Request for Transmit Buffer 1
bits : 1 - 1 (1 bit)
AR2 : Add Request for Transmit Buffer 2
bits : 2 - 2 (1 bit)
AR3 : Add Request for Transmit Buffer 3
bits : 3 - 3 (1 bit)
AR4 : Add Request for Transmit Buffer 4
bits : 4 - 4 (1 bit)
AR5 : Add Request for Transmit Buffer 5
bits : 5 - 5 (1 bit)
AR6 : Add Request for Transmit Buffer 6
bits : 6 - 6 (1 bit)
AR7 : Add Request for Transmit Buffer 7
bits : 7 - 7 (1 bit)
AR8 : Add Request for Transmit Buffer 8
bits : 8 - 8 (1 bit)
AR9 : Add Request for Transmit Buffer 9
bits : 9 - 9 (1 bit)
AR10 : Add Request for Transmit Buffer 10
bits : 10 - 10 (1 bit)
AR11 : Add Request for Transmit Buffer 11
bits : 11 - 11 (1 bit)
AR12 : Add Request for Transmit Buffer 12
bits : 12 - 12 (1 bit)
AR13 : Add Request for Transmit Buffer 13
bits : 13 - 13 (1 bit)
AR14 : Add Request for Transmit Buffer 14
bits : 14 - 14 (1 bit)
AR15 : Add Request for Transmit Buffer 15
bits : 15 - 15 (1 bit)
AR16 : Add Request for Transmit Buffer 16
bits : 16 - 16 (1 bit)
AR17 : Add Request for Transmit Buffer 17
bits : 17 - 17 (1 bit)
AR18 : Add Request for Transmit Buffer 18
bits : 18 - 18 (1 bit)
AR19 : Add Request for Transmit Buffer 19
bits : 19 - 19 (1 bit)
AR20 : Add Request for Transmit Buffer 20
bits : 20 - 20 (1 bit)
AR21 : Add Request for Transmit Buffer 21
bits : 21 - 21 (1 bit)
AR22 : Add Request for Transmit Buffer 22
bits : 22 - 22 (1 bit)
AR23 : Add Request for Transmit Buffer 23
bits : 23 - 23 (1 bit)
AR24 : Add Request for Transmit Buffer 24
bits : 24 - 24 (1 bit)
AR25 : Add Request for Transmit Buffer 25
bits : 25 - 25 (1 bit)
AR26 : Add Request for Transmit Buffer 26
bits : 26 - 26 (1 bit)
AR27 : Add Request for Transmit Buffer 27
bits : 27 - 27 (1 bit)
AR28 : Add Request for Transmit Buffer 28
bits : 28 - 28 (1 bit)
AR29 : Add Request for Transmit Buffer 29
bits : 29 - 29 (1 bit)
AR30 : Add Request for Transmit Buffer 30
bits : 30 - 30 (1 bit)
AR31 : Add Request for Transmit Buffer 31
bits : 31 - 31 (1 bit)
Transmit Buffer Add Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
AR0 : Add Request for Transmit Buffer 0
bits : 0 - 0 (1 bit)
access : read-write
AR1 : Add Request for Transmit Buffer 1
bits : 1 - 1 (1 bit)
access : read-write
AR2 : Add Request for Transmit Buffer 2
bits : 2 - 2 (1 bit)
access : read-write
AR3 : Add Request for Transmit Buffer 3
bits : 3 - 3 (1 bit)
access : read-write
AR4 : Add Request for Transmit Buffer 4
bits : 4 - 4 (1 bit)
access : read-write
AR5 : Add Request for Transmit Buffer 5
bits : 5 - 5 (1 bit)
access : read-write
AR6 : Add Request for Transmit Buffer 6
bits : 6 - 6 (1 bit)
access : read-write
AR7 : Add Request for Transmit Buffer 7
bits : 7 - 7 (1 bit)
access : read-write
AR8 : Add Request for Transmit Buffer 8
bits : 8 - 8 (1 bit)
access : read-write
AR9 : Add Request for Transmit Buffer 9
bits : 9 - 9 (1 bit)
access : read-write
AR10 : Add Request for Transmit Buffer 10
bits : 10 - 10 (1 bit)
access : read-write
AR11 : Add Request for Transmit Buffer 11
bits : 11 - 11 (1 bit)
access : read-write
AR12 : Add Request for Transmit Buffer 12
bits : 12 - 12 (1 bit)
access : read-write
AR13 : Add Request for Transmit Buffer 13
bits : 13 - 13 (1 bit)
access : read-write
AR14 : Add Request for Transmit Buffer 14
bits : 14 - 14 (1 bit)
access : read-write
AR15 : Add Request for Transmit Buffer 15
bits : 15 - 15 (1 bit)
access : read-write
AR16 : Add Request for Transmit Buffer 16
bits : 16 - 16 (1 bit)
access : read-write
AR17 : Add Request for Transmit Buffer 17
bits : 17 - 17 (1 bit)
access : read-write
AR18 : Add Request for Transmit Buffer 18
bits : 18 - 18 (1 bit)
access : read-write
AR19 : Add Request for Transmit Buffer 19
bits : 19 - 19 (1 bit)
access : read-write
AR20 : Add Request for Transmit Buffer 20
bits : 20 - 20 (1 bit)
access : read-write
AR21 : Add Request for Transmit Buffer 21
bits : 21 - 21 (1 bit)
access : read-write
AR22 : Add Request for Transmit Buffer 22
bits : 22 - 22 (1 bit)
access : read-write
AR23 : Add Request for Transmit Buffer 23
bits : 23 - 23 (1 bit)
access : read-write
AR24 : Add Request for Transmit Buffer 24
bits : 24 - 24 (1 bit)
access : read-write
AR25 : Add Request for Transmit Buffer 25
bits : 25 - 25 (1 bit)
access : read-write
AR26 : Add Request for Transmit Buffer 26
bits : 26 - 26 (1 bit)
access : read-write
AR27 : Add Request for Transmit Buffer 27
bits : 27 - 27 (1 bit)
access : read-write
AR28 : Add Request for Transmit Buffer 28
bits : 28 - 28 (1 bit)
access : read-write
AR29 : Add Request for Transmit Buffer 29
bits : 29 - 29 (1 bit)
access : read-write
AR30 : Add Request for Transmit Buffer 30
bits : 30 - 30 (1 bit)
access : read-write
AR31 : Add Request for Transmit Buffer 31
bits : 31 - 31 (1 bit)
access : read-write
Transmit Buffer Cancellation Request Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR0 : Cancellation Request for Transmit Buffer 0
bits : 0 - 0 (1 bit)
CR1 : Cancellation Request for Transmit Buffer 1
bits : 1 - 1 (1 bit)
CR2 : Cancellation Request for Transmit Buffer 2
bits : 2 - 2 (1 bit)
CR3 : Cancellation Request for Transmit Buffer 3
bits : 3 - 3 (1 bit)
CR4 : Cancellation Request for Transmit Buffer 4
bits : 4 - 4 (1 bit)
CR5 : Cancellation Request for Transmit Buffer 5
bits : 5 - 5 (1 bit)
CR6 : Cancellation Request for Transmit Buffer 6
bits : 6 - 6 (1 bit)
CR7 : Cancellation Request for Transmit Buffer 7
bits : 7 - 7 (1 bit)
CR8 : Cancellation Request for Transmit Buffer 8
bits : 8 - 8 (1 bit)
CR9 : Cancellation Request for Transmit Buffer 9
bits : 9 - 9 (1 bit)
CR10 : Cancellation Request for Transmit Buffer 10
bits : 10 - 10 (1 bit)
CR11 : Cancellation Request for Transmit Buffer 11
bits : 11 - 11 (1 bit)
CR12 : Cancellation Request for Transmit Buffer 12
bits : 12 - 12 (1 bit)
CR13 : Cancellation Request for Transmit Buffer 13
bits : 13 - 13 (1 bit)
CR14 : Cancellation Request for Transmit Buffer 14
bits : 14 - 14 (1 bit)
CR15 : Cancellation Request for Transmit Buffer 15
bits : 15 - 15 (1 bit)
CR16 : Cancellation Request for Transmit Buffer 16
bits : 16 - 16 (1 bit)
CR17 : Cancellation Request for Transmit Buffer 17
bits : 17 - 17 (1 bit)
CR18 : Cancellation Request for Transmit Buffer 18
bits : 18 - 18 (1 bit)
CR19 : Cancellation Request for Transmit Buffer 19
bits : 19 - 19 (1 bit)
CR20 : Cancellation Request for Transmit Buffer 20
bits : 20 - 20 (1 bit)
CR21 : Cancellation Request for Transmit Buffer 21
bits : 21 - 21 (1 bit)
CR22 : Cancellation Request for Transmit Buffer 22
bits : 22 - 22 (1 bit)
CR23 : Cancellation Request for Transmit Buffer 23
bits : 23 - 23 (1 bit)
CR24 : Cancellation Request for Transmit Buffer 24
bits : 24 - 24 (1 bit)
CR25 : Cancellation Request for Transmit Buffer 25
bits : 25 - 25 (1 bit)
CR26 : Cancellation Request for Transmit Buffer 26
bits : 26 - 26 (1 bit)
CR27 : Cancellation Request for Transmit Buffer 27
bits : 27 - 27 (1 bit)
CR28 : Cancellation Request for Transmit Buffer 28
bits : 28 - 28 (1 bit)
CR29 : Cancellation Request for Transmit Buffer 29
bits : 29 - 29 (1 bit)
CR30 : Cancellation Request for Transmit Buffer 30
bits : 30 - 30 (1 bit)
CR31 : Cancellation Request for Transmit Buffer 31
bits : 31 - 31 (1 bit)
Transmit Buffer Cancellation Request Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CR0 : Cancellation Request for Transmit Buffer 0
bits : 0 - 0 (1 bit)
access : read-write
CR1 : Cancellation Request for Transmit Buffer 1
bits : 1 - 1 (1 bit)
access : read-write
CR2 : Cancellation Request for Transmit Buffer 2
bits : 2 - 2 (1 bit)
access : read-write
CR3 : Cancellation Request for Transmit Buffer 3
bits : 3 - 3 (1 bit)
access : read-write
CR4 : Cancellation Request for Transmit Buffer 4
bits : 4 - 4 (1 bit)
access : read-write
CR5 : Cancellation Request for Transmit Buffer 5
bits : 5 - 5 (1 bit)
access : read-write
CR6 : Cancellation Request for Transmit Buffer 6
bits : 6 - 6 (1 bit)
access : read-write
CR7 : Cancellation Request for Transmit Buffer 7
bits : 7 - 7 (1 bit)
access : read-write
CR8 : Cancellation Request for Transmit Buffer 8
bits : 8 - 8 (1 bit)
access : read-write
CR9 : Cancellation Request for Transmit Buffer 9
bits : 9 - 9 (1 bit)
access : read-write
CR10 : Cancellation Request for Transmit Buffer 10
bits : 10 - 10 (1 bit)
access : read-write
CR11 : Cancellation Request for Transmit Buffer 11
bits : 11 - 11 (1 bit)
access : read-write
CR12 : Cancellation Request for Transmit Buffer 12
bits : 12 - 12 (1 bit)
access : read-write
CR13 : Cancellation Request for Transmit Buffer 13
bits : 13 - 13 (1 bit)
access : read-write
CR14 : Cancellation Request for Transmit Buffer 14
bits : 14 - 14 (1 bit)
access : read-write
CR15 : Cancellation Request for Transmit Buffer 15
bits : 15 - 15 (1 bit)
access : read-write
CR16 : Cancellation Request for Transmit Buffer 16
bits : 16 - 16 (1 bit)
access : read-write
CR17 : Cancellation Request for Transmit Buffer 17
bits : 17 - 17 (1 bit)
access : read-write
CR18 : Cancellation Request for Transmit Buffer 18
bits : 18 - 18 (1 bit)
access : read-write
CR19 : Cancellation Request for Transmit Buffer 19
bits : 19 - 19 (1 bit)
access : read-write
CR20 : Cancellation Request for Transmit Buffer 20
bits : 20 - 20 (1 bit)
access : read-write
CR21 : Cancellation Request for Transmit Buffer 21
bits : 21 - 21 (1 bit)
access : read-write
CR22 : Cancellation Request for Transmit Buffer 22
bits : 22 - 22 (1 bit)
access : read-write
CR23 : Cancellation Request for Transmit Buffer 23
bits : 23 - 23 (1 bit)
access : read-write
CR24 : Cancellation Request for Transmit Buffer 24
bits : 24 - 24 (1 bit)
access : read-write
CR25 : Cancellation Request for Transmit Buffer 25
bits : 25 - 25 (1 bit)
access : read-write
CR26 : Cancellation Request for Transmit Buffer 26
bits : 26 - 26 (1 bit)
access : read-write
CR27 : Cancellation Request for Transmit Buffer 27
bits : 27 - 27 (1 bit)
access : read-write
CR28 : Cancellation Request for Transmit Buffer 28
bits : 28 - 28 (1 bit)
access : read-write
CR29 : Cancellation Request for Transmit Buffer 29
bits : 29 - 29 (1 bit)
access : read-write
CR30 : Cancellation Request for Transmit Buffer 30
bits : 30 - 30 (1 bit)
access : read-write
CR31 : Cancellation Request for Transmit Buffer 31
bits : 31 - 31 (1 bit)
access : read-write
Transmit Buffer Transmission Occurred Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TO0 : Transmission Occurred for Buffer 0
bits : 0 - 0 (1 bit)
TO1 : Transmission Occurred for Buffer 1
bits : 1 - 1 (1 bit)
TO2 : Transmission Occurred for Buffer 2
bits : 2 - 2 (1 bit)
TO3 : Transmission Occurred for Buffer 3
bits : 3 - 3 (1 bit)
TO4 : Transmission Occurred for Buffer 4
bits : 4 - 4 (1 bit)
TO5 : Transmission Occurred for Buffer 5
bits : 5 - 5 (1 bit)
TO6 : Transmission Occurred for Buffer 6
bits : 6 - 6 (1 bit)
TO7 : Transmission Occurred for Buffer 7
bits : 7 - 7 (1 bit)
TO8 : Transmission Occurred for Buffer 8
bits : 8 - 8 (1 bit)
TO9 : Transmission Occurred for Buffer 9
bits : 9 - 9 (1 bit)
TO10 : Transmission Occurred for Buffer 10
bits : 10 - 10 (1 bit)
TO11 : Transmission Occurred for Buffer 11
bits : 11 - 11 (1 bit)
TO12 : Transmission Occurred for Buffer 12
bits : 12 - 12 (1 bit)
TO13 : Transmission Occurred for Buffer 13
bits : 13 - 13 (1 bit)
TO14 : Transmission Occurred for Buffer 14
bits : 14 - 14 (1 bit)
TO15 : Transmission Occurred for Buffer 15
bits : 15 - 15 (1 bit)
TO16 : Transmission Occurred for Buffer 16
bits : 16 - 16 (1 bit)
TO17 : Transmission Occurred for Buffer 17
bits : 17 - 17 (1 bit)
TO18 : Transmission Occurred for Buffer 18
bits : 18 - 18 (1 bit)
TO19 : Transmission Occurred for Buffer 19
bits : 19 - 19 (1 bit)
TO20 : Transmission Occurred for Buffer 20
bits : 20 - 20 (1 bit)
TO21 : Transmission Occurred for Buffer 21
bits : 21 - 21 (1 bit)
TO22 : Transmission Occurred for Buffer 22
bits : 22 - 22 (1 bit)
TO23 : Transmission Occurred for Buffer 23
bits : 23 - 23 (1 bit)
TO24 : Transmission Occurred for Buffer 24
bits : 24 - 24 (1 bit)
TO25 : Transmission Occurred for Buffer 25
bits : 25 - 25 (1 bit)
TO26 : Transmission Occurred for Buffer 26
bits : 26 - 26 (1 bit)
TO27 : Transmission Occurred for Buffer 27
bits : 27 - 27 (1 bit)
TO28 : Transmission Occurred for Buffer 28
bits : 28 - 28 (1 bit)
TO29 : Transmission Occurred for Buffer 29
bits : 29 - 29 (1 bit)
TO30 : Transmission Occurred for Buffer 30
bits : 30 - 30 (1 bit)
TO31 : Transmission Occurred for Buffer 31
bits : 31 - 31 (1 bit)
Transmit Buffer Transmission Occurred Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TO0 : Transmission Occurred for Buffer 0
bits : 0 - 0 (1 bit)
access : read-only
TO1 : Transmission Occurred for Buffer 1
bits : 1 - 1 (1 bit)
access : read-only
TO2 : Transmission Occurred for Buffer 2
bits : 2 - 2 (1 bit)
access : read-only
TO3 : Transmission Occurred for Buffer 3
bits : 3 - 3 (1 bit)
access : read-only
TO4 : Transmission Occurred for Buffer 4
bits : 4 - 4 (1 bit)
access : read-only
TO5 : Transmission Occurred for Buffer 5
bits : 5 - 5 (1 bit)
access : read-only
TO6 : Transmission Occurred for Buffer 6
bits : 6 - 6 (1 bit)
access : read-only
TO7 : Transmission Occurred for Buffer 7
bits : 7 - 7 (1 bit)
access : read-only
TO8 : Transmission Occurred for Buffer 8
bits : 8 - 8 (1 bit)
access : read-only
TO9 : Transmission Occurred for Buffer 9
bits : 9 - 9 (1 bit)
access : read-only
TO10 : Transmission Occurred for Buffer 10
bits : 10 - 10 (1 bit)
access : read-only
TO11 : Transmission Occurred for Buffer 11
bits : 11 - 11 (1 bit)
access : read-only
TO12 : Transmission Occurred for Buffer 12
bits : 12 - 12 (1 bit)
access : read-only
TO13 : Transmission Occurred for Buffer 13
bits : 13 - 13 (1 bit)
access : read-only
TO14 : Transmission Occurred for Buffer 14
bits : 14 - 14 (1 bit)
access : read-only
TO15 : Transmission Occurred for Buffer 15
bits : 15 - 15 (1 bit)
access : read-only
TO16 : Transmission Occurred for Buffer 16
bits : 16 - 16 (1 bit)
access : read-only
TO17 : Transmission Occurred for Buffer 17
bits : 17 - 17 (1 bit)
access : read-only
TO18 : Transmission Occurred for Buffer 18
bits : 18 - 18 (1 bit)
access : read-only
TO19 : Transmission Occurred for Buffer 19
bits : 19 - 19 (1 bit)
access : read-only
TO20 : Transmission Occurred for Buffer 20
bits : 20 - 20 (1 bit)
access : read-only
TO21 : Transmission Occurred for Buffer 21
bits : 21 - 21 (1 bit)
access : read-only
TO22 : Transmission Occurred for Buffer 22
bits : 22 - 22 (1 bit)
access : read-only
TO23 : Transmission Occurred for Buffer 23
bits : 23 - 23 (1 bit)
access : read-only
TO24 : Transmission Occurred for Buffer 24
bits : 24 - 24 (1 bit)
access : read-only
TO25 : Transmission Occurred for Buffer 25
bits : 25 - 25 (1 bit)
access : read-only
TO26 : Transmission Occurred for Buffer 26
bits : 26 - 26 (1 bit)
access : read-only
TO27 : Transmission Occurred for Buffer 27
bits : 27 - 27 (1 bit)
access : read-only
TO28 : Transmission Occurred for Buffer 28
bits : 28 - 28 (1 bit)
access : read-only
TO29 : Transmission Occurred for Buffer 29
bits : 29 - 29 (1 bit)
access : read-only
TO30 : Transmission Occurred for Buffer 30
bits : 30 - 30 (1 bit)
access : read-only
TO31 : Transmission Occurred for Buffer 31
bits : 31 - 31 (1 bit)
access : read-only
Transmit Buffer Cancellation Finished Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CF0 : Cancellation Finished for Transmit Buffer 0
bits : 0 - 0 (1 bit)
CF1 : Cancellation Finished for Transmit Buffer 1
bits : 1 - 1 (1 bit)
CF2 : Cancellation Finished for Transmit Buffer 2
bits : 2 - 2 (1 bit)
CF3 : Cancellation Finished for Transmit Buffer 3
bits : 3 - 3 (1 bit)
CF4 : Cancellation Finished for Transmit Buffer 4
bits : 4 - 4 (1 bit)
CF5 : Cancellation Finished for Transmit Buffer 5
bits : 5 - 5 (1 bit)
CF6 : Cancellation Finished for Transmit Buffer 6
bits : 6 - 6 (1 bit)
CF7 : Cancellation Finished for Transmit Buffer 7
bits : 7 - 7 (1 bit)
CF8 : Cancellation Finished for Transmit Buffer 8
bits : 8 - 8 (1 bit)
CF9 : Cancellation Finished for Transmit Buffer 9
bits : 9 - 9 (1 bit)
CF10 : Cancellation Finished for Transmit Buffer 10
bits : 10 - 10 (1 bit)
CF11 : Cancellation Finished for Transmit Buffer 11
bits : 11 - 11 (1 bit)
CF12 : Cancellation Finished for Transmit Buffer 12
bits : 12 - 12 (1 bit)
CF13 : Cancellation Finished for Transmit Buffer 13
bits : 13 - 13 (1 bit)
CF14 : Cancellation Finished for Transmit Buffer 14
bits : 14 - 14 (1 bit)
CF15 : Cancellation Finished for Transmit Buffer 15
bits : 15 - 15 (1 bit)
CF16 : Cancellation Finished for Transmit Buffer 16
bits : 16 - 16 (1 bit)
CF17 : Cancellation Finished for Transmit Buffer 17
bits : 17 - 17 (1 bit)
CF18 : Cancellation Finished for Transmit Buffer 18
bits : 18 - 18 (1 bit)
CF19 : Cancellation Finished for Transmit Buffer 19
bits : 19 - 19 (1 bit)
CF20 : Cancellation Finished for Transmit Buffer 20
bits : 20 - 20 (1 bit)
CF21 : Cancellation Finished for Transmit Buffer 21
bits : 21 - 21 (1 bit)
CF22 : Cancellation Finished for Transmit Buffer 22
bits : 22 - 22 (1 bit)
CF23 : Cancellation Finished for Transmit Buffer 23
bits : 23 - 23 (1 bit)
CF24 : Cancellation Finished for Transmit Buffer 24
bits : 24 - 24 (1 bit)
CF25 : Cancellation Finished for Transmit Buffer 25
bits : 25 - 25 (1 bit)
CF26 : Cancellation Finished for Transmit Buffer 26
bits : 26 - 26 (1 bit)
CF27 : Cancellation Finished for Transmit Buffer 27
bits : 27 - 27 (1 bit)
CF28 : Cancellation Finished for Transmit Buffer 28
bits : 28 - 28 (1 bit)
CF29 : Cancellation Finished for Transmit Buffer 29
bits : 29 - 29 (1 bit)
CF30 : Cancellation Finished for Transmit Buffer 30
bits : 30 - 30 (1 bit)
CF31 : Cancellation Finished for Transmit Buffer 31
bits : 31 - 31 (1 bit)
Transmit Buffer Cancellation Finished Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
CF0 : Cancellation Finished for Transmit Buffer 0
bits : 0 - 0 (1 bit)
access : read-only
CF1 : Cancellation Finished for Transmit Buffer 1
bits : 1 - 1 (1 bit)
access : read-only
CF2 : Cancellation Finished for Transmit Buffer 2
bits : 2 - 2 (1 bit)
access : read-only
CF3 : Cancellation Finished for Transmit Buffer 3
bits : 3 - 3 (1 bit)
access : read-only
CF4 : Cancellation Finished for Transmit Buffer 4
bits : 4 - 4 (1 bit)
access : read-only
CF5 : Cancellation Finished for Transmit Buffer 5
bits : 5 - 5 (1 bit)
access : read-only
CF6 : Cancellation Finished for Transmit Buffer 6
bits : 6 - 6 (1 bit)
access : read-only
CF7 : Cancellation Finished for Transmit Buffer 7
bits : 7 - 7 (1 bit)
access : read-only
CF8 : Cancellation Finished for Transmit Buffer 8
bits : 8 - 8 (1 bit)
access : read-only
CF9 : Cancellation Finished for Transmit Buffer 9
bits : 9 - 9 (1 bit)
access : read-only
CF10 : Cancellation Finished for Transmit Buffer 10
bits : 10 - 10 (1 bit)
access : read-only
CF11 : Cancellation Finished for Transmit Buffer 11
bits : 11 - 11 (1 bit)
access : read-only
CF12 : Cancellation Finished for Transmit Buffer 12
bits : 12 - 12 (1 bit)
access : read-only
CF13 : Cancellation Finished for Transmit Buffer 13
bits : 13 - 13 (1 bit)
access : read-only
CF14 : Cancellation Finished for Transmit Buffer 14
bits : 14 - 14 (1 bit)
access : read-only
CF15 : Cancellation Finished for Transmit Buffer 15
bits : 15 - 15 (1 bit)
access : read-only
CF16 : Cancellation Finished for Transmit Buffer 16
bits : 16 - 16 (1 bit)
access : read-only
CF17 : Cancellation Finished for Transmit Buffer 17
bits : 17 - 17 (1 bit)
access : read-only
CF18 : Cancellation Finished for Transmit Buffer 18
bits : 18 - 18 (1 bit)
access : read-only
CF19 : Cancellation Finished for Transmit Buffer 19
bits : 19 - 19 (1 bit)
access : read-only
CF20 : Cancellation Finished for Transmit Buffer 20
bits : 20 - 20 (1 bit)
access : read-only
CF21 : Cancellation Finished for Transmit Buffer 21
bits : 21 - 21 (1 bit)
access : read-only
CF22 : Cancellation Finished for Transmit Buffer 22
bits : 22 - 22 (1 bit)
access : read-only
CF23 : Cancellation Finished for Transmit Buffer 23
bits : 23 - 23 (1 bit)
access : read-only
CF24 : Cancellation Finished for Transmit Buffer 24
bits : 24 - 24 (1 bit)
access : read-only
CF25 : Cancellation Finished for Transmit Buffer 25
bits : 25 - 25 (1 bit)
access : read-only
CF26 : Cancellation Finished for Transmit Buffer 26
bits : 26 - 26 (1 bit)
access : read-only
CF27 : Cancellation Finished for Transmit Buffer 27
bits : 27 - 27 (1 bit)
access : read-only
CF28 : Cancellation Finished for Transmit Buffer 28
bits : 28 - 28 (1 bit)
access : read-only
CF29 : Cancellation Finished for Transmit Buffer 29
bits : 29 - 29 (1 bit)
access : read-only
CF30 : Cancellation Finished for Transmit Buffer 30
bits : 30 - 30 (1 bit)
access : read-only
CF31 : Cancellation Finished for Transmit Buffer 31
bits : 31 - 31 (1 bit)
access : read-only
Transmit Buffer Transmission Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE0 : Transmission Interrupt Enable for Buffer 0
bits : 0 - 0 (1 bit)
TIE1 : Transmission Interrupt Enable for Buffer 1
bits : 1 - 1 (1 bit)
TIE2 : Transmission Interrupt Enable for Buffer 2
bits : 2 - 2 (1 bit)
TIE3 : Transmission Interrupt Enable for Buffer 3
bits : 3 - 3 (1 bit)
TIE4 : Transmission Interrupt Enable for Buffer 4
bits : 4 - 4 (1 bit)
TIE5 : Transmission Interrupt Enable for Buffer 5
bits : 5 - 5 (1 bit)
TIE6 : Transmission Interrupt Enable for Buffer 6
bits : 6 - 6 (1 bit)
TIE7 : Transmission Interrupt Enable for Buffer 7
bits : 7 - 7 (1 bit)
TIE8 : Transmission Interrupt Enable for Buffer 8
bits : 8 - 8 (1 bit)
TIE9 : Transmission Interrupt Enable for Buffer 9
bits : 9 - 9 (1 bit)
TIE10 : Transmission Interrupt Enable for Buffer 10
bits : 10 - 10 (1 bit)
TIE11 : Transmission Interrupt Enable for Buffer 11
bits : 11 - 11 (1 bit)
TIE12 : Transmission Interrupt Enable for Buffer 12
bits : 12 - 12 (1 bit)
TIE13 : Transmission Interrupt Enable for Buffer 13
bits : 13 - 13 (1 bit)
TIE14 : Transmission Interrupt Enable for Buffer 14
bits : 14 - 14 (1 bit)
TIE15 : Transmission Interrupt Enable for Buffer 15
bits : 15 - 15 (1 bit)
TIE16 : Transmission Interrupt Enable for Buffer 16
bits : 16 - 16 (1 bit)
TIE17 : Transmission Interrupt Enable for Buffer 17
bits : 17 - 17 (1 bit)
TIE18 : Transmission Interrupt Enable for Buffer 18
bits : 18 - 18 (1 bit)
TIE19 : Transmission Interrupt Enable for Buffer 19
bits : 19 - 19 (1 bit)
TIE20 : Transmission Interrupt Enable for Buffer 20
bits : 20 - 20 (1 bit)
TIE21 : Transmission Interrupt Enable for Buffer 21
bits : 21 - 21 (1 bit)
TIE22 : Transmission Interrupt Enable for Buffer 22
bits : 22 - 22 (1 bit)
TIE23 : Transmission Interrupt Enable for Buffer 23
bits : 23 - 23 (1 bit)
TIE24 : Transmission Interrupt Enable for Buffer 24
bits : 24 - 24 (1 bit)
TIE25 : Transmission Interrupt Enable for Buffer 25
bits : 25 - 25 (1 bit)
TIE26 : Transmission Interrupt Enable for Buffer 26
bits : 26 - 26 (1 bit)
TIE27 : Transmission Interrupt Enable for Buffer 27
bits : 27 - 27 (1 bit)
TIE28 : Transmission Interrupt Enable for Buffer 28
bits : 28 - 28 (1 bit)
TIE29 : Transmission Interrupt Enable for Buffer 29
bits : 29 - 29 (1 bit)
TIE30 : Transmission Interrupt Enable for Buffer 30
bits : 30 - 30 (1 bit)
TIE31 : Transmission Interrupt Enable for Buffer 31
bits : 31 - 31 (1 bit)
Transmit Buffer Transmission Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TIE0 : Transmission Interrupt Enable for Buffer 0
bits : 0 - 0 (1 bit)
access : read-write
TIE1 : Transmission Interrupt Enable for Buffer 1
bits : 1 - 1 (1 bit)
access : read-write
TIE2 : Transmission Interrupt Enable for Buffer 2
bits : 2 - 2 (1 bit)
access : read-write
TIE3 : Transmission Interrupt Enable for Buffer 3
bits : 3 - 3 (1 bit)
access : read-write
TIE4 : Transmission Interrupt Enable for Buffer 4
bits : 4 - 4 (1 bit)
access : read-write
TIE5 : Transmission Interrupt Enable for Buffer 5
bits : 5 - 5 (1 bit)
access : read-write
TIE6 : Transmission Interrupt Enable for Buffer 6
bits : 6 - 6 (1 bit)
access : read-write
TIE7 : Transmission Interrupt Enable for Buffer 7
bits : 7 - 7 (1 bit)
access : read-write
TIE8 : Transmission Interrupt Enable for Buffer 8
bits : 8 - 8 (1 bit)
access : read-write
TIE9 : Transmission Interrupt Enable for Buffer 9
bits : 9 - 9 (1 bit)
access : read-write
TIE10 : Transmission Interrupt Enable for Buffer 10
bits : 10 - 10 (1 bit)
access : read-write
TIE11 : Transmission Interrupt Enable for Buffer 11
bits : 11 - 11 (1 bit)
access : read-write
TIE12 : Transmission Interrupt Enable for Buffer 12
bits : 12 - 12 (1 bit)
access : read-write
TIE13 : Transmission Interrupt Enable for Buffer 13
bits : 13 - 13 (1 bit)
access : read-write
TIE14 : Transmission Interrupt Enable for Buffer 14
bits : 14 - 14 (1 bit)
access : read-write
TIE15 : Transmission Interrupt Enable for Buffer 15
bits : 15 - 15 (1 bit)
access : read-write
TIE16 : Transmission Interrupt Enable for Buffer 16
bits : 16 - 16 (1 bit)
access : read-write
TIE17 : Transmission Interrupt Enable for Buffer 17
bits : 17 - 17 (1 bit)
access : read-write
TIE18 : Transmission Interrupt Enable for Buffer 18
bits : 18 - 18 (1 bit)
access : read-write
TIE19 : Transmission Interrupt Enable for Buffer 19
bits : 19 - 19 (1 bit)
access : read-write
TIE20 : Transmission Interrupt Enable for Buffer 20
bits : 20 - 20 (1 bit)
access : read-write
TIE21 : Transmission Interrupt Enable for Buffer 21
bits : 21 - 21 (1 bit)
access : read-write
TIE22 : Transmission Interrupt Enable for Buffer 22
bits : 22 - 22 (1 bit)
access : read-write
TIE23 : Transmission Interrupt Enable for Buffer 23
bits : 23 - 23 (1 bit)
access : read-write
TIE24 : Transmission Interrupt Enable for Buffer 24
bits : 24 - 24 (1 bit)
access : read-write
TIE25 : Transmission Interrupt Enable for Buffer 25
bits : 25 - 25 (1 bit)
access : read-write
TIE26 : Transmission Interrupt Enable for Buffer 26
bits : 26 - 26 (1 bit)
access : read-write
TIE27 : Transmission Interrupt Enable for Buffer 27
bits : 27 - 27 (1 bit)
access : read-write
TIE28 : Transmission Interrupt Enable for Buffer 28
bits : 28 - 28 (1 bit)
access : read-write
TIE29 : Transmission Interrupt Enable for Buffer 29
bits : 29 - 29 (1 bit)
access : read-write
TIE30 : Transmission Interrupt Enable for Buffer 30
bits : 30 - 30 (1 bit)
access : read-write
TIE31 : Transmission Interrupt Enable for Buffer 31
bits : 31 - 31 (1 bit)
access : read-write
Transmit Buffer Cancellation Finished Interrupt Enable Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFIE0 : Cancellation Finished Interrupt Enable for Transmit Buffer 0
bits : 0 - 0 (1 bit)
CFIE1 : Cancellation Finished Interrupt Enable for Transmit Buffer 1
bits : 1 - 1 (1 bit)
CFIE2 : Cancellation Finished Interrupt Enable for Transmit Buffer 2
bits : 2 - 2 (1 bit)
CFIE3 : Cancellation Finished Interrupt Enable for Transmit Buffer 3
bits : 3 - 3 (1 bit)
CFIE4 : Cancellation Finished Interrupt Enable for Transmit Buffer 4
bits : 4 - 4 (1 bit)
CFIE5 : Cancellation Finished Interrupt Enable for Transmit Buffer 5
bits : 5 - 5 (1 bit)
CFIE6 : Cancellation Finished Interrupt Enable for Transmit Buffer 6
bits : 6 - 6 (1 bit)
CFIE7 : Cancellation Finished Interrupt Enable for Transmit Buffer 7
bits : 7 - 7 (1 bit)
CFIE8 : Cancellation Finished Interrupt Enable for Transmit Buffer 8
bits : 8 - 8 (1 bit)
CFIE9 : Cancellation Finished Interrupt Enable for Transmit Buffer 9
bits : 9 - 9 (1 bit)
CFIE10 : Cancellation Finished Interrupt Enable for Transmit Buffer 10
bits : 10 - 10 (1 bit)
CFIE11 : Cancellation Finished Interrupt Enable for Transmit Buffer 11
bits : 11 - 11 (1 bit)
CFIE12 : Cancellation Finished Interrupt Enable for Transmit Buffer 12
bits : 12 - 12 (1 bit)
CFIE13 : Cancellation Finished Interrupt Enable for Transmit Buffer 13
bits : 13 - 13 (1 bit)
CFIE14 : Cancellation Finished Interrupt Enable for Transmit Buffer 14
bits : 14 - 14 (1 bit)
CFIE15 : Cancellation Finished Interrupt Enable for Transmit Buffer 15
bits : 15 - 15 (1 bit)
CFIE16 : Cancellation Finished Interrupt Enable for Transmit Buffer 16
bits : 16 - 16 (1 bit)
CFIE17 : Cancellation Finished Interrupt Enable for Transmit Buffer 17
bits : 17 - 17 (1 bit)
CFIE18 : Cancellation Finished Interrupt Enable for Transmit Buffer 18
bits : 18 - 18 (1 bit)
CFIE19 : Cancellation Finished Interrupt Enable for Transmit Buffer 19
bits : 19 - 19 (1 bit)
CFIE20 : Cancellation Finished Interrupt Enable for Transmit Buffer 20
bits : 20 - 20 (1 bit)
CFIE21 : Cancellation Finished Interrupt Enable for Transmit Buffer 21
bits : 21 - 21 (1 bit)
CFIE22 : Cancellation Finished Interrupt Enable for Transmit Buffer 22
bits : 22 - 22 (1 bit)
CFIE23 : Cancellation Finished Interrupt Enable for Transmit Buffer 23
bits : 23 - 23 (1 bit)
CFIE24 : Cancellation Finished Interrupt Enable for Transmit Buffer 24
bits : 24 - 24 (1 bit)
CFIE25 : Cancellation Finished Interrupt Enable for Transmit Buffer 25
bits : 25 - 25 (1 bit)
CFIE26 : Cancellation Finished Interrupt Enable for Transmit Buffer 26
bits : 26 - 26 (1 bit)
CFIE27 : Cancellation Finished Interrupt Enable for Transmit Buffer 27
bits : 27 - 27 (1 bit)
CFIE28 : Cancellation Finished Interrupt Enable for Transmit Buffer 28
bits : 28 - 28 (1 bit)
CFIE29 : Cancellation Finished Interrupt Enable for Transmit Buffer 29
bits : 29 - 29 (1 bit)
CFIE30 : Cancellation Finished Interrupt Enable for Transmit Buffer 30
bits : 30 - 30 (1 bit)
CFIE31 : Cancellation Finished Interrupt Enable for Transmit Buffer 31
bits : 31 - 31 (1 bit)
Transmit Buffer Cancellation Finished Interrupt Enable Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CFIE0 : Cancellation Finished Interrupt Enable for Transmit Buffer 0
bits : 0 - 0 (1 bit)
access : read-write
CFIE1 : Cancellation Finished Interrupt Enable for Transmit Buffer 1
bits : 1 - 1 (1 bit)
access : read-write
CFIE2 : Cancellation Finished Interrupt Enable for Transmit Buffer 2
bits : 2 - 2 (1 bit)
access : read-write
CFIE3 : Cancellation Finished Interrupt Enable for Transmit Buffer 3
bits : 3 - 3 (1 bit)
access : read-write
CFIE4 : Cancellation Finished Interrupt Enable for Transmit Buffer 4
bits : 4 - 4 (1 bit)
access : read-write
CFIE5 : Cancellation Finished Interrupt Enable for Transmit Buffer 5
bits : 5 - 5 (1 bit)
access : read-write
CFIE6 : Cancellation Finished Interrupt Enable for Transmit Buffer 6
bits : 6 - 6 (1 bit)
access : read-write
CFIE7 : Cancellation Finished Interrupt Enable for Transmit Buffer 7
bits : 7 - 7 (1 bit)
access : read-write
CFIE8 : Cancellation Finished Interrupt Enable for Transmit Buffer 8
bits : 8 - 8 (1 bit)
access : read-write
CFIE9 : Cancellation Finished Interrupt Enable for Transmit Buffer 9
bits : 9 - 9 (1 bit)
access : read-write
CFIE10 : Cancellation Finished Interrupt Enable for Transmit Buffer 10
bits : 10 - 10 (1 bit)
access : read-write
CFIE11 : Cancellation Finished Interrupt Enable for Transmit Buffer 11
bits : 11 - 11 (1 bit)
access : read-write
CFIE12 : Cancellation Finished Interrupt Enable for Transmit Buffer 12
bits : 12 - 12 (1 bit)
access : read-write
CFIE13 : Cancellation Finished Interrupt Enable for Transmit Buffer 13
bits : 13 - 13 (1 bit)
access : read-write
CFIE14 : Cancellation Finished Interrupt Enable for Transmit Buffer 14
bits : 14 - 14 (1 bit)
access : read-write
CFIE15 : Cancellation Finished Interrupt Enable for Transmit Buffer 15
bits : 15 - 15 (1 bit)
access : read-write
CFIE16 : Cancellation Finished Interrupt Enable for Transmit Buffer 16
bits : 16 - 16 (1 bit)
access : read-write
CFIE17 : Cancellation Finished Interrupt Enable for Transmit Buffer 17
bits : 17 - 17 (1 bit)
access : read-write
CFIE18 : Cancellation Finished Interrupt Enable for Transmit Buffer 18
bits : 18 - 18 (1 bit)
access : read-write
CFIE19 : Cancellation Finished Interrupt Enable for Transmit Buffer 19
bits : 19 - 19 (1 bit)
access : read-write
CFIE20 : Cancellation Finished Interrupt Enable for Transmit Buffer 20
bits : 20 - 20 (1 bit)
access : read-write
CFIE21 : Cancellation Finished Interrupt Enable for Transmit Buffer 21
bits : 21 - 21 (1 bit)
access : read-write
CFIE22 : Cancellation Finished Interrupt Enable for Transmit Buffer 22
bits : 22 - 22 (1 bit)
access : read-write
CFIE23 : Cancellation Finished Interrupt Enable for Transmit Buffer 23
bits : 23 - 23 (1 bit)
access : read-write
CFIE24 : Cancellation Finished Interrupt Enable for Transmit Buffer 24
bits : 24 - 24 (1 bit)
access : read-write
CFIE25 : Cancellation Finished Interrupt Enable for Transmit Buffer 25
bits : 25 - 25 (1 bit)
access : read-write
CFIE26 : Cancellation Finished Interrupt Enable for Transmit Buffer 26
bits : 26 - 26 (1 bit)
access : read-write
CFIE27 : Cancellation Finished Interrupt Enable for Transmit Buffer 27
bits : 27 - 27 (1 bit)
access : read-write
CFIE28 : Cancellation Finished Interrupt Enable for Transmit Buffer 28
bits : 28 - 28 (1 bit)
access : read-write
CFIE29 : Cancellation Finished Interrupt Enable for Transmit Buffer 29
bits : 29 - 29 (1 bit)
access : read-write
CFIE30 : Cancellation Finished Interrupt Enable for Transmit Buffer 30
bits : 30 - 30 (1 bit)
access : read-write
CFIE31 : Cancellation Finished Interrupt Enable for Transmit Buffer 31
bits : 31 - 31 (1 bit)
access : read-write
Transmit Event FIFO Configuration Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFSA : Event FIFO Start Address
bits : 2 - 15 (14 bit)
EFS : Event FIFO Size
bits : 16 - 21 (6 bit)
EFWM : Event FIFO Watermark
bits : 24 - 29 (6 bit)
Transmit Event FIFO Configuration Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EFSA : Event FIFO Start Address
bits : 2 - 15 (14 bit)
access : read-write
EFS : Event FIFO Size
bits : 16 - 21 (6 bit)
access : read-write
EFWM : Event FIFO Watermark
bits : 24 - 29 (6 bit)
access : read-write
Transmit Event FIFO Status Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
EFGI : Event FIFO Get Index
bits : 8 - 12 (5 bit)
EFPI : Event FIFO Put Index
bits : 16 - 20 (5 bit)
EFF : Event FIFO Full
bits : 24 - 24 (1 bit)
TEFL : Tx Event FIFO Element Lost
bits : 25 - 25 (1 bit)
Transmit Event FIFO Status Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
EFFL : Event FIFO Fill Level
bits : 0 - 5 (6 bit)
access : read-only
EFGI : Event FIFO Get Index
bits : 8 - 12 (5 bit)
access : read-only
EFPI : Event FIFO Put Index
bits : 16 - 20 (5 bit)
access : read-only
EFF : Event FIFO Full
bits : 24 - 24 (1 bit)
access : read-only
TEFL : Tx Event FIFO Element Lost
bits : 25 - 25 (1 bit)
access : read-only
Transmit Event FIFO Acknowledge Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
Transmit Event FIFO Acknowledge Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
EFAI : Event FIFO Acknowledge Index
bits : 0 - 4 (5 bit)
access : read-write
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