\n

FPU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

Registers

MVFR0

MVFR1

MVFR2

FPCCR

FPCAR

FPDSCR


MVFR0

Media and VFP Feature Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MVFR0 MVFR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A_SIMD_registers Single_precision Double_precision FP_excep_trapping Divide Square_root Short_vectors FP_rounding_modes

A_SIMD_registers : Indicates the size of the FP register bank
bits : 0 - 3 (4 bit)

Single_precision : Indicates the hardware support for FP single-precision operations
bits : 4 - 7 (4 bit)

Double_precision : Indicates the hardware support for FP double-precision operations
bits : 8 - 11 (4 bit)

FP_excep_trapping : Indicates whether the FP hardware implementation supports exception trapping
bits : 12 - 15 (4 bit)

Divide : Indicates the hardware support for FP divide operations
bits : 16 - 19 (4 bit)

Square_root : Indicates the hardware support for FP square root operations
bits : 20 - 23 (4 bit)

Short_vectors : Indicates the hardware support for FP short vectors
bits : 24 - 27 (4 bit)

FP_rounding_modes : Indicates the rounding modes supported by the FP floating-point hardware
bits : 28 - 31 (4 bit)


MVFR1

Media and VFP Feature Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MVFR1 MVFR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FtZ_mode D_NaN_mode FP_HPFP FP_fused_MAC

FtZ_mode : Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation
bits : 0 - 3 (4 bit)

D_NaN_mode : Indicates whether the FP hardware implementation supports only the Default NaN mode
bits : 4 - 7 (4 bit)

FP_HPFP : Floating Point Half-Precision and double-precision
bits : 24 - 27 (4 bit)

FP_fused_MAC : Indicates whether the FP supports fused multiply accumulate operations
bits : 28 - 31 (4 bit)


MVFR2

Media and VFP Feature Register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MVFR2 MVFR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VFP_Misc

VFP_Misc : Indicates the hardware support for FP miscellaneous features
bits : 4 - 7 (4 bit)


FPCCR

Floating-point Context Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCCR FPCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSPACT USER THREAD HFRDY MMRDY BFRDY MONRDY LSPEN ASPEN

LSPACT : Lazy state preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred.
bits : 0 - 0 (1 bit)

USER : Privilege level was user when the floating-point stack frame was allocated.
bits : 1 - 1 (1 bit)

THREAD : Mode was Thread Mode when the floating-point stack frame was allocated.
bits : 3 - 3 (1 bit)

HFRDY : Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
bits : 4 - 4 (1 bit)

MMRDY : MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
bits : 5 - 5 (1 bit)

BFRDY : BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
bits : 6 - 6 (1 bit)

MONRDY : DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated.
bits : 8 - 8 (1 bit)

LSPEN : Enable automatic lazy state preservation for floating-point context.
bits : 30 - 30 (1 bit)

ASPEN : Enables CONTROL.FPCA setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit.
bits : 31 - 31 (1 bit)


FPCAR

Floating-point Context Address Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCAR FPCAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : The location of the unpopulated floating-point register space allocated on an exception stack frame.
bits : 3 - 31 (29 bit)


FPDSCR

Floating-point Default Status Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPDSCR FPDSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMode FZ DN AHP

RMode : Default value for FPSCR.RMode.
bits : 22 - 23 (2 bit)

FZ : Default value for FPSCR.FZ.
bits : 24 - 24 (1 bit)

DN : Default value for FPSCR.DN.
bits : 25 - 25 (1 bit)

AHP : Default value for FPSCR.AHP.
bits : 26 - 26 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.