Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
QSPIEN : QSPI Enable
bits : 0 - 0 (1 bit)
QSPIDIS : QSPI Disable
bits : 1 - 1 (1 bit)
SWRST : QSPI Software Reset
bits : 7 - 7 (1 bit)
LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full (cleared by reading SPI_RDR)
bits : 0 - 0 (1 bit)
TDRE : Transmit Data Register Empty (cleared by writing SPI_TDR)
bits : 1 - 1 (1 bit)
TXEMPTY : Transmission Registers Empty (cleared by writing SPI_TDR)
bits : 2 - 2 (1 bit)
OVRES : Overrun Error Status (cleared on read)
bits : 3 - 3 (1 bit)
CSR : Chip Select Rise (cleared on read)
bits : 8 - 8 (1 bit)
CSS : Chip Select Status
bits : 9 - 9 (1 bit)
INSTRE : Instruction End Status (cleared on read)
bits : 10 - 10 (1 bit)
QSPIENS : QSPI Enable Status
bits : 24 - 24 (1 bit)
Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Enable
bits : 0 - 0 (1 bit)
TDRE : Transmit Data Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
TXEMPTY : Transmission Registers Empty Enable
bits : 2 - 2 (1 bit)
OVRES : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
CSR : Chip Select Rise Interrupt Enable
bits : 8 - 8 (1 bit)
CSS : Chip Select Status Interrupt Enable
bits : 9 - 9 (1 bit)
INSTRE : Instruction End Interrupt Enable
bits : 10 - 10 (1 bit)
Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Disable
bits : 0 - 0 (1 bit)
TDRE : Transmit Data Register Empty Interrupt Disable
bits : 1 - 1 (1 bit)
TXEMPTY : Transmission Registers Empty Disable
bits : 2 - 2 (1 bit)
OVRES : Overrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
CSR : Chip Select Rise Interrupt Disable
bits : 8 - 8 (1 bit)
CSS : Chip Select Status Interrupt Disable
bits : 9 - 9 (1 bit)
INSTRE : Instruction End Interrupt Disable
bits : 10 - 10 (1 bit)
Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDRF : Receive Data Register Full Interrupt Mask
bits : 0 - 0 (1 bit)
TDRE : Transmit Data Register Empty Interrupt Mask
bits : 1 - 1 (1 bit)
TXEMPTY : Transmission Registers Empty Mask
bits : 2 - 2 (1 bit)
OVRES : Overrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
CSR : Chip Select Rise Interrupt Mask
bits : 8 - 8 (1 bit)
CSS : Chip Select Status Interrupt Mask
bits : 9 - 9 (1 bit)
INSTRE : Instruction End Interrupt Mask
bits : 10 - 10 (1 bit)
Serial Clock Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
CPHA : Clock Phase
bits : 1 - 1 (1 bit)
SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
DLYBS : Delay Before QSCK
bits : 16 - 23 (8 bit)
Instruction Address Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address
bits : 0 - 31 (32 bit)
Instruction Code Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INST : Instruction Code
bits : 0 - 7 (8 bit)
OPT : Option Code
bits : 16 - 23 (8 bit)
Instruction Frame Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WIDTH : Width of Instruction Code, Address, Option Code and Data
bits : 0 - 2 (3 bit)
Enumeration: WIDTHSelect
0 : SINGLE_BIT_SPI
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
1 : DUAL_OUTPUT
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
2 : QUAD_OUTPUT
Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
3 : DUAL_IO
Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
4 : QUAD_IO
Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
5 : DUAL_CMD
Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
6 : QUAD_CMD
Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI
End of enumeration elements list.
INSTEN : Instruction Enable
bits : 4 - 4 (1 bit)
ADDREN : Address Enable
bits : 5 - 5 (1 bit)
OPTEN : Option Enable
bits : 6 - 6 (1 bit)
DATAEN : Data Enable
bits : 7 - 7 (1 bit)
OPTL : Option Code Length
bits : 8 - 9 (2 bit)
Enumeration: OPTLSelect
0 : OPTION_1BIT
The option code is 1 bit long.
1 : OPTION_2BIT
The option code is 2 bits long.
2 : OPTION_4BIT
The option code is 4 bits long.
3 : OPTION_8BIT
The option code is 8 bits long.
End of enumeration elements list.
ADDRL : Address Length
bits : 10 - 10 (1 bit)
Enumeration: ADDRLSelect
0 : _24_BIT
The address is 24 bits long.
1 : _32_BIT
The address is 32 bits long.
End of enumeration elements list.
TFRTYP : Data Transfer Type
bits : 12 - 13 (2 bit)
Enumeration: TFRTYPSelect
0 : TRSFR_READ
Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible.
1 : TRSFR_READ_MEMORY
Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible.
2 : TRSFR_WRITE
Write transfer into the serial memory.Scrambling is not performed.
3 : TRSFR_WRITE_MEMORY
Write data transfer into the serial memory.If enabled, scrambling is performed.
End of enumeration elements list.
CRM : Continuous Read Mode
bits : 14 - 14 (1 bit)
Enumeration: CRMSelect
0 : DISABLED
The Continuous Read mode is disabled.
1 : ENABLED
The Continuous Read mode is enabled.
End of enumeration elements list.
NBDUM : Number Of Dummy Cycles
bits : 16 - 20 (5 bit)
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMM : Serial Memory Mode
bits : 0 - 0 (1 bit)
Enumeration: SMMSelect
0 : SPI
The QSPI is in SPI mode.
1 : MEMORY
The QSPI is in Serial Memory mode.
End of enumeration elements list.
LLB : Local Loopback Enable
bits : 1 - 1 (1 bit)
Enumeration: LLBSelect
0 : DISABLED
Local loopback path disabled.
1 : ENABLED
Local loopback path enabled.
End of enumeration elements list.
WDRBT : Wait Data Read Before Transfer
bits : 2 - 2 (1 bit)
Enumeration: WDRBTSelect
0 : DISABLED
No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is.
1 : ENABLED
In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.
End of enumeration elements list.
CSMODE : Chip Select Mode
bits : 4 - 5 (2 bit)
Enumeration: CSMODESelect
0 : NOT_RELOADED
The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer.
1 : LASTXFER
The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred.
2 : SYSTEMATICALLY
The chip select is deasserted systematically after each transfer.
End of enumeration elements list.
NBBITS : Number Of Bits Per Transfer
bits : 8 - 11 (4 bit)
Enumeration: NBBITSSelect
0 : _8_BIT
8 bits for transfer
8 : _16_BIT
16 bits for transfer
End of enumeration elements list.
DLYBCT : Delay Between Consecutive Transfers
bits : 16 - 23 (8 bit)
DLYCS : Minimum Inactive QCS Delay
bits : 24 - 31 (8 bit)
Scrambling Mode Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCREN : Scrambling/Unscrambling Enable
bits : 0 - 0 (1 bit)
Enumeration: SCRENSelect
0 : DISABLED
The scrambling/unscrambling is disabled.
1 : ENABLED
The scrambling/unscrambling is enabled.
End of enumeration elements list.
RVDIS : Scrambling/Unscrambling Random Value Disable
bits : 1 - 1 (1 bit)
Scrambling Key Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
USRK : Scrambling User Key
bits : 0 - 31 (32 bit)
Receive Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RD : Receive Data
bits : 0 - 15 (16 bit)
Transmit Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TD : Transmit Data
bits : 0 - 15 (16 bit)
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
5329744 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
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