Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDTIM : Update Request Time Register
bits : 0 - 0 (1 bit)
UPDCAL : Update Request Calendar Register
bits : 1 - 1 (1 bit)
TIMEVSEL : Time Event Selection
bits : 8 - 9 (2 bit)
Enumeration: TIMEVSELSelect
0 : MINUTE
Minute change
1 : HOUR
Hour change
2 : MIDNIGHT
Every day at midnight
3 : NOON
Every day at noon
End of enumeration elements list.
CALEVSEL : Calendar Event Selection
bits : 16 - 17 (2 bit)
Enumeration: CALEVSELSelect
0 : WEEK
Week change (every Monday at time 00:00:00)
1 : MONTH
Month change (every 01 of each month at time 00:00:00)
2 : YEAR
Year change (every January 1 at time 00:00:00)
End of enumeration elements list.
Time Alarm Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : Second Alarm
bits : 0 - 6 (7 bit)
SECEN : Second Alarm Enable
bits : 7 - 7 (1 bit)
MIN : Minute Alarm
bits : 8 - 14 (7 bit)
MINEN : Minute Alarm Enable
bits : 15 - 15 (1 bit)
HOUR : Hour Alarm
bits : 16 - 21 (6 bit)
AMPM : AM/PM Indicator
bits : 22 - 22 (1 bit)
HOUREN : Hour Alarm Enable
bits : 23 - 23 (1 bit)
Calendar Alarm Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MONTH : Month Alarm
bits : 16 - 20 (5 bit)
MTHEN : Month Alarm Enable
bits : 23 - 23 (1 bit)
DATE : Date Alarm
bits : 24 - 29 (6 bit)
DATEEN : Date Alarm Enable
bits : 31 - 31 (1 bit)
Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACKUPD : Acknowledge for Update
bits : 0 - 0 (1 bit)
Enumeration: ACKUPDSelect
0 : FREERUN
Time and calendar registers cannot be updated.
1 : UPDATE
Time and calendar registers can be updated.
End of enumeration elements list.
ALARM : Alarm Flag
bits : 1 - 1 (1 bit)
Enumeration: ALARMSelect
0 : NO_ALARMEVENT
No alarm matching condition occurred.
1 : ALARMEVENT
An alarm matching condition has occurred.
End of enumeration elements list.
SEC : Second Event
bits : 2 - 2 (1 bit)
Enumeration: SECSelect
0 : NO_SECEVENT
No second event has occurred since the last clear.
1 : SECEVENT
At least one second event has occurred since the last clear.
End of enumeration elements list.
TIMEV : Time Event
bits : 3 - 3 (1 bit)
Enumeration: TIMEVSelect
0 : NO_TIMEVENT
No time event has occurred since the last clear.
1 : TIMEVENT
At least one time event has occurred since the last clear.
End of enumeration elements list.
CALEV : Calendar Event
bits : 4 - 4 (1 bit)
Enumeration: CALEVSelect
0 : NO_CALEVENT
No calendar event has occurred since the last clear.
1 : CALEVENT
At least one calendar event has occurred since the last clear.
End of enumeration elements list.
TDERR : Time and/or Date Free Running Error
bits : 5 - 5 (1 bit)
Enumeration: TDERRSelect
0 : CORRECT
The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR).
1 : ERR_TIMEDATE
The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid.
End of enumeration elements list.
Status Clear Command Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ACKCLR : Acknowledge Clear
bits : 0 - 0 (1 bit)
ALRCLR : Alarm Clear
bits : 1 - 1 (1 bit)
SECCLR : Second Clear
bits : 2 - 2 (1 bit)
TIMCLR : Time Clear
bits : 3 - 3 (1 bit)
CALCLR : Calendar Clear
bits : 4 - 4 (1 bit)
TDERRCLR : Time and/or Date Free Running Error Clear
bits : 5 - 5 (1 bit)
Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ACKEN : Acknowledge Update Interrupt Enable
bits : 0 - 0 (1 bit)
ALREN : Alarm Interrupt Enable
bits : 1 - 1 (1 bit)
SECEN : Second Event Interrupt Enable
bits : 2 - 2 (1 bit)
TIMEN : Time Event Interrupt Enable
bits : 3 - 3 (1 bit)
CALEN : Calendar Event Interrupt Enable
bits : 4 - 4 (1 bit)
TDERREN : Time and/or Date Error Interrupt Enable
bits : 5 - 5 (1 bit)
Interrupt Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ACKDIS : Acknowledge Update Interrupt Disable
bits : 0 - 0 (1 bit)
ALRDIS : Alarm Interrupt Disable
bits : 1 - 1 (1 bit)
SECDIS : Second Event Interrupt Disable
bits : 2 - 2 (1 bit)
TIMDIS : Time Event Interrupt Disable
bits : 3 - 3 (1 bit)
CALDIS : Calendar Event Interrupt Disable
bits : 4 - 4 (1 bit)
TDERRDIS : Time and/or Date Error Interrupt Disable
bits : 5 - 5 (1 bit)
Interrupt Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACK : Acknowledge Update Interrupt Mask
bits : 0 - 0 (1 bit)
ALR : Alarm Interrupt Mask
bits : 1 - 1 (1 bit)
SEC : Second Event Interrupt Mask
bits : 2 - 2 (1 bit)
TIM : Time Event Interrupt Mask
bits : 3 - 3 (1 bit)
CAL : Calendar Event Interrupt Mask
bits : 4 - 4 (1 bit)
TDERR : Time and/or Date Error Mask
bits : 5 - 5 (1 bit)
Valid Entry Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NVTIM : Non-valid Time
bits : 0 - 0 (1 bit)
NVCAL : Non-valid Calendar
bits : 1 - 1 (1 bit)
NVTIMALR : Non-valid Time Alarm
bits : 2 - 2 (1 bit)
NVCALALR : Non-valid Calendar Alarm
bits : 3 - 3 (1 bit)
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HRMOD : 12-/24-hour Mode
bits : 0 - 0 (1 bit)
PERSIAN : PERSIAN Calendar
bits : 1 - 1 (1 bit)
NEGPPM : NEGative PPM Correction
bits : 4 - 4 (1 bit)
CORRECTION : Slow Clock Correction
bits : 8 - 14 (7 bit)
HIGHPPM : HIGH PPM Correction
bits : 15 - 15 (1 bit)
OUT0 : RTCOUT0 OutputSource Selection
bits : 16 - 18 (3 bit)
Enumeration: OUT0Select
0 : NO_WAVE
No waveform, stuck at '0'
1 : FREQ1HZ
1 Hz square wave
2 : FREQ32HZ
32 Hz square wave
3 : FREQ64HZ
64 Hz square wave
4 : FREQ512HZ
512 Hz square wave
5 : ALARM_TOGGLE
Output toggles when alarm flag rises
6 : ALARM_FLAG
Output is a copy of the alarm flag
7 : PROG_PULSE
Duty cycle programmable pulse
End of enumeration elements list.
OUT1 : RTCOUT1 Output Source Selection
bits : 20 - 22 (3 bit)
Enumeration: OUT1Select
0 : NO_WAVE
No waveform, stuck at '0'
1 : FREQ1HZ
1 Hz square wave
2 : FREQ32HZ
32 Hz square wave
3 : FREQ64HZ
64 Hz square wave
4 : FREQ512HZ
512 Hz square wave
5 : ALARM_TOGGLE
Output toggles when alarm flag rises
6 : ALARM_FLAG
Output is a copy of the alarm flag
7 : PROG_PULSE
Duty cycle programmable pulse
End of enumeration elements list.
THIGH : High Duration of the Output Pulse
bits : 24 - 26 (3 bit)
Enumeration: THIGHSelect
0 : H_31MS
31.2 ms
1 : H_16MS
15.6 ms
2 : H_4MS
3.91 ms
3 : H_976US
976 us
4 : H_488US
488 us
5 : H_122US
122 us
6 : H_30US
30.5 us
7 : H_15US
15.2 us
End of enumeration elements list.
TPERIOD : Period of the Output Pulse
bits : 28 - 29 (2 bit)
Enumeration: TPERIODSelect
0 : P_1S
1 second
1 : P_500MS
500 ms
2 : P_250MS
250 ms
3 : P_125MS
125 ms
End of enumeration elements list.
Time Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : Current Second
bits : 0 - 6 (7 bit)
MIN : Current Minute
bits : 8 - 14 (7 bit)
HOUR : Current Hour
bits : 16 - 21 (6 bit)
AMPM : Ante Meridiem Post Meridiem Indicator
bits : 22 - 22 (1 bit)
Calendar Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CENT : Current Century
bits : 0 - 6 (7 bit)
YEAR : Current Year
bits : 8 - 15 (8 bit)
MONTH : Current Month
bits : 16 - 20 (5 bit)
DAY : Current Day in Current Week
bits : 21 - 23 (3 bit)
DATE : Current Day in Current Month
bits : 24 - 29 (6 bit)
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