Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xE8 byte (0x0)
mem_usage : registers
protection : not protected
TC_TC_CHANNEL[0]-TC_CMR_CAPTURE_MODE
TC_TC_CHANNEL[0]-TC_CMR_WAVEFORM_MODE
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR_CAPTURE_MODE
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR_WAVEFORM_MODE
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR
TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR_CAPTURE_MODE
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR_WAVEFORM_MODE
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR
TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR
Channel Control Register (channel = 0)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Channel Control Register (channel = 0)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Counter Value (channel = 0)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 31 (32 bit)
Counter Value (channel = 0)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 31 (32 bit)
Register A (channel = 0)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 31 (32 bit)
Register A (channel = 0)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 31 (32 bit)
Register B (channel = 0)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 31 (32 bit)
Register B (channel = 0)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 31 (32 bit)
Register C (channel = 0)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 31 (32 bit)
Register C (channel = 0)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 31 (32 bit)
Status Register (channel = 0)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status (cleared on read)
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun Status (cleared on read)
bits : 1 - 1 (1 bit)
CPAS : RA Compare Status (cleared on read)
bits : 2 - 2 (1 bit)
CPBS : RB Compare Status (cleared on read)
bits : 3 - 3 (1 bit)
CPCS : RC Compare Status (cleared on read)
bits : 4 - 4 (1 bit)
LDRAS : RA Loading Status (cleared on read)
bits : 5 - 5 (1 bit)
LDRBS : RB Loading Status (cleared on read)
bits : 6 - 6 (1 bit)
ETRGS : External Trigger Status (cleared on read)
bits : 7 - 7 (1 bit)
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
MTIOA : TIOAx Mirror
bits : 17 - 17 (1 bit)
MTIOB : TIOBx Mirror
bits : 18 - 18 (1 bit)
Status Register (channel = 0)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status (cleared on read)
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun Status (cleared on read)
bits : 1 - 1 (1 bit)
CPAS : RA Compare Status (cleared on read)
bits : 2 - 2 (1 bit)
CPBS : RB Compare Status (cleared on read)
bits : 3 - 3 (1 bit)
CPCS : RC Compare Status (cleared on read)
bits : 4 - 4 (1 bit)
LDRAS : RA Loading Status (cleared on read)
bits : 5 - 5 (1 bit)
LDRBS : RB Loading Status (cleared on read)
bits : 6 - 6 (1 bit)
ETRGS : External Trigger Status (cleared on read)
bits : 7 - 7 (1 bit)
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
MTIOA : TIOAx Mirror
bits : 17 - 17 (1 bit)
MTIOB : TIOBx Mirror
bits : 18 - 18 (1 bit)
Interrupt Enable Register (channel = 0)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Interrupt Enable Register (channel = 0)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Interrupt Disable Register (channel = 0)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Interrupt Disable Register (channel = 0)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Interrupt Mask Register (channel = 0)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Interrupt Mask Register (channel = 0)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Extended Mode Register (channel = 0)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGSRCA : Trigger Source for Input A
bits : 0 - 1 (2 bit)
Enumeration: TRIGSRCASelect
0 : EXTERNAL_TIOAx
The trigger/capture input A is driven by external pin TIOAx
1 : PWMx
The trigger/capture input A is driven internally by PWMx
End of enumeration elements list.
TRIGSRCB : Trigger Source for Input B
bits : 4 - 5 (2 bit)
Enumeration: TRIGSRCBSelect
0 : EXTERNAL_TIOBx
The trigger/capture input B is driven by external pin TIOBx
1 : PWMx
For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC).
End of enumeration elements list.
NODIVCLK : No Divided Clock
bits : 8 - 8 (1 bit)
Extended Mode Register (channel = 0)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGSRCA : Trigger Source for Input A
bits : 0 - 1 (2 bit)
Enumeration: TRIGSRCASelect
0 : EXTERNAL_TIOAx
The trigger/capture input A is driven by external pin TIOAx
1 : PWMx
The trigger/capture input A is driven internally by PWMx
End of enumeration elements list.
TRIGSRCB : Trigger Source for Input B
bits : 4 - 5 (2 bit)
Enumeration: TRIGSRCBSelect
0 : EXTERNAL_TIOBx
The trigger/capture input B is driven by external pin TIOBx
1 : PWMx
For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC).
End of enumeration elements list.
NODIVCLK : No Divided Clock
bits : 8 - 8 (1 bit)
Channel Mode Register (channel = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0 : TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
1 : TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
2 : TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
3 : TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
4 : TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
5 : XC0
Clock selected: XC0
6 : XC1
Clock selected: XC1
7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0 : NONE
The clock is not gated by an external signal.
1 : XC0
XC0 is ANDed with the selected clock.
2 : XC1
XC1 is ANDed with the selected clock.
3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0 : NONE
The clock is not gated by an external signal.
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : EDGE
Each edge
End of enumeration elements list.
ABETRG : TIOAx or TIOBx External Trigger Selection
bits : 10 - 10 (1 bit)
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0 : NONE
None
1 : RISING
Rising edge of TIOAx
2 : FALLING
Falling edge of TIOAx
3 : EDGE
Each edge of TIOAx
End of enumeration elements list.
LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0 : NONE
None
1 : RISING
Rising edge of TIOAx
2 : FALLING
Falling edge of TIOAx
3 : EDGE
Each edge of TIOAx
End of enumeration elements list.
SBSMPLR : Loading Edge Subsampling Ratio
bits : 20 - 22 (3 bit)
Enumeration: SBSMPLRSelect
0 : ONE
Load a Capture Register each selected edge
1 : HALF
Load a Capture Register every 2 selected edges
2 : FOURTH
Load a Capture Register every 4 selected edges
3 : EIGHTH
Load a Capture Register every 8 selected edges
4 : SIXTEENTH
Load a Capture Register every 16 selected edges
End of enumeration elements list.
Channel Mode Register (channel = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TC_CMR_CAPTURE_MODE
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0 : TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
1 : TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
2 : TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
3 : TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
4 : TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
5 : XC0
Clock selected: XC0
6 : XC1
Clock selected: XC1
7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0 : NONE
The clock is not gated by an external signal.
1 : XC0
XC0 is ANDed with the selected clock.
2 : XC1
XC1 is ANDed with the selected clock.
3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
CPCDIS : Counter Clock Disable with RC Loading
bits : 7 - 7 (1 bit)
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: EEVTEDGSelect
0 : NONE
None
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : EDGE
Each edges
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
Enumeration: EEVTSelect
0 : TIOB
TIOB
1 : XC0
XC0
2 : XC1
XC1
3 : XC2
XC2
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
Enumeration: WAVSELSelect
0 : UP
UP mode without automatic trigger on RC Compare
1 : UPDOWN
UPDOWN mode without automatic trigger on RC Compare
2 : UP_RC
UP mode with automatic trigger on RC Compare
3 : UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
ACPA : RA Compare Effect on TIOAx
bits : 16 - 17 (2 bit)
Enumeration: ACPASelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
ACPC : RC Compare Effect on TIOAx
bits : 18 - 19 (2 bit)
Enumeration: ACPCSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
AEEVT : External Event Effect on TIOAx
bits : 20 - 21 (2 bit)
Enumeration: AEEVTSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOAx
bits : 22 - 23 (2 bit)
Enumeration: ASWTRGSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BCPB : RB Compare Effect on TIOBx
bits : 24 - 25 (2 bit)
Enumeration: BCPBSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BCPC : RC Compare Effect on TIOBx
bits : 26 - 27 (2 bit)
Enumeration: BCPCSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BEEVT : External Event Effect on TIOBx
bits : 28 - 29 (2 bit)
Enumeration: BEEVTSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOBx
bits : 30 - 31 (2 bit)
Enumeration: BSWTRGSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
Channel Mode Register (channel = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0x0 : TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
0x1 : TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
0x2 : TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
0x3 : TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
0x4 : TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
0x5 : XC0
Clock selected: XC0
0x6 : XC1
Clock selected: XC1
0x7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0x0 : NONE
The clock is not gated by an external signal.
0x1 : XC0
XC0 is ANDed with the selected clock.
0x2 : XC1
XC1 is ANDed with the selected clock.
0x3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0x0 : NONE
The clock is not gated by an external signal.
0x1 : RISING
Rising edge
0x2 : FALLING
Falling edge
0x3 : EDGE
Each edge
End of enumeration elements list.
ABETRG : TIOAx or TIOBx External Trigger Selection
bits : 10 - 10 (1 bit)
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0x0 : NONE
None
0x1 : RISING
Rising edge of TIOAx
0x2 : FALLING
Falling edge of TIOAx
0x3 : EDGE
Each edge of TIOAx
End of enumeration elements list.
LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0x0 : NONE
None
0x1 : RISING
Rising edge of TIOAx
0x2 : FALLING
Falling edge of TIOAx
0x3 : EDGE
Each edge of TIOAx
End of enumeration elements list.
SBSMPLR : Loading Edge Subsampling Ratio
bits : 20 - 22 (3 bit)
Enumeration: SBSMPLRSelect
0x0 : ONE
Load a Capture Register each selected edge
0x1 : HALF
Load a Capture Register every 2 selected edges
0x2 : FOURTH
Load a Capture Register every 4 selected edges
0x3 : EIGHTH
Load a Capture Register every 8 selected edges
0x4 : SIXTEENTH
Load a Capture Register every 16 selected edges
End of enumeration elements list.
Channel Mode Register (channel = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : CMR_CAPTURE_MODE
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0x0 : TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
0x1 : TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
0x2 : TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
0x3 : TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
0x4 : TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
0x5 : XC0
Clock selected: XC0
0x6 : XC1
Clock selected: XC1
0x7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0x0 : NONE
The clock is not gated by an external signal.
0x1 : XC0
XC0 is ANDed with the selected clock.
0x2 : XC1
XC1 is ANDed with the selected clock.
0x3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
CPCDIS : Counter Clock Disable with RC Loading
bits : 7 - 7 (1 bit)
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: EEVTEDGSelect
0x0 : NONE
None
0x1 : RISING
Rising edge
0x2 : FALLING
Falling edge
0x3 : EDGE
Each edges
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
Enumeration: EEVTSelect
0x0 : TIOB
TIOB
0x1 : XC0
XC0
0x2 : XC1
XC1
0x3 : XC2
XC2
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
Enumeration: WAVSELSelect
0x0 : UP
UP mode without automatic trigger on RC Compare
0x1 : UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x2 : UP_RC
UP mode with automatic trigger on RC Compare
0x3 : UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
ACPA : RA Compare Effect on TIOAx
bits : 16 - 17 (2 bit)
Enumeration: ACPASelect
0x0 : NONE
NONE
0x1 : SET
SET
0x2 : CLEAR
CLEAR
0x3 : TOGGLE
TOGGLE
End of enumeration elements list.
ACPC : RC Compare Effect on TIOAx
bits : 18 - 19 (2 bit)
Enumeration: ACPCSelect
0x0 : NONE
NONE
0x1 : SET
SET
0x2 : CLEAR
CLEAR
0x3 : TOGGLE
TOGGLE
End of enumeration elements list.
AEEVT : External Event Effect on TIOAx
bits : 20 - 21 (2 bit)
Enumeration: AEEVTSelect
0x0 : NONE
NONE
0x1 : SET
SET
0x2 : CLEAR
CLEAR
0x3 : TOGGLE
TOGGLE
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOAx
bits : 22 - 23 (2 bit)
Enumeration: ASWTRGSelect
0x0 : NONE
NONE
0x1 : SET
SET
0x2 : CLEAR
CLEAR
0x3 : TOGGLE
TOGGLE
End of enumeration elements list.
BCPB : RB Compare Effect on TIOBx
bits : 24 - 25 (2 bit)
Enumeration: BCPBSelect
0x0 : NONE
NONE
0x1 : SET
SET
0x2 : CLEAR
CLEAR
0x3 : TOGGLE
TOGGLE
End of enumeration elements list.
BCPC : RC Compare Effect on TIOBx
bits : 26 - 27 (2 bit)
Enumeration: BCPCSelect
0x0 : NONE
NONE
0x1 : SET
SET
0x2 : CLEAR
CLEAR
0x3 : TOGGLE
TOGGLE
End of enumeration elements list.
BEEVT : External Event Effect on TIOBx
bits : 28 - 29 (2 bit)
Enumeration: BEEVTSelect
0x0 : NONE
NONE
0x1 : SET
SET
0x2 : CLEAR
CLEAR
0x3 : TOGGLE
TOGGLE
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOBx
bits : 30 - 31 (2 bit)
Enumeration: BSWTRGSelect
0x0 : NONE
NONE
0x1 : SET
SET
0x2 : CLEAR
CLEAR
0x3 : TOGGLE
TOGGLE
End of enumeration elements list.
Channel Control Register (channel = 0)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Channel Mode Register (channel = 0)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0 : TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
1 : TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
2 : TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
3 : TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
4 : TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
5 : XC0
Clock selected: XC0
6 : XC1
Clock selected: XC1
7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0 : NONE
The clock is not gated by an external signal.
1 : XC0
XC0 is ANDed with the selected clock.
2 : XC1
XC1 is ANDed with the selected clock.
3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0 : NONE
The clock is not gated by an external signal.
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : EDGE
Each edge
End of enumeration elements list.
ABETRG : TIOAx or TIOBx External Trigger Selection
bits : 10 - 10 (1 bit)
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0 : NONE
None
1 : RISING
Rising edge of TIOAx
2 : FALLING
Falling edge of TIOAx
3 : EDGE
Each edge of TIOAx
End of enumeration elements list.
LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0 : NONE
None
1 : RISING
Rising edge of TIOAx
2 : FALLING
Falling edge of TIOAx
3 : EDGE
Each edge of TIOAx
End of enumeration elements list.
SBSMPLR : Loading Edge Subsampling Ratio
bits : 20 - 22 (3 bit)
Enumeration: SBSMPLRSelect
0 : ONE
Load a Capture Register each selected edge
1 : HALF
Load a Capture Register every 2 selected edges
2 : FOURTH
Load a Capture Register every 4 selected edges
3 : EIGHTH
Load a Capture Register every 8 selected edges
4 : SIXTEENTH
Load a Capture Register every 16 selected edges
End of enumeration elements list.
Channel Mode Register (channel = 0)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TC_CMR_CAPTURE_MODE
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0 : TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
1 : TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
2 : TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
3 : TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
4 : TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
5 : XC0
Clock selected: XC0
6 : XC1
Clock selected: XC1
7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0 : NONE
The clock is not gated by an external signal.
1 : XC0
XC0 is ANDed with the selected clock.
2 : XC1
XC1 is ANDed with the selected clock.
3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
CPCDIS : Counter Clock Disable with RC Loading
bits : 7 - 7 (1 bit)
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: EEVTEDGSelect
0 : NONE
None
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : EDGE
Each edges
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
Enumeration: EEVTSelect
0 : TIOB
TIOB
1 : XC0
XC0
2 : XC1
XC1
3 : XC2
XC2
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
Enumeration: WAVSELSelect
0 : UP
UP mode without automatic trigger on RC Compare
1 : UPDOWN
UPDOWN mode without automatic trigger on RC Compare
2 : UP_RC
UP mode with automatic trigger on RC Compare
3 : UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
ACPA : RA Compare Effect on TIOAx
bits : 16 - 17 (2 bit)
Enumeration: ACPASelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
ACPC : RC Compare Effect on TIOAx
bits : 18 - 19 (2 bit)
Enumeration: ACPCSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
AEEVT : External Event Effect on TIOAx
bits : 20 - 21 (2 bit)
Enumeration: AEEVTSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOAx
bits : 22 - 23 (2 bit)
Enumeration: ASWTRGSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BCPB : RB Compare Effect on TIOBx
bits : 24 - 25 (2 bit)
Enumeration: BCPBSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BCPC : RC Compare Effect on TIOBx
bits : 26 - 27 (2 bit)
Enumeration: BCPCSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BEEVT : External Event Effect on TIOBx
bits : 28 - 29 (2 bit)
Enumeration: BEEVTSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOBx
bits : 30 - 31 (2 bit)
Enumeration: BSWTRGSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
Stepper Motor Mode Register (channel = 0)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Register AB (channel = 0)
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAB : Register A or Register B
bits : 0 - 31 (32 bit)
Counter Value (channel = 0)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 31 (32 bit)
Register A (channel = 0)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 31 (32 bit)
Register B (channel = 0)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 31 (32 bit)
Register C (channel = 0)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 31 (32 bit)
Status Register (channel = 0)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status (cleared on read)
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun Status (cleared on read)
bits : 1 - 1 (1 bit)
CPAS : RA Compare Status (cleared on read)
bits : 2 - 2 (1 bit)
CPBS : RB Compare Status (cleared on read)
bits : 3 - 3 (1 bit)
CPCS : RC Compare Status (cleared on read)
bits : 4 - 4 (1 bit)
LDRAS : RA Loading Status (cleared on read)
bits : 5 - 5 (1 bit)
LDRBS : RB Loading Status (cleared on read)
bits : 6 - 6 (1 bit)
ETRGS : External Trigger Status (cleared on read)
bits : 7 - 7 (1 bit)
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
MTIOA : TIOAx Mirror
bits : 17 - 17 (1 bit)
MTIOB : TIOBx Mirror
bits : 18 - 18 (1 bit)
Interrupt Enable Register (channel = 0)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Interrupt Disable Register (channel = 0)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Interrupt Mask Register (channel = 0)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Extended Mode Register (channel = 0)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGSRCA : Trigger Source for Input A
bits : 0 - 1 (2 bit)
Enumeration: TRIGSRCASelect
0 : EXTERNAL_TIOAx
The trigger/capture input A is driven by external pin TIOAx
1 : PWMx
The trigger/capture input A is driven internally by PWMx
End of enumeration elements list.
TRIGSRCB : Trigger Source for Input B
bits : 4 - 5 (2 bit)
Enumeration: TRIGSRCBSelect
0 : EXTERNAL_TIOBx
The trigger/capture input B is driven by external pin TIOBx
1 : PWMx
For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC).
End of enumeration elements list.
NODIVCLK : No Divided Clock
bits : 8 - 8 (1 bit)
Stepper Motor Mode Register (channel = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Stepper Motor Mode Register (channel = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
Register AB (channel = 0)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAB : Register A or Register B
bits : 0 - 31 (32 bit)
Register AB (channel = 0)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAB : Register A or Register B
bits : 0 - 31 (32 bit)
Channel Control Register (channel = 0)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
Block Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNC : Synchro Command
bits : 0 - 0 (1 bit)
Block Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNC : Synchro Command
bits : 0 - 0 (1 bit)
Channel Mode Register (channel = 0)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0 : TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
1 : TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
2 : TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
3 : TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
4 : TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
5 : XC0
Clock selected: XC0
6 : XC1
Clock selected: XC1
7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0 : NONE
The clock is not gated by an external signal.
1 : XC0
XC0 is ANDed with the selected clock.
2 : XC1
XC1 is ANDed with the selected clock.
3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: ETRGEDGSelect
0 : NONE
The clock is not gated by an external signal.
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : EDGE
Each edge
End of enumeration elements list.
ABETRG : TIOAx or TIOBx External Trigger Selection
bits : 10 - 10 (1 bit)
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
Enumeration: LDRASelect
0 : NONE
None
1 : RISING
Rising edge of TIOAx
2 : FALLING
Falling edge of TIOAx
3 : EDGE
Each edge of TIOAx
End of enumeration elements list.
LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
Enumeration: LDRBSelect
0 : NONE
None
1 : RISING
Rising edge of TIOAx
2 : FALLING
Falling edge of TIOAx
3 : EDGE
Each edge of TIOAx
End of enumeration elements list.
SBSMPLR : Loading Edge Subsampling Ratio
bits : 20 - 22 (3 bit)
Enumeration: SBSMPLRSelect
0 : ONE
Load a Capture Register each selected edge
1 : HALF
Load a Capture Register every 2 selected edges
2 : FOURTH
Load a Capture Register every 4 selected edges
3 : EIGHTH
Load a Capture Register every 8 selected edges
4 : SIXTEENTH
Load a Capture Register every 16 selected edges
End of enumeration elements list.
Channel Mode Register (channel = 0)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : TC_CMR_CAPTURE_MODE
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
Enumeration: TCCLKSSelect
0 : TIMER_CLOCK1
Clock selected: internal PCK6 clock signal (from PMC)
1 : TIMER_CLOCK2
Clock selected: internal MCK/8 clock signal (from PMC)
2 : TIMER_CLOCK3
Clock selected: internal MCK/32 clock signal (from PMC)
3 : TIMER_CLOCK4
Clock selected: internal MCK/128 clock signal (from PMC)
4 : TIMER_CLOCK5
Clock selected: internal SLCK clock signal (from PMC)
5 : XC0
Clock selected: XC0
6 : XC1
Clock selected: XC1
7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
Enumeration: BURSTSelect
0 : NONE
The clock is not gated by an external signal.
1 : XC0
XC0 is ANDed with the selected clock.
2 : XC1
XC1 is ANDed with the selected clock.
3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
CPCDIS : Counter Clock Disable with RC Loading
bits : 7 - 7 (1 bit)
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
Enumeration: EEVTEDGSelect
0 : NONE
None
1 : RISING
Rising edge
2 : FALLING
Falling edge
3 : EDGE
Each edges
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
Enumeration: EEVTSelect
0 : TIOB
TIOB
1 : XC0
XC0
2 : XC1
XC1
3 : XC2
XC2
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
Enumeration: WAVSELSelect
0 : UP
UP mode without automatic trigger on RC Compare
1 : UPDOWN
UPDOWN mode without automatic trigger on RC Compare
2 : UP_RC
UP mode with automatic trigger on RC Compare
3 : UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
ACPA : RA Compare Effect on TIOAx
bits : 16 - 17 (2 bit)
Enumeration: ACPASelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
ACPC : RC Compare Effect on TIOAx
bits : 18 - 19 (2 bit)
Enumeration: ACPCSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
AEEVT : External Event Effect on TIOAx
bits : 20 - 21 (2 bit)
Enumeration: AEEVTSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOAx
bits : 22 - 23 (2 bit)
Enumeration: ASWTRGSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BCPB : RB Compare Effect on TIOBx
bits : 24 - 25 (2 bit)
Enumeration: BCPBSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BCPC : RC Compare Effect on TIOBx
bits : 26 - 27 (2 bit)
Enumeration: BCPCSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BEEVT : External Event Effect on TIOBx
bits : 28 - 29 (2 bit)
Enumeration: BEEVTSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOBx
bits : 30 - 31 (2 bit)
Enumeration: BSWTRGSelect
0 : NONE
NONE
1 : SET
SET
2 : CLEAR
CLEAR
3 : TOGGLE
TOGGLE
End of enumeration elements list.
Block Mode Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC0XC0S : External Clock Signal 0 Selection
bits : 0 - 1 (2 bit)
Enumeration: TC0XC0SSelect
0 : TCLK0
Signal connected to XC0: TCLK0
2 : TIOA1
Signal connected to XC0: TIOA1
3 : TIOA2
Signal connected to XC0: TIOA2
End of enumeration elements list.
TC1XC1S : External Clock Signal 1 Selection
bits : 2 - 3 (2 bit)
Enumeration: TC1XC1SSelect
0 : TCLK1
Signal connected to XC1: TCLK1
2 : TIOA0
Signal connected to XC1: TIOA0
3 : TIOA2
Signal connected to XC1: TIOA2
End of enumeration elements list.
TC2XC2S : External Clock Signal 2 Selection
bits : 4 - 5 (2 bit)
Enumeration: TC2XC2SSelect
0 : TCLK2
Signal connected to XC2: TCLK2
2 : TIOA0
Signal connected to XC2: TIOA0
3 : TIOA1
Signal connected to XC2: TIOA1
End of enumeration elements list.
QDEN : Quadrature Decoder Enabled
bits : 8 - 8 (1 bit)
POSEN : Position Enabled
bits : 9 - 9 (1 bit)
SPEEDEN : Speed Enabled
bits : 10 - 10 (1 bit)
QDTRANS : Quadrature Decoding Transparent
bits : 11 - 11 (1 bit)
EDGPHA : Edge on PHA Count Mode
bits : 12 - 12 (1 bit)
INVA : Inverted PHA
bits : 13 - 13 (1 bit)
INVB : Inverted PHB
bits : 14 - 14 (1 bit)
INVIDX : Inverted Index
bits : 15 - 15 (1 bit)
SWAP : Swap PHA and PHB
bits : 16 - 16 (1 bit)
IDXPHB : Index Pin is PHB Pin
bits : 17 - 17 (1 bit)
AUTOC : AutoCorrection of missing pulses
bits : 18 - 18 (1 bit)
MAXFILT : Maximum Filter
bits : 20 - 25 (6 bit)
MAXCMP : Maximum Consecutive Missing Pulses
bits : 26 - 29 (4 bit)
Block Mode Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC0XC0S : External Clock Signal 0 Selection
bits : 0 - 1 (2 bit)
Enumeration: TC0XC0SSelect
0x0 : TCLK0
Signal connected to XC0: TCLK0
0x2 : TIOA1
Signal connected to XC0: TIOA1
0x3 : TIOA2
Signal connected to XC0: TIOA2
End of enumeration elements list.
TC1XC1S : External Clock Signal 1 Selection
bits : 2 - 3 (2 bit)
Enumeration: TC1XC1SSelect
0x0 : TCLK1
Signal connected to XC1: TCLK1
0x2 : TIOA0
Signal connected to XC1: TIOA0
0x3 : TIOA2
Signal connected to XC1: TIOA2
End of enumeration elements list.
TC2XC2S : External Clock Signal 2 Selection
bits : 4 - 5 (2 bit)
Enumeration: TC2XC2SSelect
0x0 : TCLK2
Signal connected to XC2: TCLK2
0x2 : TIOA0
Signal connected to XC2: TIOA0
0x3 : TIOA1
Signal connected to XC2: TIOA1
End of enumeration elements list.
QDEN : Quadrature Decoder Enabled
bits : 8 - 8 (1 bit)
POSEN : Position Enabled
bits : 9 - 9 (1 bit)
SPEEDEN : Speed Enabled
bits : 10 - 10 (1 bit)
QDTRANS : Quadrature Decoding Transparent
bits : 11 - 11 (1 bit)
EDGPHA : Edge on PHA Count Mode
bits : 12 - 12 (1 bit)
INVA : Inverted PHA
bits : 13 - 13 (1 bit)
INVB : Inverted PHB
bits : 14 - 14 (1 bit)
INVIDX : Inverted Index
bits : 15 - 15 (1 bit)
SWAP : Swap PHA and PHB
bits : 16 - 16 (1 bit)
IDXPHB : Index Pin is PHB Pin
bits : 17 - 17 (1 bit)
AUTOC : AutoCorrection of missing pulses
bits : 18 - 18 (1 bit)
MAXFILT : Maximum Filter
bits : 20 - 25 (6 bit)
MAXCMP : Maximum Consecutive Missing Pulses
bits : 26 - 29 (4 bit)
Stepper Motor Mode Register (channel = 0)
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
DOWN : Down Count
bits : 1 - 1 (1 bit)
QDEC Interrupt Enable Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDX : Index
bits : 0 - 0 (1 bit)
DIRCHG : Direction Change
bits : 1 - 1 (1 bit)
QERR : Quadrature Error
bits : 2 - 2 (1 bit)
MPE : Consecutive Missing Pulse Error
bits : 3 - 3 (1 bit)
QDEC Interrupt Enable Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDX : Index
bits : 0 - 0 (1 bit)
DIRCHG : Direction Change
bits : 1 - 1 (1 bit)
QERR : Quadrature Error
bits : 2 - 2 (1 bit)
MPE : Consecutive Missing Pulse Error
bits : 3 - 3 (1 bit)
Register AB (channel = 0)
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAB : Register A or Register B
bits : 0 - 31 (32 bit)
QDEC Interrupt Disable Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDX : Index
bits : 0 - 0 (1 bit)
DIRCHG : Direction Change
bits : 1 - 1 (1 bit)
QERR : Quadrature Error
bits : 2 - 2 (1 bit)
MPE : Consecutive Missing Pulse Error
bits : 3 - 3 (1 bit)
QDEC Interrupt Disable Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDX : Index
bits : 0 - 0 (1 bit)
DIRCHG : Direction Change
bits : 1 - 1 (1 bit)
QERR : Quadrature Error
bits : 2 - 2 (1 bit)
MPE : Consecutive Missing Pulse Error
bits : 3 - 3 (1 bit)
Counter Value (channel = 0)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 31 (32 bit)
QDEC Interrupt Mask Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDX : Index
bits : 0 - 0 (1 bit)
DIRCHG : Direction Change
bits : 1 - 1 (1 bit)
QERR : Quadrature Error
bits : 2 - 2 (1 bit)
MPE : Consecutive Missing Pulse Error
bits : 3 - 3 (1 bit)
QDEC Interrupt Mask Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDX : Index
bits : 0 - 0 (1 bit)
DIRCHG : Direction Change
bits : 1 - 1 (1 bit)
QERR : Quadrature Error
bits : 2 - 2 (1 bit)
MPE : Consecutive Missing Pulse Error
bits : 3 - 3 (1 bit)
Register A (channel = 0)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 31 (32 bit)
QDEC Interrupt Status Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDX : Index
bits : 0 - 0 (1 bit)
DIRCHG : Direction Change
bits : 1 - 1 (1 bit)
QERR : Quadrature Error
bits : 2 - 2 (1 bit)
MPE : Consecutive Missing Pulse Error
bits : 3 - 3 (1 bit)
DIR : Direction
bits : 8 - 8 (1 bit)
QDEC Interrupt Status Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDX : Index
bits : 0 - 0 (1 bit)
DIRCHG : Direction Change
bits : 1 - 1 (1 bit)
QERR : Quadrature Error
bits : 2 - 2 (1 bit)
MPE : Consecutive Missing Pulse Error
bits : 3 - 3 (1 bit)
DIR : Direction
bits : 8 - 8 (1 bit)
Register B (channel = 0)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 31 (32 bit)
Fault Mode Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENCF0 : Enable Compare Fault Channel 0
bits : 0 - 0 (1 bit)
ENCF1 : Enable Compare Fault Channel 1
bits : 1 - 1 (1 bit)
Fault Mode Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENCF0 : Enable Compare Fault Channel 0
bits : 0 - 0 (1 bit)
ENCF1 : Enable Compare Fault Channel 1
bits : 1 - 1 (1 bit)
Register C (channel = 0)
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 31 (32 bit)
Status Register (channel = 0)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status (cleared on read)
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun Status (cleared on read)
bits : 1 - 1 (1 bit)
CPAS : RA Compare Status (cleared on read)
bits : 2 - 2 (1 bit)
CPBS : RB Compare Status (cleared on read)
bits : 3 - 3 (1 bit)
CPCS : RC Compare Status (cleared on read)
bits : 4 - 4 (1 bit)
LDRAS : RA Loading Status (cleared on read)
bits : 5 - 5 (1 bit)
LDRBS : RB Loading Status (cleared on read)
bits : 6 - 6 (1 bit)
ETRGS : External Trigger Status (cleared on read)
bits : 7 - 7 (1 bit)
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
MTIOA : TIOAx Mirror
bits : 17 - 17 (1 bit)
MTIOB : TIOBx Mirror
bits : 18 - 18 (1 bit)
Interrupt Enable Register (channel = 0)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
5523789 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x54494D : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Interrupt Disable Register (channel = 0)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Interrupt Mask Register (channel = 0)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
CPAS : RA Compare
bits : 2 - 2 (1 bit)
CPBS : RB Compare
bits : 3 - 3 (1 bit)
CPCS : RC Compare
bits : 4 - 4 (1 bit)
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
Extended Mode Register (channel = 0)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGSRCA : Trigger Source for Input A
bits : 0 - 1 (2 bit)
Enumeration: TRIGSRCASelect
0 : EXTERNAL_TIOAx
The trigger/capture input A is driven by external pin TIOAx
1 : PWMx
The trigger/capture input A is driven internally by PWMx
End of enumeration elements list.
TRIGSRCB : Trigger Source for Input B
bits : 4 - 5 (2 bit)
Enumeration: TRIGSRCBSelect
0 : EXTERNAL_TIOBx
The trigger/capture input B is driven by external pin TIOBx
1 : PWMx
For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC).
End of enumeration elements list.
NODIVCLK : No Divided Clock
bits : 8 - 8 (1 bit)
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