\n

ACC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

IER

IDR

IMR

ISR

MR

ACR

WPMR

WPSR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST

SWRST : Software Reset
bits : 0 - 0 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE

CE : Comparison Edge
bits : 0 - 0 (1 bit)


IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE

CE : Comparison Edge
bits : 0 - 0 (1 bit)


IMR

Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE

CE : Comparison Edge
bits : 0 - 0 (1 bit)


ISR

Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CE SCO MASK

CE : Comparison Edge (cleared on read)
bits : 0 - 0 (1 bit)

SCO : Synchronized Comparator Output
bits : 1 - 1 (1 bit)

MASK : Flag Mask
bits : 31 - 31 (1 bit)


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SELMINUS SELPLUS ACEN EDGETYP INV SELFS FE

SELMINUS : Selection for Minus Comparator Input
bits : 0 - 2 (3 bit)

Enumeration: SELMINUSSelect

0 : TS

Select TS

1 : VREFP

Select VREFP

2 : DAC0

Select DAC0

3 : DAC1

Select DAC1

4 : AFE0_AD0

Select AFE0_AD0

5 : AFE0_AD1

Select AFE0_AD1

6 : AFE0_AD2

Select AFE0_AD2

7 : AFE0_AD3

Select AFE0_AD3

End of enumeration elements list.

SELPLUS : Selection For Plus Comparator Input
bits : 4 - 6 (3 bit)

Enumeration: SELPLUSSelect

0 : AFE0_AD0

Select AFE0_AD0

1 : AFE0_AD1

Select AFE0_AD1

2 : AFE0_AD2

Select AFE0_AD2

3 : AFE0_AD3

Select AFE0_AD3

4 : AFE0_AD4

Select AFE0_AD4

5 : AFE0_AD5

Select AFE0_AD5

6 : AFE1_AD0

Select AFE1_AD0

7 : AFE1_AD1

Select AFE1_AD1

End of enumeration elements list.

ACEN : Analog Comparator Enable
bits : 8 - 8 (1 bit)

Enumeration: ACENSelect

0 : DIS

Analog comparator disabled.

1 : EN

Analog comparator enabled.

End of enumeration elements list.

EDGETYP : Edge Type
bits : 9 - 10 (2 bit)

Enumeration: EDGETYPSelect

0 : RISING

Only rising edge of comparator output

1 : FALLING

Falling edge of comparator output

2 : ANY

Any edge of comparator output

End of enumeration elements list.

INV : Invert Comparator Output
bits : 12 - 12 (1 bit)

Enumeration: INVSelect

0 : DIS

Analog comparator output is directly processed.

1 : EN

Analog comparator output is inverted prior to being processed.

End of enumeration elements list.

SELFS : Selection Of Fault Source
bits : 13 - 13 (1 bit)

Enumeration: SELFSSelect

0 : CE

The CE flag is used to drive the FAULT output.

1 : OUTPUT

The output of the analog comparator flag is used to drive the FAULT output.

End of enumeration elements list.

FE : Fault Enable
bits : 14 - 14 (1 bit)

Enumeration: FESelect

0 : DIS

The FAULT output is tied to 0.

1 : EN

The FAULT output is driven by the signal defined by SELFS.

End of enumeration elements list.


ACR

Analog Control Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACR ACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISEL HYST

ISEL : Current Selection
bits : 0 - 0 (1 bit)

Enumeration: ISELSelect

0 : LOPW

Low-power option.

1 : HISP

High-speed option.

End of enumeration elements list.

HYST : Hysteresis Selection
bits : 1 - 2 (2 bit)


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)

Enumeration: WPKEYSelect

4277059 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)



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