\n
address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start Processing
bits : 0 - 0 (1 bit)
SWRST : Software Reset
bits : 8 - 8 (1 bit)
LOADSEED : Random Number Generator Seed Loading
bits : 16 - 16 (1 bit)
Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Enable
bits : 0 - 0 (1 bit)
URAD : Unspecified Register Access Detection Interrupt Enable
bits : 8 - 8 (1 bit)
TAGRDY : GCM Tag Ready Interrupt Enable
bits : 16 - 16 (1 bit)
Input Data Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
GCM Authentication Tag Word Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Initialization Vector Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
GCM H Word Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H Word x
bits : 0 - 31 (32 bit)
Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Disable
bits : 0 - 0 (1 bit)
URAD : Unspecified Register Access Detection Interrupt Disable
bits : 8 - 8 (1 bit)
TAGRDY : GCM Tag Ready Interrupt Disable
bits : 16 - 16 (1 bit)
Output Data Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Input Data Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
GCM Intermediate Hash Word Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Mask
bits : 0 - 0 (1 bit)
URAD : Unspecified Register Access Detection Interrupt Mask
bits : 8 - 8 (1 bit)
TAGRDY : GCM Tag Ready Interrupt Mask
bits : 16 - 16 (1 bit)
Initialization Vector Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
GCM Authentication Tag Word Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
Output Data Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)
bits : 0 - 0 (1 bit)
URAD : Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)
bits : 8 - 8 (1 bit)
URAT : Unspecified Register Access (cleared by writing SWRST in AES_CR)
bits : 12 - 15 (4 bit)
Enumeration: URATSelect
0 : IDR_WR_PROCESSING
Input Data Register written during the data processing when SMOD = 0x2 mode.
1 : ODR_RD_PROCESSING
Output Data Register read during the data processing.
2 : MR_WR_PROCESSING
Mode Register written during the data processing.
3 : ODR_RD_SUBKGEN
Output Data Register read during the sub-keys generation.
4 : MR_WR_SUBKGEN
Mode Register written during the sub-keys generation.
5 : WOR_RD_ACCESS
Write-only register read access.
End of enumeration elements list.
TAGRDY : GCM Tag Ready
bits : 16 - 16 (1 bit)
GCM H Word Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H Word x
bits : 0 - 31 (32 bit)
GCM Intermediate Hash Word Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
Initialization Vector Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
GCM Authentication Tag Word Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
GCM Intermediate Hash Word Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
GCM H Word Register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H Word x
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
GCM Authentication Tag Word Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
GCM H Word Register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H Word x
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIPHER : Processing Mode
bits : 0 - 0 (1 bit)
GTAGEN : GCM Automatic Tag Generation Enable
bits : 1 - 1 (1 bit)
DUALBUFF : Dual Input Buffer
bits : 3 - 3 (1 bit)
Enumeration: DUALBUFFSelect
0 : INACTIVE
AES_IDATARx cannot be written during processing of previous block.
1 : ACTIVE
AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files.
End of enumeration elements list.
PROCDLY : Processing Delay
bits : 4 - 7 (4 bit)
SMOD : Start Mode
bits : 8 - 9 (2 bit)
Enumeration: SMODSelect
0 : MANUAL_START
Manual Mode
1 : AUTO_START
Auto Mode
2 : IDATAR0_START
AES_IDATAR0 access only Auto Mode (DMA)
End of enumeration elements list.
KEYSIZE : Key Size
bits : 10 - 11 (2 bit)
Enumeration: KEYSIZESelect
0 : AES128
AES Key Size is 128 bits
1 : AES192
AES Key Size is 192 bits
2 : AES256
AES Key Size is 256 bits
End of enumeration elements list.
OPMOD : Operating Mode
bits : 12 - 14 (3 bit)
Enumeration: OPMODSelect
0 : ECB
ECB: Electronic Code Book mode
1 : CBC
CBC: Cipher Block Chaining mode
2 : OFB
OFB: Output Feedback mode
3 : CFB
CFB: Cipher Feedback mode
4 : CTR
CTR: Counter mode (16-bit internal counter)
5 : GCM
GCM: Galois/Counter mode
End of enumeration elements list.
LOD : Last Output Data Mode
bits : 15 - 15 (1 bit)
CFBS : Cipher Feedback Data Size
bits : 16 - 18 (3 bit)
Enumeration: CFBSSelect
0 : SIZE_128BIT
128-bit
1 : SIZE_64BIT
64-bit
2 : SIZE_32BIT
32-bit
3 : SIZE_16BIT
16-bit
4 : SIZE_8BIT
8-bit
End of enumeration elements list.
CKEY : Countermeasure Key
bits : 20 - 23 (4 bit)
Enumeration: CKEYSelect
14 : PASSWD
This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0.
End of enumeration elements list.
Key Word Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Input Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
Input Data Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
Input Data Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
Input Data Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
Output Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
Output Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
Output Data Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
Output Data Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
Initialization Vector Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Initialization Vector Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
Initialization Vector Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
Initialization Vector Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
Additional Authenticated Data Length Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AADLEN : Additional Authenticated Data Length
bits : 0 - 31 (32 bit)
Plaintext/Ciphertext Length Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLEN : Plaintext/Ciphertext Length
bits : 0 - 31 (32 bit)
GCM Intermediate Hash Word Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
GCM Intermediate Hash Word Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
Input Data Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
GCM Intermediate Hash Word Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
GCM Intermediate Hash Word Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
GCM Authentication Tag Word Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
GCM Authentication Tag Word Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
GCM Authentication Tag Word Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
GCM Authentication Tag Word Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
GCM Encryption Counter Value Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTR : GCM Encryption Counter
bits : 0 - 31 (32 bit)
GCM H Word Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H Word x
bits : 0 - 31 (32 bit)
Output Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
GCM H Word Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H Word x
bits : 0 - 31 (32 bit)
GCM H Word Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H Word x
bits : 0 - 31 (32 bit)
GCM H Word Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H Word x
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
Initialization Vector Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
Input Data Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
Key Word Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
GCM Intermediate Hash Word Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
Output Data Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
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