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TWIHS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TWIHS_TWIHS_CR

CR

TWIHS_TWIHS_CWGR

CWGR

TWIHS_TWIHS_SR

SR

TWIHS_TWIHS_IER

IER

TWIHS_TWIHS_IDR

IDR

TWIHS_TWIHS_IMR

IMR

TWIHS_TWIHS_RHR

RHR

TWIHS_TWIHS_THR

THR

TWIHS_TWIHS_SMBTR

SMBTR

TWIHS_TWIHS_MMR

MMR

TWIHS_TWIHS_FILTR

FILTR

TWIHS_TWIHS_SWMR

SWMR

TWIHS_TWIHS_SMR

SMR

TWIHS_TWIHS_IADR

IADR

TWIHS_TWIHS_WPMR

WPMR

TWIHS_TWIHS_WPSR

WPSR


TWIHS_TWIHS_CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_CR TWIHS_TWIHS_CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP MSEN MSDIS SVEN SVDIS QUICK SWRST HSEN HSDIS SMBEN SMBDIS PECEN PECDIS PECRQ CLEAR ACMEN ACMDIS THRCLR LOCKCLR FIFOEN FIFODIS

START : Send a START Condition
bits : 0 - 0 (1 bit)

STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)

MSEN : TWIHS Master Mode Enabled
bits : 2 - 2 (1 bit)

MSDIS : TWIHS Master Mode Disabled
bits : 3 - 3 (1 bit)

SVEN : TWIHS Slave Mode Enabled
bits : 4 - 4 (1 bit)

SVDIS : TWIHS Slave Mode Disabled
bits : 5 - 5 (1 bit)

QUICK : SMBus Quick Command
bits : 6 - 6 (1 bit)

SWRST : Software Reset
bits : 7 - 7 (1 bit)

HSEN : TWIHS High-Speed Mode Enabled
bits : 8 - 8 (1 bit)

HSDIS : TWIHS High-Speed Mode Disabled
bits : 9 - 9 (1 bit)

SMBEN : SMBus Mode Enabled
bits : 10 - 10 (1 bit)

SMBDIS : SMBus Mode Disabled
bits : 11 - 11 (1 bit)

PECEN : Packet Error Checking Enable
bits : 12 - 12 (1 bit)

PECDIS : Packet Error Checking Disable
bits : 13 - 13 (1 bit)

PECRQ : PEC Request
bits : 14 - 14 (1 bit)

CLEAR : Bus CLEAR Command
bits : 15 - 15 (1 bit)

ACMEN : Alternative Command Mode Enable
bits : 16 - 16 (1 bit)

ACMDIS : Alternative Command Mode Disable
bits : 17 - 17 (1 bit)

THRCLR : Transmit Holding Register Clear
bits : 24 - 24 (1 bit)

LOCKCLR : Lock Clear
bits : 26 - 26 (1 bit)

FIFOEN : FIFO Enable
bits : 28 - 28 (1 bit)

FIFODIS : FIFO Disable
bits : 29 - 29 (1 bit)


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP MSEN MSDIS SVEN SVDIS QUICK SWRST HSEN HSDIS SMBEN SMBDIS PECEN PECDIS PECRQ CLEAR

START : Send a START Condition
bits : 0 - 0 (1 bit)
access : write-only

STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)
access : write-only

MSEN : TWIHS Master Mode Enabled
bits : 2 - 2 (1 bit)
access : write-only

MSDIS : TWIHS Master Mode Disabled
bits : 3 - 3 (1 bit)
access : write-only

SVEN : TWIHS Slave Mode Enabled
bits : 4 - 4 (1 bit)
access : write-only

SVDIS : TWIHS Slave Mode Disabled
bits : 5 - 5 (1 bit)
access : write-only

QUICK : SMBus Quick Command
bits : 6 - 6 (1 bit)
access : write-only

SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only

HSEN : TWIHS High-Speed Mode Enabled
bits : 8 - 8 (1 bit)
access : write-only

HSDIS : TWIHS High-Speed Mode Disabled
bits : 9 - 9 (1 bit)
access : write-only

SMBEN : SMBus Mode Enabled
bits : 10 - 10 (1 bit)
access : write-only

SMBDIS : SMBus Mode Disabled
bits : 11 - 11 (1 bit)
access : write-only

PECEN : Packet Error Checking Enable
bits : 12 - 12 (1 bit)
access : write-only

PECDIS : Packet Error Checking Disable
bits : 13 - 13 (1 bit)
access : write-only

PECRQ : PEC Request
bits : 14 - 14 (1 bit)
access : write-only

CLEAR : Bus CLEAR Command
bits : 15 - 15 (1 bit)
access : write-only


TWIHS_TWIHS_CWGR

Clock Waveform Generator Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_CWGR TWIHS_TWIHS_CWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLDIV CHDIV CKDIV HOLD

CLDIV : Clock Low Divider
bits : 0 - 7 (8 bit)

CHDIV : Clock High Divider
bits : 8 - 15 (8 bit)

CKDIV : Clock Divider
bits : 16 - 18 (3 bit)

HOLD : TWD Hold Time Versus TWCK Falling
bits : 24 - 29 (6 bit)


CWGR

Clock Waveform Generator Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CWGR CWGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLDIV CHDIV CKDIV HOLD

CLDIV : Clock Low Divider
bits : 0 - 7 (8 bit)
access : read-write

CHDIV : Clock High Divider
bits : 8 - 15 (8 bit)
access : read-write

CKDIV : Clock Divider
bits : 16 - 18 (3 bit)
access : read-write

HOLD : TWD Hold Time Versus TWCK Falling
bits : 24 - 28 (5 bit)
access : read-write


TWIHS_TWIHS_SR

Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_SR TWIHS_TWIHS_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVREAD SVACC GACC OVRE UNRE NACK ARBLST SCLWS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM SCL SDA

TXCOMP : Transmission Completed (cleared by writing TWIHS_THR)
bits : 0 - 0 (1 bit)

RXRDY : Receive Holding Register Ready (cleared by reading TWIHS_RHR)
bits : 1 - 1 (1 bit)

TXRDY : Transmit Holding Register Ready (cleared by writing TWIHS_THR)
bits : 2 - 2 (1 bit)

SVREAD : Slave Read
bits : 3 - 3 (1 bit)

SVACC : Slave Access
bits : 4 - 4 (1 bit)

GACC : General Call Access (cleared on read)
bits : 5 - 5 (1 bit)

OVRE : Overrun Error (cleared on read)
bits : 6 - 6 (1 bit)

UNRE : Underrun Error (cleared on read)
bits : 7 - 7 (1 bit)

NACK : Not Acknowledged (cleared on read)
bits : 8 - 8 (1 bit)

ARBLST : Arbitration Lost (cleared on read)
bits : 9 - 9 (1 bit)

SCLWS : Clock Wait State
bits : 10 - 10 (1 bit)

EOSACC : End Of Slave Access (cleared on read)
bits : 11 - 11 (1 bit)

MCACK : Master Code Acknowledge (cleared on read)
bits : 16 - 16 (1 bit)

TOUT : Timeout Error (cleared on read)
bits : 18 - 18 (1 bit)

PECERR : PEC Error (cleared on read)
bits : 19 - 19 (1 bit)

SMBDAM : SMBus Default Address Match (cleared on read)
bits : 20 - 20 (1 bit)

SMBHHM : SMBus Host Header Address Match (cleared on read)
bits : 21 - 21 (1 bit)

SCL : SCL Line Value
bits : 24 - 24 (1 bit)

SDA : SDA Line Value
bits : 25 - 25 (1 bit)


SR

Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVREAD SVACC GACC OVRE UNRE NACK ARBLST SCLWS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM SCL SDA

TXCOMP : Transmission Completed (cleared by writing TWIHS_THR)
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready (cleared by reading TWIHS_RHR)
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready (cleared by writing TWIHS_THR)
bits : 2 - 2 (1 bit)
access : read-only

SVREAD : Slave Read
bits : 3 - 3 (1 bit)
access : read-only

SVACC : Slave Access
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access (cleared on read)
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error (cleared on read)
bits : 6 - 6 (1 bit)
access : read-only

UNRE : Underrun Error (cleared on read)
bits : 7 - 7 (1 bit)
access : read-only

NACK : Not Acknowledged (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost (cleared on read)
bits : 9 - 9 (1 bit)
access : read-only

SCLWS : Clock Wait State
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access (cleared on read)
bits : 11 - 11 (1 bit)
access : read-only

MCACK : Master Code Acknowledge (cleared on read)
bits : 16 - 16 (1 bit)
access : read-only

TOUT : Timeout Error (cleared on read)
bits : 18 - 18 (1 bit)
access : read-only

PECERR : PEC Error (cleared on read)
bits : 19 - 19 (1 bit)
access : read-only

SMBDAM : SMBus Default Address Match (cleared on read)
bits : 20 - 20 (1 bit)
access : read-only

SMBHHM : SMBus Host Header Address Match (cleared on read)
bits : 21 - 21 (1 bit)
access : read-only

SCL : SCL Line Value
bits : 24 - 24 (1 bit)
access : read-only

SDA : SDA Line Value
bits : 25 - 25 (1 bit)
access : read-only


TWIHS_TWIHS_IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_IER TWIHS_TWIHS_IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Enable
bits : 0 - 0 (1 bit)

RXRDY : Receive Holding Register Ready Interrupt Enable
bits : 1 - 1 (1 bit)

TXRDY : Transmit Holding Register Ready Interrupt Enable
bits : 2 - 2 (1 bit)

SVACC : Slave Access Interrupt Enable
bits : 4 - 4 (1 bit)

GACC : General Call Access Interrupt Enable
bits : 5 - 5 (1 bit)

OVRE : Overrun Error Interrupt Enable
bits : 6 - 6 (1 bit)

UNRE : Underrun Error Interrupt Enable
bits : 7 - 7 (1 bit)

NACK : Not Acknowledge Interrupt Enable
bits : 8 - 8 (1 bit)

ARBLST : Arbitration Lost Interrupt Enable
bits : 9 - 9 (1 bit)

SCL_WS : Clock Wait State Interrupt Enable
bits : 10 - 10 (1 bit)

EOSACC : End Of Slave Access Interrupt Enable
bits : 11 - 11 (1 bit)

MCACK : Master Code Acknowledge Interrupt Enable
bits : 16 - 16 (1 bit)

TOUT : Timeout Error Interrupt Enable
bits : 18 - 18 (1 bit)

PECERR : PEC Error Interrupt Enable
bits : 19 - 19 (1 bit)

SMBDAM : SMBus Default Address Match Interrupt Enable
bits : 20 - 20 (1 bit)

SMBHHM : SMBus Host Header Address Match Interrupt Enable
bits : 21 - 21 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receive Holding Register Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Holding Register Ready Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

SVACC : Slave Access Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

GACC : General Call Access Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

UNRE : Underrun Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NACK : Not Acknowledge Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

ARBLST : Arbitration Lost Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

SCL_WS : Clock Wait State Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

EOSACC : End Of Slave Access Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

MCACK : Master Code Acknowledge Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

TOUT : Timeout Error Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only

PECERR : PEC Error Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only

SMBDAM : SMBus Default Address Match Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only

SMBHHM : SMBus Host Header Address Match Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only


TWIHS_TWIHS_IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_IDR TWIHS_TWIHS_IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Disable
bits : 0 - 0 (1 bit)

RXRDY : Receive Holding Register Ready Interrupt Disable
bits : 1 - 1 (1 bit)

TXRDY : Transmit Holding Register Ready Interrupt Disable
bits : 2 - 2 (1 bit)

SVACC : Slave Access Interrupt Disable
bits : 4 - 4 (1 bit)

GACC : General Call Access Interrupt Disable
bits : 5 - 5 (1 bit)

OVRE : Overrun Error Interrupt Disable
bits : 6 - 6 (1 bit)

UNRE : Underrun Error Interrupt Disable
bits : 7 - 7 (1 bit)

NACK : Not Acknowledge Interrupt Disable
bits : 8 - 8 (1 bit)

ARBLST : Arbitration Lost Interrupt Disable
bits : 9 - 9 (1 bit)

SCL_WS : Clock Wait State Interrupt Disable
bits : 10 - 10 (1 bit)

EOSACC : End Of Slave Access Interrupt Disable
bits : 11 - 11 (1 bit)

MCACK : Master Code Acknowledge Interrupt Disable
bits : 16 - 16 (1 bit)

TOUT : Timeout Error Interrupt Disable
bits : 18 - 18 (1 bit)

PECERR : PEC Error Interrupt Disable
bits : 19 - 19 (1 bit)

SMBDAM : SMBus Default Address Match Interrupt Disable
bits : 20 - 20 (1 bit)

SMBHHM : SMBus Host Header Address Match Interrupt Disable
bits : 21 - 21 (1 bit)


IDR

Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

RXRDY : Receive Holding Register Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXRDY : Transmit Holding Register Ready Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

SVACC : Slave Access Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

GACC : General Call Access Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

OVRE : Overrun Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

UNRE : Underrun Error Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NACK : Not Acknowledge Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

ARBLST : Arbitration Lost Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

SCL_WS : Clock Wait State Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

EOSACC : End Of Slave Access Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

MCACK : Master Code Acknowledge Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

TOUT : Timeout Error Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only

PECERR : PEC Error Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only

SMBDAM : SMBus Default Address Match Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only

SMBHHM : SMBus Host Header Address Match Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only


TWIHS_TWIHS_IMR

Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_IMR TWIHS_TWIHS_IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Mask
bits : 0 - 0 (1 bit)

RXRDY : Receive Holding Register Ready Interrupt Mask
bits : 1 - 1 (1 bit)

TXRDY : Transmit Holding Register Ready Interrupt Mask
bits : 2 - 2 (1 bit)

SVACC : Slave Access Interrupt Mask
bits : 4 - 4 (1 bit)

GACC : General Call Access Interrupt Mask
bits : 5 - 5 (1 bit)

OVRE : Overrun Error Interrupt Mask
bits : 6 - 6 (1 bit)

UNRE : Underrun Error Interrupt Mask
bits : 7 - 7 (1 bit)

NACK : Not Acknowledge Interrupt Mask
bits : 8 - 8 (1 bit)

ARBLST : Arbitration Lost Interrupt Mask
bits : 9 - 9 (1 bit)

SCL_WS : Clock Wait State Interrupt Mask
bits : 10 - 10 (1 bit)

EOSACC : End Of Slave Access Interrupt Mask
bits : 11 - 11 (1 bit)

MCACK : Master Code Acknowledge Interrupt Mask
bits : 16 - 16 (1 bit)

TOUT : Timeout Error Interrupt Mask
bits : 18 - 18 (1 bit)

PECERR : PEC Error Interrupt Mask
bits : 19 - 19 (1 bit)

SMBDAM : SMBus Default Address Match Interrupt Mask
bits : 20 - 20 (1 bit)

SMBHHM : SMBus Host Header Address Match Interrupt Mask
bits : 21 - 21 (1 bit)


IMR

Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCOMP RXRDY TXRDY SVACC GACC OVRE UNRE NACK ARBLST SCL_WS EOSACC MCACK TOUT PECERR SMBDAM SMBHHM

TXCOMP : Transmission Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

RXRDY : Receive Holding Register Ready Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

TXRDY : Transmit Holding Register Ready Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

SVACC : Slave Access Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

GACC : General Call Access Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

OVRE : Overrun Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

UNRE : Underrun Error Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

NACK : Not Acknowledge Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

ARBLST : Arbitration Lost Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only

SCL_WS : Clock Wait State Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only

EOSACC : End Of Slave Access Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only

MCACK : Master Code Acknowledge Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

TOUT : Timeout Error Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only

PECERR : PEC Error Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only

SMBDAM : SMBus Default Address Match Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only

SMBHHM : SMBus Host Header Address Match Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only


TWIHS_TWIHS_RHR

Receive Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_RHR TWIHS_TWIHS_RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Master or Slave Receive Holding Data
bits : 0 - 7 (8 bit)


RHR

Receive Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

RHR RHR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : Master or Slave Receive Holding Data
bits : 0 - 7 (8 bit)
access : read-only


TWIHS_TWIHS_THR

Transmit Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_THR TWIHS_TWIHS_THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Master or Slave Transmit Holding Data
bits : 0 - 7 (8 bit)


THR

Transmit Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

THR THR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : Master or Slave Transmit Holding Data
bits : 0 - 7 (8 bit)
access : write-only


TWIHS_TWIHS_SMBTR

SMBus Timing Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_SMBTR TWIHS_TWIHS_SMBTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC TLOWS TLOWM THMAX

PRESC : SMBus Clock Prescaler
bits : 0 - 3 (4 bit)

TLOWS : Slave Clock Stretch Maximum Cycles
bits : 8 - 15 (8 bit)

TLOWM : Master Clock Stretch Maximum Cycles
bits : 16 - 23 (8 bit)

THMAX : Clock High Maximum Cycles
bits : 24 - 31 (8 bit)


SMBTR

SMBus Timing Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SMBTR SMBTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESC TLOWS TLOWM THMAX

PRESC : SMBus Clock Prescaler
bits : 0 - 3 (4 bit)
access : read-write

TLOWS : Slave Clock Stretch Maximum Cycles
bits : 8 - 15 (8 bit)
access : read-write

TLOWM : Master Clock Stretch Maximum Cycles
bits : 16 - 23 (8 bit)
access : read-write

THMAX : Clock High Maximum Cycles
bits : 24 - 31 (8 bit)
access : read-write


TWIHS_TWIHS_MMR

Master Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_MMR TWIHS_TWIHS_MMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADRSZ MREAD DADR

IADRSZ : Internal Device Address Size
bits : 8 - 9 (2 bit)

Enumeration: IADRSZSelect

0 : NONE

No internal device address

1 : _1_BYTE

One-byte internal device address

2 : _2_BYTE

Two-byte internal device address

3 : _3_BYTE

Three-byte internal device address

End of enumeration elements list.

MREAD : Master Read Direction
bits : 12 - 12 (1 bit)

DADR : Device Address
bits : 16 - 22 (7 bit)


MMR

Master Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MMR MMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADRSZ MREAD DADR

IADRSZ : Internal Device Address Size
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : NONE

No internal device address

0x1 : 1_BYTE

One-byte internal device address

0x2 : 2_BYTE

Two-byte internal device address

0x3 : 3_BYTE

Three-byte internal device address

End of enumeration elements list.

MREAD : Master Read Direction
bits : 12 - 12 (1 bit)
access : read-write

DADR : Device Address
bits : 16 - 22 (7 bit)
access : read-write


TWIHS_TWIHS_FILTR

Filter Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_FILTR TWIHS_TWIHS_FILTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILT PADFEN PADFCFG THRES

FILT : RX Digital Filter
bits : 0 - 0 (1 bit)

PADFEN : PAD Filter Enable
bits : 1 - 1 (1 bit)

PADFCFG : PAD Filter Config
bits : 2 - 2 (1 bit)

THRES : Digital Filter Threshold
bits : 8 - 10 (3 bit)


FILTR

Filter Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FILTR FILTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILT PADFEN PADFCFG THRES

FILT : RX Digital Filter
bits : 0 - 0 (1 bit)
access : read-write

PADFEN : PAD Filter Enable
bits : 1 - 1 (1 bit)
access : read-write

PADFCFG : PAD Filter Config
bits : 2 - 2 (1 bit)
access : read-write

THRES : Digital Filter Threshold
bits : 8 - 10 (3 bit)
access : read-write


TWIHS_TWIHS_SWMR

SleepWalking Matching Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_SWMR TWIHS_TWIHS_SWMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADR1 SADR2 SADR3 DATAM

SADR1 : Slave Address 1
bits : 0 - 6 (7 bit)

SADR2 : Slave Address 2
bits : 8 - 14 (7 bit)

SADR3 : Slave Address 3
bits : 16 - 22 (7 bit)

DATAM : Data Match
bits : 24 - 31 (8 bit)


SWMR

SleepWalking Matching Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SWMR SWMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADR1 SADR2 SADR3 DATAM

SADR1 : Slave Address 1
bits : 0 - 6 (7 bit)
access : read-write

SADR2 : Slave Address 2
bits : 8 - 14 (7 bit)
access : read-write

SADR3 : Slave Address 3
bits : 16 - 22 (7 bit)
access : read-write

DATAM : Data Match
bits : 24 - 31 (8 bit)
access : read-write


TWIHS_TWIHS_SMR

Slave Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_SMR TWIHS_TWIHS_SMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NACKEN SMDA SMHH SCLWSDIS MASK SADR SADR1EN SADR2EN SADR3EN DATAMEN

NACKEN : Slave Receiver Data Phase NACK enable
bits : 0 - 0 (1 bit)

SMDA : SMBus Default Address
bits : 2 - 2 (1 bit)

SMHH : SMBus Host Header
bits : 3 - 3 (1 bit)

SCLWSDIS : Clock Wait State Disable
bits : 6 - 6 (1 bit)

MASK : Slave Address Mask
bits : 8 - 14 (7 bit)

SADR : Slave Address
bits : 16 - 22 (7 bit)

SADR1EN : Slave Address 1 Enable
bits : 28 - 28 (1 bit)

SADR2EN : Slave Address 2 Enable
bits : 29 - 29 (1 bit)

SADR3EN : Slave Address 3 Enable
bits : 30 - 30 (1 bit)

DATAMEN : Data Matching Enable
bits : 31 - 31 (1 bit)


SMR

Slave Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SMR SMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NACKEN SMDA SMHH SCLWSDIS MASK SADR SADR1EN SADR2EN SADR3EN DATAMEN

NACKEN : Slave Receiver Data Phase NACK enable
bits : 0 - 0 (1 bit)
access : read-write

SMDA : SMBus Default Address
bits : 2 - 2 (1 bit)
access : read-write

SMHH : SMBus Host Header
bits : 3 - 3 (1 bit)
access : read-write

SCLWSDIS : Clock Wait State Disable
bits : 6 - 6 (1 bit)
access : read-write

MASK : Slave Address Mask
bits : 8 - 14 (7 bit)
access : read-write

SADR : Slave Address
bits : 16 - 22 (7 bit)
access : read-write

SADR1EN : Slave Address 1 Enable
bits : 28 - 28 (1 bit)
access : read-write

SADR2EN : Slave Address 2 Enable
bits : 29 - 29 (1 bit)
access : read-write

SADR3EN : Slave Address 3 Enable
bits : 30 - 30 (1 bit)
access : read-write

DATAMEN : Data Matching Enable
bits : 31 - 31 (1 bit)
access : read-write


TWIHS_TWIHS_IADR

Internal Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_IADR TWIHS_TWIHS_IADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADR

IADR : Internal Address
bits : 0 - 23 (24 bit)


IADR

Internal Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

IADR IADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IADR

IADR : Internal Address
bits : 0 - 23 (24 bit)
access : read-write


TWIHS_TWIHS_WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_WPMR TWIHS_TWIHS_WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)

Enumeration: WPKEYSelect

5527369 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

End of enumeration elements list.


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x545749 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0

End of enumeration elements list.


TWIHS_TWIHS_WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TWIHS_TWIHS_WPSR TWIHS_TWIHS_WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)

WPVSRC : Write Protection Violation Source
bits : 8 - 31 (24 bit)


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 31 (24 bit)
access : read-only



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