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address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
MPU Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEPARATE : Indicates support for unified or separate instruction and date memory maps.
bits : 0 - 0 (1 bit)
DREGION : Indicates the number of supported MPU instruction regions.
bits : 8 - 15 (8 bit)
IREGION : Indicates the number of supported MPU data regions.
bits : 16 - 23 (8 bit)
MPU Region Attribute and Size Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Region enable bit.
bits : 0 - 0 (1 bit)
SIZE : Specifies the size of the MPU protection region.
bits : 1 - 5 (5 bit)
SRD : Subregion disable bits.
bits : 8 - 15 (8 bit)
B : MPU access permission attributes.
bits : 16 - 16 (1 bit)
C : MPU access permission attributes.
bits : 17 - 17 (1 bit)
S : Shareable bit.
bits : 18 - 18 (1 bit)
TEX : MPU access permission attributes.
bits : 19 - 21 (3 bit)
AP : Access permission field.
bits : 24 - 26 (3 bit)
XN : Instruction access disable bit.
bits : 28 - 28 (1 bit)
MPU Alias 1 Region Base Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 1 Region Attribute and Size Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 2 Region Base Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 2 Region Attribute and Size Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 3 Region Base Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 3 Region Attribute and Size Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enables the MPU
bits : 0 - 0 (1 bit)
HFNMIENA : Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
bits : 1 - 1 (1 bit)
PRIVDEFENA : Enables privileged software access to the default memory map.
bits : 2 - 2 (1 bit)
MPU Region Number Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGION : Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
bits : 0 - 7 (8 bit)
MPU Region Base Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGION : MPU region field.
bits : 0 - 3 (4 bit)
VALID : MPU Region Number valid bit.
bits : 4 - 4 (1 bit)
ADDR : Region base address field.
bits : 5 - 31 (27 bit)
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