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SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SPI_SPI_CR

CR

SPI_SPI_SR

SR

SPI_SPI_CSR[3]

SPI_SPI_IER

IER

SPI_SPI_IDR

IDR

SPI_SPI_IMR

IMR

CSR0

CSR1

CSR2

CSR3

SPI_SPI_MR

MR

SPI_SPI_CSR[0]

SPI_SPI_RDR

RDR

SPI_SPI_CSR[1]

SPI_SPI_TDR

TDR

SPI_SPI_CSR[2]

SPI_SPI_WPMR

WPMR

SPI_SPI_WPSR

WPSR


SPI_SPI_CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_CR SPI_SPI_CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIEN SPIDIS SWRST REQCLR TXFCLR RXFCLR LASTXFER FIFOEN FIFODIS

SPIEN : SPI Enable
bits : 0 - 0 (1 bit)

SPIDIS : SPI Disable
bits : 1 - 1 (1 bit)

SWRST : SPI Software Reset
bits : 7 - 7 (1 bit)

REQCLR : Request to Clear the Comparison Trigger
bits : 12 - 12 (1 bit)

TXFCLR : Transmit FIFO Clear
bits : 16 - 16 (1 bit)

RXFCLR : Receive FIFO Clear
bits : 17 - 17 (1 bit)

LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)

FIFOEN : FIFO Enable
bits : 30 - 30 (1 bit)

FIFODIS : FIFO Disable
bits : 31 - 31 (1 bit)


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIEN SPIDIS SWRST LASTXFER

SPIEN : SPI Enable
bits : 0 - 0 (1 bit)
access : write-only

SPIDIS : SPI Disable
bits : 1 - 1 (1 bit)
access : write-only

SWRST : SPI Software Reset
bits : 7 - 7 (1 bit)
access : write-only

LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
access : write-only


SPI_SPI_SR

Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_SR SPI_SPI_SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES NSSR TXEMPTY UNDES SPIENS

RDRF : Receive Data Register Full (cleared by reading SPI_RDR)
bits : 0 - 0 (1 bit)

TDRE : Transmit Data Register Empty (cleared by writing SPI_TDR)
bits : 1 - 1 (1 bit)

MODF : Mode Fault Error (cleared on read)
bits : 2 - 2 (1 bit)

OVRES : Overrun Error Status (cleared on read)
bits : 3 - 3 (1 bit)

NSSR : NSS Rising (cleared on read)
bits : 8 - 8 (1 bit)

TXEMPTY : Transmission Registers Empty (cleared by writing SPI_TDR)
bits : 9 - 9 (1 bit)

UNDES : Underrun Error Status (Slave mode only) (cleared on read)
bits : 10 - 10 (1 bit)

SPIENS : SPI Enable Status
bits : 16 - 16 (1 bit)


SR

Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES NSSR TXEMPTY UNDES SPIENS

RDRF : Receive Data Register Full (cleared by reading SPI_RDR)
bits : 0 - 0 (1 bit)
access : read-only

TDRE : Transmit Data Register Empty (cleared by writing SPI_TDR)
bits : 1 - 1 (1 bit)
access : read-only

MODF : Mode Fault Error (cleared on read)
bits : 2 - 2 (1 bit)
access : read-only

OVRES : Overrun Error Status (cleared on read)
bits : 3 - 3 (1 bit)
access : read-only

NSSR : NSS Rising (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmission Registers Empty (cleared by writing SPI_TDR)
bits : 9 - 9 (1 bit)
access : read-only

UNDES : Underrun Error Status (Slave mode only) (cleared on read)
bits : 10 - 10 (1 bit)
access : read-only

SPIENS : SPI Enable Status
bits : 16 - 16 (1 bit)
access : read-only


SPI_SPI_CSR[3]

Chip Select Register 0
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_CSR[3] SPI_SPI_CSR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)

Enumeration: BITSSelect

0 : _8_BIT

8 bits for transfer

1 : _9_BIT

9 bits for transfer

2 : _10_BIT

10 bits for transfer

3 : _11_BIT

11 bits for transfer

4 : _12_BIT

12 bits for transfer

5 : _13_BIT

13 bits for transfer

6 : _14_BIT

14 bits for transfer

7 : _15_BIT

15 bits for transfer

8 : _16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)


SPI_SPI_IER

Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_IER SPI_SPI_IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Enable
bits : 0 - 0 (1 bit)

TDRE : SPI Transmit Data Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)

MODF : Mode Fault Error Interrupt Enable
bits : 2 - 2 (1 bit)

OVRES : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)

NSSR : NSS Rising Interrupt Enable
bits : 8 - 8 (1 bit)

TXEMPTY : Transmission Registers Empty Enable
bits : 9 - 9 (1 bit)

UNDES : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TDRE : SPI Transmit Data Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

MODF : Mode Fault Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

OVRES : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NSSR : NSS Rising Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : Transmission Registers Empty Enable
bits : 9 - 9 (1 bit)
access : write-only

UNDES : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only


SPI_SPI_IDR

Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_IDR SPI_SPI_IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Disable
bits : 0 - 0 (1 bit)

TDRE : SPI Transmit Data Register Empty Interrupt Disable
bits : 1 - 1 (1 bit)

MODF : Mode Fault Error Interrupt Disable
bits : 2 - 2 (1 bit)

OVRES : Overrun Error Interrupt Disable
bits : 3 - 3 (1 bit)

NSSR : NSS Rising Interrupt Disable
bits : 8 - 8 (1 bit)

TXEMPTY : Transmission Registers Empty Disable
bits : 9 - 9 (1 bit)

UNDES : Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)


IDR

Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TDRE : SPI Transmit Data Register Empty Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

MODF : Mode Fault Error Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

OVRES : Overrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NSSR : NSS Rising Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : Transmission Registers Empty Disable
bits : 9 - 9 (1 bit)
access : write-only

UNDES : Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only


SPI_SPI_IMR

Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_IMR SPI_SPI_IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Mask
bits : 0 - 0 (1 bit)

TDRE : SPI Transmit Data Register Empty Interrupt Mask
bits : 1 - 1 (1 bit)

MODF : Mode Fault Error Interrupt Mask
bits : 2 - 2 (1 bit)

OVRES : Overrun Error Interrupt Mask
bits : 3 - 3 (1 bit)

NSSR : NSS Rising Interrupt Mask
bits : 8 - 8 (1 bit)

TXEMPTY : Transmission Registers Empty Mask
bits : 9 - 9 (1 bit)

UNDES : Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)


IMR

Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TDRE : SPI Transmit Data Register Empty Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

MODF : Mode Fault Error Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

OVRES : Overrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

NSSR : NSS Rising Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmission Registers Empty Mask
bits : 9 - 9 (1 bit)
access : read-only

UNDES : Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only


CSR0

Chip Select Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSR0 CSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


CSR1

Chip Select Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSR1 CSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


CSR2

Chip Select Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSR2 CSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


CSR3

Chip Select Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSR3 CSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


SPI_SPI_MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_MR SPI_SPI_MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSTR PS PCSDEC MODFDIS WDRBT LLB PCS DLYBCS

MSTR : Master/Slave Mode
bits : 0 - 0 (1 bit)

PS : Peripheral Select
bits : 1 - 1 (1 bit)

PCSDEC : Chip Select Decode
bits : 2 - 2 (1 bit)

MODFDIS : Mode Fault Detection
bits : 4 - 4 (1 bit)

WDRBT : Wait Data Read Before Transfer
bits : 5 - 5 (1 bit)

LLB : Local Loopback Enable
bits : 7 - 7 (1 bit)

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)

DLYBCS : Delay Between Chip Selects
bits : 24 - 31 (8 bit)


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSTR PS PCSDEC MODFDIS WDRBT LLB PCS DLYBCS

MSTR : Master/Slave Mode
bits : 0 - 0 (1 bit)
access : read-write

PS : Peripheral Select
bits : 1 - 1 (1 bit)
access : read-write

PCSDEC : Chip Select Decode
bits : 2 - 2 (1 bit)
access : read-write

MODFDIS : Mode Fault Detection
bits : 4 - 4 (1 bit)
access : read-write

WDRBT : Wait Data Read Before Transfer
bits : 5 - 5 (1 bit)
access : read-write

LLB : Local Loopback Enable
bits : 7 - 7 (1 bit)
access : read-write

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : read-write

DLYBCS : Delay Between Chip Selects
bits : 24 - 31 (8 bit)
access : read-write


SPI_SPI_CSR[0]

Chip Select Register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_CSR[0] SPI_SPI_CSR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)

Enumeration: BITSSelect

0 : _8_BIT

8 bits for transfer

1 : _9_BIT

9 bits for transfer

2 : _10_BIT

10 bits for transfer

3 : _11_BIT

11 bits for transfer

4 : _12_BIT

12 bits for transfer

5 : _13_BIT

13 bits for transfer

6 : _14_BIT

14 bits for transfer

7 : _15_BIT

15 bits for transfer

8 : _16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)


SPI_SPI_RDR

Receive Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_RDR SPI_SPI_RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD PCS

RD : Receive Data
bits : 0 - 15 (16 bit)

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)


RDR

Receive Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

RDR RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD PCS

RD : Receive Data
bits : 0 - 15 (16 bit)
access : read-only

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : read-only


SPI_SPI_CSR[1]

Chip Select Register 0
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_CSR[1] SPI_SPI_CSR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)

Enumeration: BITSSelect

0 : _8_BIT

8 bits for transfer

1 : _9_BIT

9 bits for transfer

2 : _10_BIT

10 bits for transfer

3 : _11_BIT

11 bits for transfer

4 : _12_BIT

12 bits for transfer

5 : _13_BIT

13 bits for transfer

6 : _14_BIT

14 bits for transfer

7 : _15_BIT

15 bits for transfer

8 : _16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)


SPI_SPI_TDR

Transmit Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_TDR SPI_SPI_TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TD PCS LASTXFER

TD : Transmit Data
bits : 0 - 15 (16 bit)

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)

LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)


TDR

Transmit Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

TDR TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TD PCS LASTXFER

TD : Transmit Data
bits : 0 - 15 (16 bit)
access : write-only

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : write-only

LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
access : write-only


SPI_SPI_CSR[2]

Chip Select Register 0
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_CSR[2] SPI_SPI_CSR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)

Enumeration: BITSSelect

0 : _8_BIT

8 bits for transfer

1 : _9_BIT

9 bits for transfer

2 : _10_BIT

10 bits for transfer

3 : _11_BIT

11 bits for transfer

4 : _12_BIT

12 bits for transfer

5 : _13_BIT

13 bits for transfer

6 : _14_BIT

14 bits for transfer

7 : _15_BIT

15 bits for transfer

8 : _16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Bit Rate
bits : 8 - 15 (8 bit)

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)


SPI_SPI_WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_WPMR SPI_SPI_WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)

Enumeration: WPKEYSelect

5460041 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x535049 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


SPI_SPI_WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SPI_SPI_WPSR SPI_SPI_WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)

WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
access : read-only



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