Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected
SA3-GMAC_SA2-GMAC_SA1-GMAC_SAB
SA3-GMAC_SA2-GMAC_SA1-GMAC_SAT
SA4-GMAC_SA3-GMAC_SA2-GMAC_SA1-GMAC_SAB
SA4-GMAC_SA3-GMAC_SA2-GMAC_SA1-GMAC_SAT
Network Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBL : Loop Back Local
bits : 1 - 1 (1 bit)
RXEN : Receive Enable
bits : 2 - 2 (1 bit)
TXEN : Transmit Enable
bits : 3 - 3 (1 bit)
MPE : Management Port Enable
bits : 4 - 4 (1 bit)
CLRSTAT : Clear Statistics Registers
bits : 5 - 5 (1 bit)
INCSTAT : Increment Statistics Registers
bits : 6 - 6 (1 bit)
WESTAT : Write Enable for Statistics Registers
bits : 7 - 7 (1 bit)
BP : Back pressure
bits : 8 - 8 (1 bit)
TSTART : Start Transmission
bits : 9 - 9 (1 bit)
THALT : Transmit Halt
bits : 10 - 10 (1 bit)
TXPF : Transmit Pause Frame
bits : 11 - 11 (1 bit)
TXZQPF : Transmit Zero Quantum Pause Frame
bits : 12 - 12 (1 bit)
SRTSM : Store Receive Time Stamp to Memory
bits : 15 - 15 (1 bit)
ENPBPR : Enable PFC Priority-based Pause Reception
bits : 16 - 16 (1 bit)
TXPBPF : Transmit PFC Priority-based Pause Frame
bits : 17 - 17 (1 bit)
FNP : Flush Next Packet
bits : 18 - 18 (1 bit)
DMA Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBLDO : Fixed Burst Length for DMA Data Operations:
bits : 0 - 4 (5 bit)
Enumeration: FBLDOSelect
1 : SINGLE
00001: Always use SINGLE AHB bursts
4 : INCR4
001xx: Attempt to use INCR4 AHB bursts (Default)
8 : INCR8
01xxx: Attempt to use INCR8 AHB bursts
16 : INCR16
1xxxx: Attempt to use INCR16 AHB bursts
End of enumeration elements list.
ESMA : Endian Swap Mode Enable for Management Descriptor Accesses
bits : 6 - 6 (1 bit)
ESPA : Endian Swap Mode Enable for Packet Data Accesses
bits : 7 - 7 (1 bit)
RXBMS : Receiver Packet Buffer Memory Size Select
bits : 8 - 9 (2 bit)
Enumeration: RXBMSSelect
0 : EIGHTH
4/8 Kbyte Memory Size
1 : QUARTER
4/4 Kbytes Memory Size
2 : HALF
4/2 Kbytes Memory Size
3 : FULL
4 Kbytes Memory Size
End of enumeration elements list.
TXPBMS : Transmitter Packet Buffer Memory Size Select
bits : 10 - 10 (1 bit)
TXCOEN : Transmitter Checksum Generation Offload Enable
bits : 11 - 11 (1 bit)
DRBS : DMA Receive Buffer Size
bits : 16 - 23 (8 bit)
DDRP : DMA Discard Receive Packets
bits : 24 - 24 (1 bit)
Octets Transmitted Low Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXO : Transmitted Octets
bits : 0 - 31 (32 bit)
Octets Transmitted High Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXO : Transmitted Octets
bits : 0 - 15 (16 bit)
Frames Transmitted Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FTX : Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Broadcast Frames Transmitted Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BFTX : Broadcast Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Multicast Frames Transmitted Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFTX : Multicast Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Pause Frames Transmitted Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PFTX : Pause Frames Transmitted Register
bits : 0 - 15 (16 bit)
Specific Address 1 Bottom Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 31 (32 bit)
64 Byte Frames Transmitted Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 64 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Specific Address 1 Top Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 15 (16 bit)
65 to 127 Byte Frames Transmitted Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 65 to 127 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Interrupt Enable Register Priority Queue (index = 1) 0
address_offset : 0x11F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
128 to 255 Byte Frames Transmitted Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 128 to 255 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
256 to 511 Byte Frames Transmitted Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 256 to 511 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Interrupt Disable Register Priority Queue (index = 1) 0
address_offset : 0x1258 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
512 to 1023 Byte Frames Transmitted Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 512 to 1023 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Interrupt Mask Register Priority Queue (index = 1) 0
address_offset : 0x12B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
AHB : AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
1024 to 1518 Byte Frames Transmitted Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : 1024 to 1518 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Greater Than 1518 Byte Frames Transmitted Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFTX : Greater than 1518 Byte Frames Transmitted without Error
bits : 0 - 31 (32 bit)
Transmit Underruns Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXUNR : Transmit Underruns
bits : 0 - 9 (10 bit)
Single Collision Frames Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SCOL : Single Collision
bits : 0 - 17 (18 bit)
Multiple Collision Frames Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MCOL : Multiple Collision
bits : 0 - 17 (18 bit)
Transmit Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UBR : Used Bit Read
bits : 0 - 0 (1 bit)
COL : Collision Occurred
bits : 1 - 1 (1 bit)
RLE : Retry Limit Exceeded
bits : 2 - 2 (1 bit)
TXGO : Transmit Go
bits : 3 - 3 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 4 - 4 (1 bit)
TXCOMP : Transmit Complete
bits : 5 - 5 (1 bit)
HRESP : HRESP Not OK
bits : 8 - 8 (1 bit)
Excessive Collisions Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XCOL : Excessive Collisions
bits : 0 - 9 (10 bit)
Screening Type 1 Register Priority Queue (index = 0) 0
address_offset : 0x140C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
DSTCM : Differentiated Services or Traffic Class Match
bits : 4 - 11 (8 bit)
UDPM : UDP Port Match
bits : 12 - 27 (16 bit)
DSTCE : Differentiated Services or Traffic Class Match Enable
bits : 28 - 28 (1 bit)
UDPE : UDP Port Match Enable
bits : 29 - 29 (1 bit)
Late Collisions Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LCOL : Late Collisions
bits : 0 - 9 (10 bit)
Deferred Transmission Frames Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEFT : Deferred Transmission
bits : 0 - 17 (18 bit)
Screening Type 2 Ethertype Register (index = 0) 0
address_offset : 0x14A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPVAL : Ethertype Compare Value
bits : 0 - 15 (16 bit)
Carrier Sense Errors Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSR : Carrier Sense Error
bits : 0 - 9 (10 bit)
Octets Received Low Received Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXO : Received Octets
bits : 0 - 31 (32 bit)
Screening Type 2 Register Priority Queue (index = 0) 0
address_offset : 0x150C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
Octets Received High Received Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXO : Received Octets
bits : 0 - 15 (16 bit)
Frames Received Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRX : Frames Received without Error
bits : 0 - 31 (32 bit)
Broadcast Frames Received Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BFRX : Broadcast Frames Received without Error
bits : 0 - 31 (32 bit)
Multicast Frames Received Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFRX : Multicast Frames Received without Error
bits : 0 - 31 (32 bit)
Pause Frames Received Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PFRX : Pause Frames Received Register
bits : 0 - 15 (16 bit)
64 Byte Frames Received Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 64 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
65 to 127 Byte Frames Received Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 65 to 127 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
128 to 255 Byte Frames Received Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 128 to 255 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
256 to 511 Byte Frames Received Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 256 to 511 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
512 to 1023 Byte Frames Received Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 512 to 1023 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
1024 to 1518 Byte Frames Received Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 1024 to 1518 Byte Frames Received without Error
bits : 0 - 31 (32 bit)
Receive Buffer Queue Base Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Receive Buffer Queue Base Address
bits : 2 - 31 (30 bit)
1519 to Maximum Byte Frames Received Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NFRX : 1519 to Maximum Byte Frames Received without Error
bits : 0 - 31 (32 bit)
Undersize Frames Received Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UFRX : Undersize Frames Received
bits : 0 - 9 (10 bit)
Oversize Frames Received Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OFRX : Oversized Frames Received
bits : 0 - 9 (10 bit)
Jabbers Received Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
JRX : Jabbers Received
bits : 0 - 9 (10 bit)
Frame Check Sequence Errors Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCKR : Frame Check Sequence Errors
bits : 0 - 9 (10 bit)
Screening Type 1 Register Priority Queue (index = 0) 0
address_offset : 0x1918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
DSTCM : Differentiated Services or Traffic Class Match
bits : 4 - 11 (8 bit)
UDPM : UDP Port Match
bits : 12 - 27 (16 bit)
DSTCE : Differentiated Services or Traffic Class Match Enable
bits : 28 - 28 (1 bit)
UDPE : UDP Port Match Enable
bits : 29 - 29 (1 bit)
Length Field Frame Errors Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LFER : Length Field Frame Errors
bits : 0 - 9 (10 bit)
Receive Symbol Errors Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXSE : Receive Symbol Errors
bits : 0 - 9 (10 bit)
Alignment Errors Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AER : Alignment Errors
bits : 0 - 9 (10 bit)
Receive Resource Errors Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRER : Receive Resource Errors
bits : 0 - 17 (18 bit)
Receive Overrun Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXOVR : Receive Overruns
bits : 0 - 9 (10 bit)
Screening Type 2 Register Priority Queue (index = 0) 0
address_offset : 0x1A58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
IP Header Checksum Errors Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HCKER : IP Header Checksum Errors
bits : 0 - 7 (8 bit)
TCP Checksum Errors Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TCKER : TCP Checksum Errors
bits : 0 - 7 (8 bit)
Specific Address 1 Bottom Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 31 (32 bit)
UDP Checksum Errors Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UCKER : UDP Checksum Errors
bits : 0 - 7 (8 bit)
Specific Address 1 Top Register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 15 (16 bit)
Screening Type 2 Ethertype Register (index = 0) 0
address_offset : 0x1B8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPVAL : Ethertype Compare Value
bits : 0 - 15 (16 bit)
1588 Timer Increment Sub-nanoseconds Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSBTIR : Lower Significant Bits of Timer Increment Register
bits : 0 - 15 (16 bit)
Transmit Buffer Queue Base Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Transmit Buffer Queue Base Address
bits : 2 - 31 (30 bit)
1588 Timer Seconds High Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCS : Timer Count in Seconds
bits : 0 - 15 (16 bit)
1588 Timer Seconds Low Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCS : Timer Count in Seconds
bits : 0 - 31 (32 bit)
1588 Timer Nanoseconds Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TNS : Timer Count in Nanoseconds
bits : 0 - 29 (30 bit)
1588 Timer Adjust Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ITDT : Increment/Decrement
bits : 0 - 29 (30 bit)
ADJ : Adjust 1588 Timer
bits : 31 - 31 (1 bit)
1588 Timer Increment Register
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNS : Count Nanoseconds
bits : 0 - 7 (8 bit)
ACNS : Alternative Count Nanoseconds
bits : 8 - 15 (8 bit)
NIT : Number of Increments
bits : 16 - 23 (8 bit)
PTP Event Frame Transmitted Seconds Low Register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 31 (32 bit)
PTP Event Frame Transmitted Nanoseconds Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 29 (30 bit)
PTP Event Frame Received Seconds Low Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 31 (32 bit)
PTP Event Frame Received Nanoseconds Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 29 (30 bit)
PTP Peer Event Frame Transmitted Seconds Low Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 31 (32 bit)
PTP Peer Event Frame Transmitted Nanoseconds Register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 29 (30 bit)
PTP Peer Event Frame Received Seconds Low Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 31 (32 bit)
Screening Type 2 Register Priority Queue (index = 0) 0
address_offset : 0x1FA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
PTP Peer Event Frame Received Nanoseconds Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 29 (30 bit)
Receive Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNA : Buffer Not Available
bits : 0 - 0 (1 bit)
REC : Frame Received
bits : 1 - 1 (1 bit)
RXOVR : Receive Overrun
bits : 2 - 2 (1 bit)
HNO : HRESP Not OK
bits : 3 - 3 (1 bit)
Screening Type 2 Ethertype Register (index = 0) 0
address_offset : 0x2278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPVAL : Ethertype Compare Value
bits : 0 - 15 (16 bit)
Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
RLEX : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
WOL : Wake On LAN
bits : 28 - 28 (1 bit)
Screening Type 2 Register Priority Queue (index = 0) 0
address_offset : 0x24FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
Specific Address 1 Bottom Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 31 (32 bit)
Specific Address 1 Top Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 15 (16 bit)
Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
EXINT : External Interrupt
bits : 15 - 15 (1 bit)
DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
WOL : Wake On LAN
bits : 28 - 28 (1 bit)
Screening Type 2 Register Priority Queue (index = 0) 0
address_offset : 0x2A54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
Interrupt Disable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
EXINT : External Interrupt
bits : 15 - 15 (1 bit)
DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
WOL : Wake On LAN
bits : 28 - 28 (1 bit)
Screening Type 2 Register Priority Queue (index = 0) 0
address_offset : 0x2FB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFS : Management Frame Sent
bits : 0 - 0 (1 bit)
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
TXUBR : TX Used Bit Read
bits : 3 - 3 (1 bit)
TUR : Transmit Underrun
bits : 4 - 4 (1 bit)
RLEX : Retry Limit Exceeded
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
PFNZ : Pause Frame with Non-zero Pause Quantum Received
bits : 12 - 12 (1 bit)
PTZ : Pause Time Zero
bits : 13 - 13 (1 bit)
PFTR : Pause Frame Transmitted
bits : 14 - 14 (1 bit)
EXINT : External Interrupt
bits : 15 - 15 (1 bit)
DRQFR : PTP Delay Request Frame Received
bits : 18 - 18 (1 bit)
SFR : PTP Sync Frame Received
bits : 19 - 19 (1 bit)
DRQFT : PTP Delay Request Frame Transmitted
bits : 20 - 20 (1 bit)
SFT : PTP Sync Frame Transmitted
bits : 21 - 21 (1 bit)
PDRQFR : PDelay Request Frame Received
bits : 22 - 22 (1 bit)
PDRSFR : PDelay Response Frame Received
bits : 23 - 23 (1 bit)
PDRQFT : PDelay Request Frame Transmitted
bits : 24 - 24 (1 bit)
PDRSFT : PDelay Response Frame Transmitted
bits : 25 - 25 (1 bit)
SRI : TSU Seconds Register Increment
bits : 26 - 26 (1 bit)
WOL : Wake On LAN
bits : 28 - 28 (1 bit)
PHY Maintenance Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : PHY Data
bits : 0 - 15 (16 bit)
WTN : Write Ten
bits : 16 - 17 (2 bit)
REGA : Register Address
bits : 18 - 22 (5 bit)
PHYA : PHY Address
bits : 23 - 27 (5 bit)
OP : Operation
bits : 28 - 29 (2 bit)
CLTTO : Clause 22 Operation
bits : 30 - 30 (1 bit)
WZO : Write ZERO
bits : 31 - 31 (1 bit)
Received Pause Quantum Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RPQ : Received Pause Quantum
bits : 0 - 15 (16 bit)
Transmit Pause Quantum Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPQ : Transmit Pause Quantum
bits : 0 - 15 (16 bit)
Network Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPD : Speed
bits : 0 - 0 (1 bit)
FD : Full Duplex
bits : 1 - 1 (1 bit)
DNVLAN : Discard Non-VLAN FRAMES
bits : 2 - 2 (1 bit)
JFRAME : Jumbo Frame Size
bits : 3 - 3 (1 bit)
CAF : Copy All Frames
bits : 4 - 4 (1 bit)
NBC : No Broadcast
bits : 5 - 5 (1 bit)
MTIHEN : Multicast Hash Enable
bits : 6 - 6 (1 bit)
UNIHEN : Unicast Hash Enable
bits : 7 - 7 (1 bit)
MAXFS : 1536 Maximum Frame Size
bits : 8 - 8 (1 bit)
RTY : Retry Test
bits : 12 - 12 (1 bit)
PEN : Pause Enable
bits : 13 - 13 (1 bit)
RXBUFO : Receive Buffer Offset
bits : 14 - 15 (2 bit)
LFERD : Length Field Error Frame Discard
bits : 16 - 16 (1 bit)
RFCS : Remove FCS
bits : 17 - 17 (1 bit)
CLK : MDC CLock Division
bits : 18 - 20 (3 bit)
Enumeration: CLKSelect
0 : MCK_8
MCK divided by 8 (MCK up to 20 MHz)
1 : MCK_16
MCK divided by 16 (MCK up to 40 MHz)
2 : MCK_32
MCK divided by 32 (MCK up to 80 MHz)
3 : MCK_48
MCK divided by 48 (MCK up to 120 MHz)
4 : MCK_64
MCK divided by 64 (MCK up to 160 MHz)
5 : MCK_96
MCK divided by 96 (MCK up to 240 MHz)
End of enumeration elements list.
DBW : Data Bus Width
bits : 21 - 22 (2 bit)
DCPF : Disable Copy of Pause Frames
bits : 23 - 23 (1 bit)
RXCOEN : Receive Checksum Offload Enable
bits : 24 - 24 (1 bit)
EFRHD : Enable Frames Received in Half Duplex
bits : 25 - 25 (1 bit)
IRXFCS : Ignore RX FCS
bits : 26 - 26 (1 bit)
IPGSEN : IP Stretch Enable
bits : 28 - 28 (1 bit)
RXBP : Receive Bad Preamble
bits : 29 - 29 (1 bit)
IRXER : Ignore IPG GRXER
bits : 30 - 30 (1 bit)
TX Partial Store and Forward Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPB1ADR : Transmit Partial Store and Forward Address
bits : 0 - 11 (12 bit)
ENTXP : Enable TX Partial Store and Forward Operation
bits : 31 - 31 (1 bit)
Interrupt Status Register Priority Queue (index = 1)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : read-only
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : read-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : read-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : read-only
Interrupt Status Register Priority Queue (index = 1)
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : read-only
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : read-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : read-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : read-only
RX Partial Store and Forward Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPB1ADR : Receive Partial Store and Forward Address
bits : 0 - 11 (12 bit)
ENRXP : Enable RX Partial Store and Forward Operation
bits : 31 - 31 (1 bit)
Transmit Buffer Queue Base Address Register Priority Queue (index = 1)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXBQBA : Transmit Buffer Queue Base Address
bits : 2 - 31 (30 bit)
access : read-write
Transmit Buffer Queue Base Address Register Priority Queue (index = 1)
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
TXBQBA : Transmit Buffer Queue Base Address
bits : 2 - 31 (30 bit)
access : read-write
RX Jumbo Frame Max Length Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FML : Frame Max Length
bits : 0 - 13 (14 bit)
Receive Buffer Queue Base Address Register Priority Queue (index = 1)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RXBQBA : Receive Buffer Queue Base Address
bits : 2 - 31 (30 bit)
access : read-write
Receive Buffer Queue Base Address Register Priority Queue (index = 1)
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RXBQBA : Receive Buffer Queue Base Address
bits : 2 - 31 (30 bit)
access : read-write
Receive Buffer Size Register Priority Queue (index = 1)
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RBS : Receive Buffer Size
bits : 0 - 15 (16 bit)
access : read-write
Receive Buffer Size Register Priority Queue (index = 1)
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RBS : Receive Buffer Size
bits : 0 - 15 (16 bit)
access : read-write
Credit-Based Shaping Control Register
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QBE : Queue B CBS Enable
bits : 0 - 0 (1 bit)
QAE : Queue A CBS Enable
bits : 1 - 1 (1 bit)
Credit-Based Shaping IdleSlope Register for Queue A
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IS : IdleSlope
bits : 0 - 31 (32 bit)
Credit-Based Shaping IdleSlope Register for Queue B
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IS : IdleSlope
bits : 0 - 31 (32 bit)
Screening Type 1 Register Priority Queue (index = 0)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
DSTCM : Differentiated Services or Traffic Class Match
bits : 4 - 11 (8 bit)
access : read-write
UDPM : UDP Port Match
bits : 12 - 27 (16 bit)
access : read-write
DSTCE : Differentiated Services or Traffic Class Match Enable
bits : 28 - 28 (1 bit)
access : read-write
UDPE : UDP Port Match Enable
bits : 29 - 29 (1 bit)
access : read-write
Screening Type 1 Register Priority Queue (index = 0)
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
DSTCM : Differentiated Services or Traffic Class Match
bits : 4 - 11 (8 bit)
access : read-write
UDPM : UDP Port Match
bits : 12 - 27 (16 bit)
access : read-write
DSTCE : Differentiated Services or Traffic Class Match Enable
bits : 28 - 28 (1 bit)
access : read-write
UDPE : UDP Port Match Enable
bits : 29 - 29 (1 bit)
access : read-write
Screening Type 1 Register Priority Queue (index = 0)
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
DSTCM : Differentiated Services or Traffic Class Match
bits : 4 - 11 (8 bit)
access : read-write
UDPM : UDP Port Match
bits : 12 - 27 (16 bit)
access : read-write
DSTCE : Differentiated Services or Traffic Class Match Enable
bits : 28 - 28 (1 bit)
access : read-write
UDPE : UDP Port Match Enable
bits : 29 - 29 (1 bit)
access : read-write
Screening Type 1 Register Priority Queue (index = 0)
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
DSTCM : Differentiated Services or Traffic Class Match
bits : 4 - 11 (8 bit)
access : read-write
UDPM : UDP Port Match
bits : 12 - 27 (16 bit)
access : read-write
DSTCE : Differentiated Services or Traffic Class Match Enable
bits : 28 - 28 (1 bit)
access : read-write
UDPE : UDP Port Match Enable
bits : 29 - 29 (1 bit)
access : read-write
Screening Type 2 Register Priority Queue (index = 0)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
access : read-write
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
access : read-write
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
access : read-write
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
access : read-write
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
access : read-write
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
access : read-write
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
access : read-write
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
access : read-write
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
access : read-write
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
access : read-write
Screening Type 2 Register Priority Queue (index = 0)
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
access : read-write
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
access : read-write
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
access : read-write
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
access : read-write
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
access : read-write
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
access : read-write
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
access : read-write
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
access : read-write
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
access : read-write
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
access : read-write
Screening Type 2 Register Priority Queue (index = 0)
address_offset : 0x548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
access : read-write
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
access : read-write
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
access : read-write
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
access : read-write
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
access : read-write
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
access : read-write
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
access : read-write
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
access : read-write
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
access : read-write
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
access : read-write
Screening Type 2 Register Priority Queue (index = 0)
address_offset : 0x54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
access : read-write
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
access : read-write
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
access : read-write
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
access : read-write
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
access : read-write
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
access : read-write
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
access : read-write
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
access : read-write
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
access : read-write
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
access : read-write
Screening Type 2 Register Priority Queue (index = 0)
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
access : read-write
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
access : read-write
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
access : read-write
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
access : read-write
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
access : read-write
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
access : read-write
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
access : read-write
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
access : read-write
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
access : read-write
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
access : read-write
Screening Type 2 Register Priority Queue (index = 0)
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
access : read-write
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
access : read-write
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
access : read-write
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
access : read-write
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
access : read-write
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
access : read-write
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
access : read-write
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
access : read-write
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
access : read-write
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
access : read-write
Screening Type 2 Register Priority Queue (index = 0)
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
access : read-write
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
access : read-write
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
access : read-write
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
access : read-write
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
access : read-write
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
access : read-write
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
access : read-write
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
access : read-write
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
access : read-write
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
access : read-write
Screening Type 2 Register Priority Queue (index = 0)
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
access : read-write
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
access : read-write
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
access : read-write
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
access : read-write
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
access : read-write
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
access : read-write
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
access : read-write
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
access : read-write
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
access : read-write
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
access : read-write
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
access : read-write
Interrupt Enable Register Priority Queue (index = 1)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : write-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : write-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : write-only
Interrupt Enable Register Priority Queue (index = 1)
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : write-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : write-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : write-only
Interrupt Disable Register Priority Queue (index = 1)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : write-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : write-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : write-only
Interrupt Disable Register Priority Queue (index = 1)
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : write-only
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : write-only
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : write-only
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
access : write-only
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : write-only
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : write-only
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : write-only
Interrupt Mask Register Priority Queue (index = 1)
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-write
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : read-write
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : read-write
AHB : AHB Error
bits : 6 - 6 (1 bit)
access : read-write
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-write
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-write
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : read-write
Interrupt Mask Register Priority Queue (index = 1)
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
access : read-write
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
access : read-write
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
access : read-write
AHB : AHB Error
bits : 6 - 6 (1 bit)
access : read-write
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
access : read-write
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
access : read-write
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
access : read-write
Screening Type 2 Ethertype Register (index = 0)
address_offset : 0x6E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
COMPVAL : Ethertype Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Screening Type 2 Ethertype Register (index = 0)
address_offset : 0x6E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
COMPVAL : Ethertype Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Screening Type 2 Ethertype Register (index = 0)
address_offset : 0x6E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
COMPVAL : Ethertype Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Screening Type 2 Ethertype Register (index = 0)
address_offset : 0x6EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
COMPVAL : Ethertype Compare Value
bits : 0 - 15 (16 bit)
access : read-write
Screening Type 2 Compare Word 0 Register (index = 0)
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 0)
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 1)
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 1)
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 2)
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 2)
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 3)
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 3)
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 4)
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 4)
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 5)
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 5)
address_offset : 0x72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 6)
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 6)
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 7)
address_offset : 0x738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 7)
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 8)
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 8)
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 9)
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 9)
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 10)
address_offset : 0x750 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 10)
address_offset : 0x754 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 11)
address_offset : 0x758 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 11)
address_offset : 0x75C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 12)
address_offset : 0x760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 12)
address_offset : 0x764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 13)
address_offset : 0x768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 13)
address_offset : 0x76C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 14)
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 14)
address_offset : 0x774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 15)
address_offset : 0x778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 15)
address_offset : 0x77C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 16)
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 16)
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 17)
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 17)
address_offset : 0x78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 18)
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 18)
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 19)
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 19)
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 20)
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 20)
address_offset : 0x7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 21)
address_offset : 0x7A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 21)
address_offset : 0x7AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 22)
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 22)
address_offset : 0x7B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Screening Type 2 Compare Word 0 Register (index = 23)
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASKVAL : Mask Value
bits : 0 - 15 (16 bit)
COMPVAL : Compare Value
bits : 16 - 31 (16 bit)
Screening Type 2 Compare Word 1 Register (index = 23)
address_offset : 0x7BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSVAL : Offset Value in Bytes
bits : 0 - 6 (7 bit)
OFFSSTRT : Ethernet Frame Offset Start
bits : 7 - 8 (2 bit)
Enumeration: OFFSSTRTSelect
0 : FRAMESTART
Offset from the start of the frame
1 : ETHERTYPE
Offset from the byte after the EtherType field
2 : IP
Offset from the byte after the IP header field
3 : TCP_UDP
Offset from the byte after the TCP/UDP header field
End of enumeration elements list.
Interrupt Status Register Priority Queue (index = 1) 0
address_offset : 0x7F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
Network Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MDIO : MDIO Input Status
bits : 1 - 1 (1 bit)
IDLE : PHY Management Logic Idle
bits : 2 - 2 (1 bit)
Hash Register Bottom
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Hash Address
bits : 0 - 31 (32 bit)
Hash Register Top
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Hash Address
bits : 0 - 31 (32 bit)
Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0
address_offset : 0x878 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBQBA : Transmit Buffer Queue Base Address
bits : 2 - 31 (30 bit)
Specific Address 1 Bottom Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 31 (32 bit)
Specific Address 1 Bottom Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADDR : Specific Address 1
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 1 Top Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1
bits : 0 - 15 (16 bit)
Specific Address 1 Top Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADDR : Specific Address 1
bits : 0 - 15 (16 bit)
access : read-write
Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0
address_offset : 0x8F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBQBA : Receive Buffer Queue Base Address
bits : 2 - 31 (30 bit)
Specific Address 2 Bottom Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADDR : Specific Address 2
bits : 0 - 31 (32 bit)
access : read-write
Receive Buffer Size Register Priority Queue (index = 1) 0
address_offset : 0x938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBS : Receive Buffer Size
bits : 0 - 15 (16 bit)
Specific Address 2 Top Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADDR : Specific Address 2
bits : 0 - 15 (16 bit)
access : read-write
Specific Address 3 Bottom Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADDR : Specific Address 3
bits : 0 - 31 (32 bit)
access : read-write
Specific Address 3 Top Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADDR : Specific Address 3
bits : 0 - 15 (16 bit)
access : read-write
Specific Address 4 Bottom Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADDR : Specific Address 4
bits : 0 - 31 (32 bit)
access : read-write
Screening Type 1 Register Priority Queue (index = 0) 0
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
DSTCM : Differentiated Services or Traffic Class Match
bits : 4 - 11 (8 bit)
UDPM : UDP Port Match
bits : 12 - 27 (16 bit)
DSTCE : Differentiated Services or Traffic Class Match Enable
bits : 28 - 28 (1 bit)
UDPE : UDP Port Match Enable
bits : 29 - 29 (1 bit)
Specific Address 4 Top Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ADDR : Specific Address 4
bits : 0 - 15 (16 bit)
access : read-write
Type ID Match 1 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID Match 1
bits : 0 - 15 (16 bit)
ENID1 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
Screening Type 2 Register Priority Queue (index = 0) 0
address_offset : 0xA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
Type ID Match 2 Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID Match 2
bits : 0 - 15 (16 bit)
ENID2 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
Type ID Match 3 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID Match 3
bits : 0 - 15 (16 bit)
ENID3 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
Type ID Match 4 Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TID : Type ID Match 4
bits : 0 - 15 (16 bit)
ENID4 : Enable Copying of TID Matched Frames
bits : 31 - 31 (1 bit)
Wake on LAN Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IP : ARP Request IP Address
bits : 0 - 15 (16 bit)
MAG : Magic Packet Event Enable
bits : 16 - 16 (1 bit)
ARP : ARP Request IP Address
bits : 17 - 17 (1 bit)
SA1 : Specific Address Register 1 Event Enable
bits : 18 - 18 (1 bit)
MTI : Multicast Hash Event Enable
bits : 19 - 19 (1 bit)
IPG Stretch Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FL : Frame Length
bits : 0 - 15 (16 bit)
Interrupt Status Register Priority Queue (index = 1) 0
address_offset : 0xBF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
Interrupt Enable Register Priority Queue (index = 1) 0
address_offset : 0xBF8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
User Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMII : Reduced MII Mode
bits : 0 - 0 (1 bit)
Stacked VLAN Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VLAN_TYPE : User Defined VLAN_TYPE Field
bits : 0 - 15 (16 bit)
ESVLAN : Enable Stacked VLAN Processing Mode
bits : 31 - 31 (1 bit)
Interrupt Disable Register Priority Queue (index = 1) 0
address_offset : 0xC38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
TFC : Transmit Frame Corruption Due to AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
Transmit PFC Pause Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEV : Priority Enable Vector
bits : 0 - 7 (8 bit)
PQ : Pause Quantum
bits : 8 - 15 (8 bit)
Interrupt Mask Register Priority Queue (index = 1) 0
address_offset : 0xC78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCOMP : Receive Complete
bits : 1 - 1 (1 bit)
RXUBR : RX Used Bit Read
bits : 2 - 2 (1 bit)
RLEX : Retry Limit Exceeded or Late Collision
bits : 5 - 5 (1 bit)
AHB : AHB Error
bits : 6 - 6 (1 bit)
TCOMP : Transmit Complete
bits : 7 - 7 (1 bit)
ROVR : Receive Overrun
bits : 10 - 10 (1 bit)
HRESP : HRESP Not OK
bits : 11 - 11 (1 bit)
Specific Address 1 Mask Bottom Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1 Mask
bits : 0 - 31 (32 bit)
Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0
address_offset : 0xCB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBQBA : Transmit Buffer Queue Base Address
bits : 2 - 31 (30 bit)
Specific Address 1 Mask Top Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Specific Address 1 Mask
bits : 0 - 15 (16 bit)
Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBQBA : Receive Buffer Queue Base Address
bits : 2 - 31 (30 bit)
1588 Timer Nanosecond Comparison Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NANOSEC : 1588 Timer Nanosecond Comparison Value
bits : 0 - 21 (22 bit)
Screening Type 2 Ethertype Register (index = 0) 0
address_offset : 0xDC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMPVAL : Ethertype Compare Value
bits : 0 - 15 (16 bit)
Receive Buffer Size Register Priority Queue (index = 1) 0
address_offset : 0xDD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RBS : Receive Buffer Size
bits : 0 - 15 (16 bit)
1588 Timer Second Comparison Low Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1588 Timer Second Comparison Value
bits : 0 - 31 (32 bit)
1588 Timer Second Comparison High Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1588 Timer Second Comparison Value
bits : 0 - 15 (16 bit)
PTP Event Frame Transmitted Seconds High Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 15 (16 bit)
PTP Event Frame Received Seconds High Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 15 (16 bit)
PTP Peer Event Frame Transmitted Seconds High Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 15 (16 bit)
Screening Type 1 Register Priority Queue (index = 0) 0
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
DSTCM : Differentiated Services or Traffic Class Match
bits : 4 - 11 (8 bit)
UDPM : UDP Port Match
bits : 12 - 27 (16 bit)
DSTCE : Differentiated Services or Traffic Class Match Enable
bits : 28 - 28 (1 bit)
UDPE : UDP Port Match Enable
bits : 29 - 29 (1 bit)
PTP Peer Event Frame Received Seconds High Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUD : Register Update
bits : 0 - 15 (16 bit)
Screening Type 2 Register Priority Queue (index = 0) 0
address_offset : 0xFC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QNB : Queue Number (0-2)
bits : 0 - 2 (3 bit)
VLANP : VLAN Priority
bits : 4 - 6 (3 bit)
VLANE : VLAN Enable
bits : 8 - 8 (1 bit)
I2ETH : Index of Screening Type 2 EtherType register x
bits : 9 - 11 (3 bit)
ETHE : EtherType Enable
bits : 12 - 12 (1 bit)
COMPA : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 13 - 17 (5 bit)
COMPAE : Compare A Enable
bits : 18 - 18 (1 bit)
COMPB : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 19 - 23 (5 bit)
COMPBE : Compare B Enable
bits : 24 - 24 (1 bit)
COMPC : Index of Screening Type 2 Compare Word 0/Word 1 register x
bits : 25 - 29 (5 bit)
COMPCE : Compare C Enable
bits : 30 - 30 (1 bit)
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