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PMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCER

PCER0

PCER1

PCDR1

PCSR1

PCK[2]

PCR

OCR

SLPWK_ER0

SLPWK_DR0

SLPWK_SR0

SLPWK_ASR0

PMMR

SLPWK_ER1

SLPWK_DR1

SLPWK_SR1

PCDR0

SLPWK_ASR1

SLPWK_AIPR

PCK[3]

PCSR0

PCK[4]

CKGR_UCKR

PCK[5]

CKGR_MOR

CKGR_MCFR

PCK[6]

CKGR_PLLAR

PCK[7]

MCKR

USB

SCDR

IER

IDR

SR

IMR

FSMR

FSPR

FOCR

SCSR

PCK[0]

PCK[1]

WPMR

WPSR


SCER

System Clock Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCER SCER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBCLK PCK0 PCK1 PCK2 PCK3 PCK4 PCK5 PCK6

USBCLK : Enable USB FS Clock
bits : 5 - 5 (1 bit)

PCK0 : Programmable Clock 0 Output Enable
bits : 8 - 8 (1 bit)

PCK1 : Programmable Clock 1 Output Enable
bits : 9 - 9 (1 bit)

PCK2 : Programmable Clock 2 Output Enable
bits : 10 - 10 (1 bit)

PCK3 : Programmable Clock 3 Output Enable
bits : 11 - 11 (1 bit)

PCK4 : Programmable Clock 4 Output Enable
bits : 12 - 12 (1 bit)

PCK5 : Programmable Clock 5 Output Enable
bits : 13 - 13 (1 bit)

PCK6 : Programmable Clock 6 Output Enable
bits : 14 - 14 (1 bit)


PCER0

Peripheral Clock Enable Register 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCER0 PCER0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID7 : Peripheral Clock 7 Enable
bits : 7 - 7 (1 bit)

PID8 : Peripheral Clock 8 Enable
bits : 8 - 8 (1 bit)

PID9 : Peripheral Clock 9 Enable
bits : 9 - 9 (1 bit)

PID10 : Peripheral Clock 10 Enable
bits : 10 - 10 (1 bit)

PID11 : Peripheral Clock 11 Enable
bits : 11 - 11 (1 bit)

PID12 : Peripheral Clock 12 Enable
bits : 12 - 12 (1 bit)

PID13 : Peripheral Clock 13 Enable
bits : 13 - 13 (1 bit)

PID14 : Peripheral Clock 14 Enable
bits : 14 - 14 (1 bit)

PID15 : Peripheral Clock 15 Enable
bits : 15 - 15 (1 bit)

PID16 : Peripheral Clock 16 Enable
bits : 16 - 16 (1 bit)

PID17 : Peripheral Clock 17 Enable
bits : 17 - 17 (1 bit)

PID18 : Peripheral Clock 18 Enable
bits : 18 - 18 (1 bit)

PID19 : Peripheral Clock 19 Enable
bits : 19 - 19 (1 bit)

PID20 : Peripheral Clock 20 Enable
bits : 20 - 20 (1 bit)

PID21 : Peripheral Clock 21 Enable
bits : 21 - 21 (1 bit)

PID22 : Peripheral Clock 22 Enable
bits : 22 - 22 (1 bit)

PID23 : Peripheral Clock 23 Enable
bits : 23 - 23 (1 bit)

PID24 : Peripheral Clock 24 Enable
bits : 24 - 24 (1 bit)

PID25 : Peripheral Clock 25 Enable
bits : 25 - 25 (1 bit)

PID26 : Peripheral Clock 26 Enable
bits : 26 - 26 (1 bit)

PID27 : Peripheral Clock 27 Enable
bits : 27 - 27 (1 bit)

PID28 : Peripheral Clock 28 Enable
bits : 28 - 28 (1 bit)

PID29 : Peripheral Clock 29 Enable
bits : 29 - 29 (1 bit)

PID30 : Peripheral Clock 30 Enable
bits : 30 - 30 (1 bit)

PID31 : Peripheral Clock 31 Enable
bits : 31 - 31 (1 bit)


PCER1

Peripheral Clock Enable Register 1
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCER1 PCER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID37 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID56 PID57 PID58 PID59 PID60

PID32 : Peripheral Clock 32 Enable
bits : 0 - 0 (1 bit)

PID33 : Peripheral Clock 33 Enable
bits : 1 - 1 (1 bit)

PID34 : Peripheral Clock 34 Enable
bits : 2 - 2 (1 bit)

PID35 : Peripheral Clock 35 Enable
bits : 3 - 3 (1 bit)

PID37 : Peripheral Clock 37 Enable
bits : 5 - 5 (1 bit)

PID39 : Peripheral Clock 39 Enable
bits : 7 - 7 (1 bit)

PID40 : Peripheral Clock 40 Enable
bits : 8 - 8 (1 bit)

PID41 : Peripheral Clock 41 Enable
bits : 9 - 9 (1 bit)

PID42 : Peripheral Clock 42 Enable
bits : 10 - 10 (1 bit)

PID43 : Peripheral Clock 43 Enable
bits : 11 - 11 (1 bit)

PID44 : Peripheral Clock 44 Enable
bits : 12 - 12 (1 bit)

PID45 : Peripheral Clock 45 Enable
bits : 13 - 13 (1 bit)

PID46 : Peripheral Clock 46 Enable
bits : 14 - 14 (1 bit)

PID47 : Peripheral Clock 47 Enable
bits : 15 - 15 (1 bit)

PID48 : Peripheral Clock 48 Enable
bits : 16 - 16 (1 bit)

PID49 : Peripheral Clock 49 Enable
bits : 17 - 17 (1 bit)

PID50 : Peripheral Clock 50 Enable
bits : 18 - 18 (1 bit)

PID51 : Peripheral Clock 51 Enable
bits : 19 - 19 (1 bit)

PID52 : Peripheral Clock 52 Enable
bits : 20 - 20 (1 bit)

PID53 : Peripheral Clock 53 Enable
bits : 21 - 21 (1 bit)

PID56 : Peripheral Clock 56 Enable
bits : 24 - 24 (1 bit)

PID57 : Peripheral Clock 57 Enable
bits : 25 - 25 (1 bit)

PID58 : Peripheral Clock 58 Enable
bits : 26 - 26 (1 bit)

PID59 : Peripheral Clock 59 Enable
bits : 27 - 27 (1 bit)

PID60 : Peripheral Clock 60 Enable
bits : 28 - 28 (1 bit)


PCDR1

Peripheral Clock Disable Register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCDR1 PCDR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID37 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID56 PID57 PID58 PID59 PID60

PID32 : Peripheral Clock 32 Disable
bits : 0 - 0 (1 bit)

PID33 : Peripheral Clock 33 Disable
bits : 1 - 1 (1 bit)

PID34 : Peripheral Clock 34 Disable
bits : 2 - 2 (1 bit)

PID35 : Peripheral Clock 35 Disable
bits : 3 - 3 (1 bit)

PID37 : Peripheral Clock 37 Disable
bits : 5 - 5 (1 bit)

PID39 : Peripheral Clock 39 Disable
bits : 7 - 7 (1 bit)

PID40 : Peripheral Clock 40 Disable
bits : 8 - 8 (1 bit)

PID41 : Peripheral Clock 41 Disable
bits : 9 - 9 (1 bit)

PID42 : Peripheral Clock 42 Disable
bits : 10 - 10 (1 bit)

PID43 : Peripheral Clock 43 Disable
bits : 11 - 11 (1 bit)

PID44 : Peripheral Clock 44 Disable
bits : 12 - 12 (1 bit)

PID45 : Peripheral Clock 45 Disable
bits : 13 - 13 (1 bit)

PID46 : Peripheral Clock 46 Disable
bits : 14 - 14 (1 bit)

PID47 : Peripheral Clock 47 Disable
bits : 15 - 15 (1 bit)

PID48 : Peripheral Clock 48 Disable
bits : 16 - 16 (1 bit)

PID49 : Peripheral Clock 49 Disable
bits : 17 - 17 (1 bit)

PID50 : Peripheral Clock 50 Disable
bits : 18 - 18 (1 bit)

PID51 : Peripheral Clock 51 Disable
bits : 19 - 19 (1 bit)

PID52 : Peripheral Clock 52 Disable
bits : 20 - 20 (1 bit)

PID53 : Peripheral Clock 53 Disable
bits : 21 - 21 (1 bit)

PID56 : Peripheral Clock 56 Disable
bits : 24 - 24 (1 bit)

PID57 : Peripheral Clock 57 Disable
bits : 25 - 25 (1 bit)

PID58 : Peripheral Clock 58 Disable
bits : 26 - 26 (1 bit)

PID59 : Peripheral Clock 59 Disable
bits : 27 - 27 (1 bit)

PID60 : Peripheral Clock 60 Disable
bits : 28 - 28 (1 bit)


PCSR1

Peripheral Clock Status Register 1
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCSR1 PCSR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID37 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID56 PID57 PID58 PID59 PID60

PID32 : Peripheral Clock 32 Status
bits : 0 - 0 (1 bit)

PID33 : Peripheral Clock 33 Status
bits : 1 - 1 (1 bit)

PID34 : Peripheral Clock 34 Status
bits : 2 - 2 (1 bit)

PID35 : Peripheral Clock 35 Status
bits : 3 - 3 (1 bit)

PID37 : Peripheral Clock 37 Status
bits : 5 - 5 (1 bit)

PID39 : Peripheral Clock 39 Status
bits : 7 - 7 (1 bit)

PID40 : Peripheral Clock 40 Status
bits : 8 - 8 (1 bit)

PID41 : Peripheral Clock 41 Status
bits : 9 - 9 (1 bit)

PID42 : Peripheral Clock 42 Status
bits : 10 - 10 (1 bit)

PID43 : Peripheral Clock 43 Status
bits : 11 - 11 (1 bit)

PID44 : Peripheral Clock 44 Status
bits : 12 - 12 (1 bit)

PID45 : Peripheral Clock 45 Status
bits : 13 - 13 (1 bit)

PID46 : Peripheral Clock 46 Status
bits : 14 - 14 (1 bit)

PID47 : Peripheral Clock 47 Status
bits : 15 - 15 (1 bit)

PID48 : Peripheral Clock 48 Status
bits : 16 - 16 (1 bit)

PID49 : Peripheral Clock 49 Status
bits : 17 - 17 (1 bit)

PID50 : Peripheral Clock 50 Status
bits : 18 - 18 (1 bit)

PID51 : Peripheral Clock 51 Status
bits : 19 - 19 (1 bit)

PID52 : Peripheral Clock 52 Status
bits : 20 - 20 (1 bit)

PID53 : Peripheral Clock 53 Status
bits : 21 - 21 (1 bit)

PID56 : Peripheral Clock 56 Status
bits : 24 - 24 (1 bit)

PID57 : Peripheral Clock 57 Status
bits : 25 - 25 (1 bit)

PID58 : Peripheral Clock 58 Status
bits : 26 - 26 (1 bit)

PID59 : Peripheral Clock 59 Status
bits : 27 - 27 (1 bit)

PID60 : Peripheral Clock 60 Status
bits : 28 - 28 (1 bit)


PCK[2]

Programmable Clock Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[2] PCK[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Programmable Clock Source Selection
bits : 0 - 2 (3 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

SLCK is selected

1 : MAIN_CLK

MAINCK is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLLCKDIV is selected

4 : MCK

MCK is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 11 (8 bit)


PCR

Peripheral Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCR PCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID GCLKCSS CMD GCLKDIV EN GCLKEN

PID : Peripheral ID
bits : 0 - 6 (7 bit)

GCLKCSS : Generic Clock Source Selection
bits : 8 - 10 (3 bit)

Enumeration: GCLKCSSSelect

0 : SLOW_CLK

Slow clock is selected

1 : MAIN_CLK

Main clock is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLL Clock is selected

4 : MCK_CLK

Master Clock is selected

End of enumeration elements list.

CMD : Command
bits : 12 - 12 (1 bit)

GCLKDIV : Generic Clock Division Ratio
bits : 20 - 27 (8 bit)

EN : Enable
bits : 28 - 28 (1 bit)

GCLKEN : Generic Clock Enable
bits : 29 - 29 (1 bit)


OCR

Oscillator Calibration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCR OCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL4 SEL4 CAL8 SEL8 CAL12 SEL12

CAL4 : Main RC Oscillator Calibration Bits for 4 MHz
bits : 0 - 6 (7 bit)

SEL4 : Selection of Main RC Oscillator Calibration Bits for 4 MHz
bits : 7 - 7 (1 bit)

CAL8 : Main RC Oscillator Calibration Bits for 8 MHz
bits : 8 - 14 (7 bit)

SEL8 : Selection of Main RC Oscillator Calibration Bits for 8 MHz
bits : 15 - 15 (1 bit)

CAL12 : Main RC Oscillator Calibration Bits for 12 MHz
bits : 16 - 22 (7 bit)

SEL12 : Selection of Main RC Oscillator Calibration Bits for 12 MHz
bits : 23 - 23 (1 bit)


SLPWK_ER0

SleepWalking Enable Register 0
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_ER0 SLPWK_ER0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID7 : Peripheral 7 SleepWalking Enable
bits : 7 - 7 (1 bit)

PID8 : Peripheral 8 SleepWalking Enable
bits : 8 - 8 (1 bit)

PID9 : Peripheral 9 SleepWalking Enable
bits : 9 - 9 (1 bit)

PID10 : Peripheral 10 SleepWalking Enable
bits : 10 - 10 (1 bit)

PID11 : Peripheral 11 SleepWalking Enable
bits : 11 - 11 (1 bit)

PID12 : Peripheral 12 SleepWalking Enable
bits : 12 - 12 (1 bit)

PID13 : Peripheral 13 SleepWalking Enable
bits : 13 - 13 (1 bit)

PID14 : Peripheral 14 SleepWalking Enable
bits : 14 - 14 (1 bit)

PID15 : Peripheral 15 SleepWalking Enable
bits : 15 - 15 (1 bit)

PID16 : Peripheral 16 SleepWalking Enable
bits : 16 - 16 (1 bit)

PID17 : Peripheral 17 SleepWalking Enable
bits : 17 - 17 (1 bit)

PID18 : Peripheral 18 SleepWalking Enable
bits : 18 - 18 (1 bit)

PID19 : Peripheral 19 SleepWalking Enable
bits : 19 - 19 (1 bit)

PID20 : Peripheral 20 SleepWalking Enable
bits : 20 - 20 (1 bit)

PID21 : Peripheral 21 SleepWalking Enable
bits : 21 - 21 (1 bit)

PID22 : Peripheral 22 SleepWalking Enable
bits : 22 - 22 (1 bit)

PID23 : Peripheral 23 SleepWalking Enable
bits : 23 - 23 (1 bit)

PID24 : Peripheral 24 SleepWalking Enable
bits : 24 - 24 (1 bit)

PID25 : Peripheral 25 SleepWalking Enable
bits : 25 - 25 (1 bit)

PID26 : Peripheral 26 SleepWalking Enable
bits : 26 - 26 (1 bit)

PID27 : Peripheral 27 SleepWalking Enable
bits : 27 - 27 (1 bit)

PID28 : Peripheral 28 SleepWalking Enable
bits : 28 - 28 (1 bit)

PID29 : Peripheral 29 SleepWalking Enable
bits : 29 - 29 (1 bit)

PID30 : Peripheral 30 SleepWalking Enable
bits : 30 - 30 (1 bit)

PID31 : Peripheral 31 SleepWalking Enable
bits : 31 - 31 (1 bit)


SLPWK_DR0

SleepWalking Disable Register 0
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_DR0 SLPWK_DR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID7 : Peripheral 7 SleepWalking Disable
bits : 7 - 7 (1 bit)

PID8 : Peripheral 8 SleepWalking Disable
bits : 8 - 8 (1 bit)

PID9 : Peripheral 9 SleepWalking Disable
bits : 9 - 9 (1 bit)

PID10 : Peripheral 10 SleepWalking Disable
bits : 10 - 10 (1 bit)

PID11 : Peripheral 11 SleepWalking Disable
bits : 11 - 11 (1 bit)

PID12 : Peripheral 12 SleepWalking Disable
bits : 12 - 12 (1 bit)

PID13 : Peripheral 13 SleepWalking Disable
bits : 13 - 13 (1 bit)

PID14 : Peripheral 14 SleepWalking Disable
bits : 14 - 14 (1 bit)

PID15 : Peripheral 15 SleepWalking Disable
bits : 15 - 15 (1 bit)

PID16 : Peripheral 16 SleepWalking Disable
bits : 16 - 16 (1 bit)

PID17 : Peripheral 17 SleepWalking Disable
bits : 17 - 17 (1 bit)

PID18 : Peripheral 18 SleepWalking Disable
bits : 18 - 18 (1 bit)

PID19 : Peripheral 19 SleepWalking Disable
bits : 19 - 19 (1 bit)

PID20 : Peripheral 20 SleepWalking Disable
bits : 20 - 20 (1 bit)

PID21 : Peripheral 21 SleepWalking Disable
bits : 21 - 21 (1 bit)

PID22 : Peripheral 22 SleepWalking Disable
bits : 22 - 22 (1 bit)

PID23 : Peripheral 23 SleepWalking Disable
bits : 23 - 23 (1 bit)

PID24 : Peripheral 24 SleepWalking Disable
bits : 24 - 24 (1 bit)

PID25 : Peripheral 25 SleepWalking Disable
bits : 25 - 25 (1 bit)

PID26 : Peripheral 26 SleepWalking Disable
bits : 26 - 26 (1 bit)

PID27 : Peripheral 27 SleepWalking Disable
bits : 27 - 27 (1 bit)

PID28 : Peripheral 28 SleepWalking Disable
bits : 28 - 28 (1 bit)

PID29 : Peripheral 29 SleepWalking Disable
bits : 29 - 29 (1 bit)

PID30 : Peripheral 30 SleepWalking Disable
bits : 30 - 30 (1 bit)

PID31 : Peripheral 31 SleepWalking Disable
bits : 31 - 31 (1 bit)


SLPWK_SR0

SleepWalking Status Register 0
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_SR0 SLPWK_SR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID7 : Peripheral 7 SleepWalking Status
bits : 7 - 7 (1 bit)

PID8 : Peripheral 8 SleepWalking Status
bits : 8 - 8 (1 bit)

PID9 : Peripheral 9 SleepWalking Status
bits : 9 - 9 (1 bit)

PID10 : Peripheral 10 SleepWalking Status
bits : 10 - 10 (1 bit)

PID11 : Peripheral 11 SleepWalking Status
bits : 11 - 11 (1 bit)

PID12 : Peripheral 12 SleepWalking Status
bits : 12 - 12 (1 bit)

PID13 : Peripheral 13 SleepWalking Status
bits : 13 - 13 (1 bit)

PID14 : Peripheral 14 SleepWalking Status
bits : 14 - 14 (1 bit)

PID15 : Peripheral 15 SleepWalking Status
bits : 15 - 15 (1 bit)

PID16 : Peripheral 16 SleepWalking Status
bits : 16 - 16 (1 bit)

PID17 : Peripheral 17 SleepWalking Status
bits : 17 - 17 (1 bit)

PID18 : Peripheral 18 SleepWalking Status
bits : 18 - 18 (1 bit)

PID19 : Peripheral 19 SleepWalking Status
bits : 19 - 19 (1 bit)

PID20 : Peripheral 20 SleepWalking Status
bits : 20 - 20 (1 bit)

PID21 : Peripheral 21 SleepWalking Status
bits : 21 - 21 (1 bit)

PID22 : Peripheral 22 SleepWalking Status
bits : 22 - 22 (1 bit)

PID23 : Peripheral 23 SleepWalking Status
bits : 23 - 23 (1 bit)

PID24 : Peripheral 24 SleepWalking Status
bits : 24 - 24 (1 bit)

PID25 : Peripheral 25 SleepWalking Status
bits : 25 - 25 (1 bit)

PID26 : Peripheral 26 SleepWalking Status
bits : 26 - 26 (1 bit)

PID27 : Peripheral 27 SleepWalking Status
bits : 27 - 27 (1 bit)

PID28 : Peripheral 28 SleepWalking Status
bits : 28 - 28 (1 bit)

PID29 : Peripheral 29 SleepWalking Status
bits : 29 - 29 (1 bit)

PID30 : Peripheral 30 SleepWalking Status
bits : 30 - 30 (1 bit)

PID31 : Peripheral 31 SleepWalking Status
bits : 31 - 31 (1 bit)


SLPWK_ASR0

SleepWalking Activity Status Register 0
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_ASR0 SLPWK_ASR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID7 : Peripheral 7 Activity Status
bits : 7 - 7 (1 bit)

PID8 : Peripheral 8 Activity Status
bits : 8 - 8 (1 bit)

PID9 : Peripheral 9 Activity Status
bits : 9 - 9 (1 bit)

PID10 : Peripheral 10 Activity Status
bits : 10 - 10 (1 bit)

PID11 : Peripheral 11 Activity Status
bits : 11 - 11 (1 bit)

PID12 : Peripheral 12 Activity Status
bits : 12 - 12 (1 bit)

PID13 : Peripheral 13 Activity Status
bits : 13 - 13 (1 bit)

PID14 : Peripheral 14 Activity Status
bits : 14 - 14 (1 bit)

PID15 : Peripheral 15 Activity Status
bits : 15 - 15 (1 bit)

PID16 : Peripheral 16 Activity Status
bits : 16 - 16 (1 bit)

PID17 : Peripheral 17 Activity Status
bits : 17 - 17 (1 bit)

PID18 : Peripheral 18 Activity Status
bits : 18 - 18 (1 bit)

PID19 : Peripheral 19 Activity Status
bits : 19 - 19 (1 bit)

PID20 : Peripheral 20 Activity Status
bits : 20 - 20 (1 bit)

PID21 : Peripheral 21 Activity Status
bits : 21 - 21 (1 bit)

PID22 : Peripheral 22 Activity Status
bits : 22 - 22 (1 bit)

PID23 : Peripheral 23 Activity Status
bits : 23 - 23 (1 bit)

PID24 : Peripheral 24 Activity Status
bits : 24 - 24 (1 bit)

PID25 : Peripheral 25 Activity Status
bits : 25 - 25 (1 bit)

PID26 : Peripheral 26 Activity Status
bits : 26 - 26 (1 bit)

PID27 : Peripheral 27 Activity Status
bits : 27 - 27 (1 bit)

PID28 : Peripheral 28 Activity Status
bits : 28 - 28 (1 bit)

PID29 : Peripheral 29 Activity Status
bits : 29 - 29 (1 bit)

PID30 : Peripheral 30 Activity Status
bits : 30 - 30 (1 bit)

PID31 : Peripheral 31 Activity Status
bits : 31 - 31 (1 bit)


PMMR

PLL Maximum Multiplier Value Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PMMR PMMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLA_MMAX

PLLA_MMAX : PLLA Maximum Allowed Multiplier Value
bits : 0 - 10 (11 bit)


SLPWK_ER1

SleepWalking Enable Register 1
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_ER1 SLPWK_ER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID37 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID56 PID57 PID58 PID59 PID60

PID32 : Peripheral 32 SleepWalking Enable
bits : 0 - 0 (1 bit)

PID33 : Peripheral 33 SleepWalking Enable
bits : 1 - 1 (1 bit)

PID34 : Peripheral 34 SleepWalking Enable
bits : 2 - 2 (1 bit)

PID35 : Peripheral 35 SleepWalking Enable
bits : 3 - 3 (1 bit)

PID37 : Peripheral 37 SleepWalking Enable
bits : 5 - 5 (1 bit)

PID39 : Peripheral 39 SleepWalking Enable
bits : 7 - 7 (1 bit)

PID40 : Peripheral 40 SleepWalking Enable
bits : 8 - 8 (1 bit)

PID41 : Peripheral 41 SleepWalking Enable
bits : 9 - 9 (1 bit)

PID42 : Peripheral 42 SleepWalking Enable
bits : 10 - 10 (1 bit)

PID43 : Peripheral 43 SleepWalking Enable
bits : 11 - 11 (1 bit)

PID44 : Peripheral 44 SleepWalking Enable
bits : 12 - 12 (1 bit)

PID45 : Peripheral 45 SleepWalking Enable
bits : 13 - 13 (1 bit)

PID46 : Peripheral 46 SleepWalking Enable
bits : 14 - 14 (1 bit)

PID47 : Peripheral 47 SleepWalking Enable
bits : 15 - 15 (1 bit)

PID48 : Peripheral 48 SleepWalking Enable
bits : 16 - 16 (1 bit)

PID49 : Peripheral 49 SleepWalking Enable
bits : 17 - 17 (1 bit)

PID50 : Peripheral 50 SleepWalking Enable
bits : 18 - 18 (1 bit)

PID51 : Peripheral 51 SleepWalking Enable
bits : 19 - 19 (1 bit)

PID52 : Peripheral 52 SleepWalking Enable
bits : 20 - 20 (1 bit)

PID53 : Peripheral 53 SleepWalking Enable
bits : 21 - 21 (1 bit)

PID56 : Peripheral 56 SleepWalking Enable
bits : 24 - 24 (1 bit)

PID57 : Peripheral 57 SleepWalking Enable
bits : 25 - 25 (1 bit)

PID58 : Peripheral 58 SleepWalking Enable
bits : 26 - 26 (1 bit)

PID59 : Peripheral 59 SleepWalking Enable
bits : 27 - 27 (1 bit)

PID60 : Peripheral 60 SleepWalking Enable
bits : 28 - 28 (1 bit)


SLPWK_DR1

SleepWalking Disable Register 1
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_DR1 SLPWK_DR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID37 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID56 PID57 PID58 PID59 PID60

PID32 : Peripheral 32 SleepWalking Disable
bits : 0 - 0 (1 bit)

PID33 : Peripheral 33 SleepWalking Disable
bits : 1 - 1 (1 bit)

PID34 : Peripheral 34 SleepWalking Disable
bits : 2 - 2 (1 bit)

PID35 : Peripheral 35 SleepWalking Disable
bits : 3 - 3 (1 bit)

PID37 : Peripheral 37 SleepWalking Disable
bits : 5 - 5 (1 bit)

PID39 : Peripheral 39 SleepWalking Disable
bits : 7 - 7 (1 bit)

PID40 : Peripheral 40 SleepWalking Disable
bits : 8 - 8 (1 bit)

PID41 : Peripheral 41 SleepWalking Disable
bits : 9 - 9 (1 bit)

PID42 : Peripheral 42 SleepWalking Disable
bits : 10 - 10 (1 bit)

PID43 : Peripheral 43 SleepWalking Disable
bits : 11 - 11 (1 bit)

PID44 : Peripheral 44 SleepWalking Disable
bits : 12 - 12 (1 bit)

PID45 : Peripheral 45 SleepWalking Disable
bits : 13 - 13 (1 bit)

PID46 : Peripheral 46 SleepWalking Disable
bits : 14 - 14 (1 bit)

PID47 : Peripheral 47 SleepWalking Disable
bits : 15 - 15 (1 bit)

PID48 : Peripheral 48 SleepWalking Disable
bits : 16 - 16 (1 bit)

PID49 : Peripheral 49 SleepWalking Disable
bits : 17 - 17 (1 bit)

PID50 : Peripheral 50 SleepWalking Disable
bits : 18 - 18 (1 bit)

PID51 : Peripheral 51 SleepWalking Disable
bits : 19 - 19 (1 bit)

PID52 : Peripheral 52 SleepWalking Disable
bits : 20 - 20 (1 bit)

PID53 : Peripheral 53 SleepWalking Disable
bits : 21 - 21 (1 bit)

PID56 : Peripheral 56 SleepWalking Disable
bits : 24 - 24 (1 bit)

PID57 : Peripheral 57 SleepWalking Disable
bits : 25 - 25 (1 bit)

PID58 : Peripheral 58 SleepWalking Disable
bits : 26 - 26 (1 bit)

PID59 : Peripheral 59 SleepWalking Disable
bits : 27 - 27 (1 bit)

PID60 : Peripheral 60 SleepWalking Disable
bits : 28 - 28 (1 bit)


SLPWK_SR1

SleepWalking Status Register 1
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_SR1 SLPWK_SR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID37 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID56 PID57 PID58 PID59 PID60

PID32 : Peripheral 32 SleepWalking Status
bits : 0 - 0 (1 bit)

PID33 : Peripheral 33 SleepWalking Status
bits : 1 - 1 (1 bit)

PID34 : Peripheral 34 SleepWalking Status
bits : 2 - 2 (1 bit)

PID35 : Peripheral 35 SleepWalking Status
bits : 3 - 3 (1 bit)

PID37 : Peripheral 37 SleepWalking Status
bits : 5 - 5 (1 bit)

PID39 : Peripheral 39 SleepWalking Status
bits : 7 - 7 (1 bit)

PID40 : Peripheral 40 SleepWalking Status
bits : 8 - 8 (1 bit)

PID41 : Peripheral 41 SleepWalking Status
bits : 9 - 9 (1 bit)

PID42 : Peripheral 42 SleepWalking Status
bits : 10 - 10 (1 bit)

PID43 : Peripheral 43 SleepWalking Status
bits : 11 - 11 (1 bit)

PID44 : Peripheral 44 SleepWalking Status
bits : 12 - 12 (1 bit)

PID45 : Peripheral 45 SleepWalking Status
bits : 13 - 13 (1 bit)

PID46 : Peripheral 46 SleepWalking Status
bits : 14 - 14 (1 bit)

PID47 : Peripheral 47 SleepWalking Status
bits : 15 - 15 (1 bit)

PID48 : Peripheral 48 SleepWalking Status
bits : 16 - 16 (1 bit)

PID49 : Peripheral 49 SleepWalking Status
bits : 17 - 17 (1 bit)

PID50 : Peripheral 50 SleepWalking Status
bits : 18 - 18 (1 bit)

PID51 : Peripheral 51 SleepWalking Status
bits : 19 - 19 (1 bit)

PID52 : Peripheral 52 SleepWalking Status
bits : 20 - 20 (1 bit)

PID53 : Peripheral 53 SleepWalking Status
bits : 21 - 21 (1 bit)

PID56 : Peripheral 56 SleepWalking Status
bits : 24 - 24 (1 bit)

PID57 : Peripheral 57 SleepWalking Status
bits : 25 - 25 (1 bit)

PID58 : Peripheral 58 SleepWalking Status
bits : 26 - 26 (1 bit)

PID59 : Peripheral 59 SleepWalking Status
bits : 27 - 27 (1 bit)

PID60 : Peripheral 60 SleepWalking Status
bits : 28 - 28 (1 bit)


PCDR0

Peripheral Clock Disable Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PCDR0 PCDR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID7 : Peripheral Clock 7 Disable
bits : 7 - 7 (1 bit)

PID8 : Peripheral Clock 8 Disable
bits : 8 - 8 (1 bit)

PID9 : Peripheral Clock 9 Disable
bits : 9 - 9 (1 bit)

PID10 : Peripheral Clock 10 Disable
bits : 10 - 10 (1 bit)

PID11 : Peripheral Clock 11 Disable
bits : 11 - 11 (1 bit)

PID12 : Peripheral Clock 12 Disable
bits : 12 - 12 (1 bit)

PID13 : Peripheral Clock 13 Disable
bits : 13 - 13 (1 bit)

PID14 : Peripheral Clock 14 Disable
bits : 14 - 14 (1 bit)

PID15 : Peripheral Clock 15 Disable
bits : 15 - 15 (1 bit)

PID16 : Peripheral Clock 16 Disable
bits : 16 - 16 (1 bit)

PID17 : Peripheral Clock 17 Disable
bits : 17 - 17 (1 bit)

PID18 : Peripheral Clock 18 Disable
bits : 18 - 18 (1 bit)

PID19 : Peripheral Clock 19 Disable
bits : 19 - 19 (1 bit)

PID20 : Peripheral Clock 20 Disable
bits : 20 - 20 (1 bit)

PID21 : Peripheral Clock 21 Disable
bits : 21 - 21 (1 bit)

PID22 : Peripheral Clock 22 Disable
bits : 22 - 22 (1 bit)

PID23 : Peripheral Clock 23 Disable
bits : 23 - 23 (1 bit)

PID24 : Peripheral Clock 24 Disable
bits : 24 - 24 (1 bit)

PID25 : Peripheral Clock 25 Disable
bits : 25 - 25 (1 bit)

PID26 : Peripheral Clock 26 Disable
bits : 26 - 26 (1 bit)

PID27 : Peripheral Clock 27 Disable
bits : 27 - 27 (1 bit)

PID28 : Peripheral Clock 28 Disable
bits : 28 - 28 (1 bit)

PID29 : Peripheral Clock 29 Disable
bits : 29 - 29 (1 bit)

PID30 : Peripheral Clock 30 Disable
bits : 30 - 30 (1 bit)

PID31 : Peripheral Clock 31 Disable
bits : 31 - 31 (1 bit)


SLPWK_ASR1

SleepWalking Activity Status Register 1
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_ASR1 SLPWK_ASR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID32 PID33 PID34 PID35 PID37 PID39 PID40 PID41 PID42 PID43 PID44 PID45 PID46 PID47 PID48 PID49 PID50 PID51 PID52 PID53 PID56 PID57 PID58 PID59 PID60

PID32 : Peripheral 32 Activity Status
bits : 0 - 0 (1 bit)

PID33 : Peripheral 33 Activity Status
bits : 1 - 1 (1 bit)

PID34 : Peripheral 34 Activity Status
bits : 2 - 2 (1 bit)

PID35 : Peripheral 35 Activity Status
bits : 3 - 3 (1 bit)

PID37 : Peripheral 37 Activity Status
bits : 5 - 5 (1 bit)

PID39 : Peripheral 39 Activity Status
bits : 7 - 7 (1 bit)

PID40 : Peripheral 40 Activity Status
bits : 8 - 8 (1 bit)

PID41 : Peripheral 41 Activity Status
bits : 9 - 9 (1 bit)

PID42 : Peripheral 42 Activity Status
bits : 10 - 10 (1 bit)

PID43 : Peripheral 43 Activity Status
bits : 11 - 11 (1 bit)

PID44 : Peripheral 44 Activity Status
bits : 12 - 12 (1 bit)

PID45 : Peripheral 45 Activity Status
bits : 13 - 13 (1 bit)

PID46 : Peripheral 46 Activity Status
bits : 14 - 14 (1 bit)

PID47 : Peripheral 47 Activity Status
bits : 15 - 15 (1 bit)

PID48 : Peripheral 48 Activity Status
bits : 16 - 16 (1 bit)

PID49 : Peripheral 49 Activity Status
bits : 17 - 17 (1 bit)

PID50 : Peripheral 50 Activity Status
bits : 18 - 18 (1 bit)

PID51 : Peripheral 51 Activity Status
bits : 19 - 19 (1 bit)

PID52 : Peripheral 52 Activity Status
bits : 20 - 20 (1 bit)

PID53 : Peripheral 53 Activity Status
bits : 21 - 21 (1 bit)

PID56 : Peripheral 56 Activity Status
bits : 24 - 24 (1 bit)

PID57 : Peripheral 57 Activity Status
bits : 25 - 25 (1 bit)

PID58 : Peripheral 58 Activity Status
bits : 26 - 26 (1 bit)

PID59 : Peripheral 59 Activity Status
bits : 27 - 27 (1 bit)

PID60 : Peripheral 60 Activity Status
bits : 28 - 28 (1 bit)


SLPWK_AIPR

SleepWalking Activity In Progress Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SLPWK_AIPR SLPWK_AIPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIP

AIP : Activity In Progress
bits : 0 - 0 (1 bit)


PCK[3]

Programmable Clock Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[3] PCK[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Programmable Clock Source Selection
bits : 0 - 2 (3 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

SLCK is selected

1 : MAIN_CLK

MAINCK is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLLCKDIV is selected

4 : MCK

MCK is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 11 (8 bit)


PCSR0

Peripheral Clock Status Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCSR0 PCSR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PID7 PID8 PID9 PID10 PID11 PID12 PID13 PID14 PID15 PID16 PID17 PID18 PID19 PID20 PID21 PID22 PID23 PID24 PID25 PID26 PID27 PID28 PID29 PID30 PID31

PID7 : Peripheral Clock 7 Status
bits : 7 - 7 (1 bit)

PID8 : Peripheral Clock 8 Status
bits : 8 - 8 (1 bit)

PID9 : Peripheral Clock 9 Status
bits : 9 - 9 (1 bit)

PID10 : Peripheral Clock 10 Status
bits : 10 - 10 (1 bit)

PID11 : Peripheral Clock 11 Status
bits : 11 - 11 (1 bit)

PID12 : Peripheral Clock 12 Status
bits : 12 - 12 (1 bit)

PID13 : Peripheral Clock 13 Status
bits : 13 - 13 (1 bit)

PID14 : Peripheral Clock 14 Status
bits : 14 - 14 (1 bit)

PID15 : Peripheral Clock 15 Status
bits : 15 - 15 (1 bit)

PID16 : Peripheral Clock 16 Status
bits : 16 - 16 (1 bit)

PID17 : Peripheral Clock 17 Status
bits : 17 - 17 (1 bit)

PID18 : Peripheral Clock 18 Status
bits : 18 - 18 (1 bit)

PID19 : Peripheral Clock 19 Status
bits : 19 - 19 (1 bit)

PID20 : Peripheral Clock 20 Status
bits : 20 - 20 (1 bit)

PID21 : Peripheral Clock 21 Status
bits : 21 - 21 (1 bit)

PID22 : Peripheral Clock 22 Status
bits : 22 - 22 (1 bit)

PID23 : Peripheral Clock 23 Status
bits : 23 - 23 (1 bit)

PID24 : Peripheral Clock 24 Status
bits : 24 - 24 (1 bit)

PID25 : Peripheral Clock 25 Status
bits : 25 - 25 (1 bit)

PID26 : Peripheral Clock 26 Status
bits : 26 - 26 (1 bit)

PID27 : Peripheral Clock 27 Status
bits : 27 - 27 (1 bit)

PID28 : Peripheral Clock 28 Status
bits : 28 - 28 (1 bit)

PID29 : Peripheral Clock 29 Status
bits : 29 - 29 (1 bit)

PID30 : Peripheral Clock 30 Status
bits : 30 - 30 (1 bit)

PID31 : Peripheral Clock 31 Status
bits : 31 - 31 (1 bit)


PCK[4]

Programmable Clock Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[4] PCK[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Programmable Clock Source Selection
bits : 0 - 2 (3 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

SLCK is selected

1 : MAIN_CLK

MAINCK is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLLCKDIV is selected

4 : MCK

MCK is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 11 (8 bit)


CKGR_UCKR

UTMI Clock Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKGR_UCKR CKGR_UCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPLLEN UPLLCOUNT

UPLLEN : UTMI PLL Enable
bits : 16 - 16 (1 bit)

UPLLCOUNT : UTMI PLL Start-up Time
bits : 20 - 23 (4 bit)


PCK[5]

Programmable Clock Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[5] PCK[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Programmable Clock Source Selection
bits : 0 - 2 (3 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

SLCK is selected

1 : MAIN_CLK

MAINCK is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLLCKDIV is selected

4 : MCK

MCK is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 11 (8 bit)


CKGR_MOR

Main Oscillator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKGR_MOR CKGR_MOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTEN MOSCXTBY WAITMODE MOSCRCEN MOSCRCF MOSCXTST KEY MOSCSEL CFDEN XT32KFME

MOSCXTEN : Main Crystal Oscillator Enable
bits : 0 - 0 (1 bit)

MOSCXTBY : Main Crystal Oscillator Bypass
bits : 1 - 1 (1 bit)

WAITMODE : Wait Mode Command (Write-only)
bits : 2 - 2 (1 bit)

MOSCRCEN : Main RC Oscillator Enable
bits : 3 - 3 (1 bit)

MOSCRCF : Main RC Oscillator Frequency Selection
bits : 4 - 6 (3 bit)

Enumeration: MOSCRCFSelect

0 : _4_MHz

The RC oscillator frequency is at 4 MHz

1 : _8_MHz

The RC oscillator frequency is at 8 MHz

2 : _12_MHz

The RC oscillator frequency is at 12 MHz

End of enumeration elements list.

MOSCXTST : Main Crystal Oscillator Startup Time
bits : 8 - 15 (8 bit)

KEY : Write Access Password
bits : 16 - 23 (8 bit)

Enumeration: KEYSelect

55 : PASSWD

Writing any other value in this field aborts the write operation.Always reads as 0.

End of enumeration elements list.

MOSCSEL : Main Clock Oscillator Selection
bits : 24 - 24 (1 bit)

CFDEN : Clock Failure Detector Enable
bits : 25 - 25 (1 bit)

XT32KFME : 32.768 kHz Crystal Oscillator Frequency Monitoring Enable
bits : 26 - 26 (1 bit)


CKGR_MCFR

Main Clock Frequency Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKGR_MCFR CKGR_MCFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAINF MAINFRDY RCMEAS CCSS

MAINF : Main Clock Frequency
bits : 0 - 15 (16 bit)

MAINFRDY : Main Clock Frequency Measure Ready
bits : 16 - 16 (1 bit)

RCMEAS : RC Oscillator Frequency Measure (write-only)
bits : 20 - 20 (1 bit)

CCSS : Counter Clock Source Selection
bits : 24 - 24 (1 bit)


PCK[6]

Programmable Clock Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[6] PCK[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Programmable Clock Source Selection
bits : 0 - 2 (3 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

SLCK is selected

1 : MAIN_CLK

MAINCK is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLLCKDIV is selected

4 : MCK

MCK is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 11 (8 bit)


CKGR_PLLAR

PLLA Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKGR_PLLAR CKGR_PLLAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVA PLLACOUNT MULA ONE

DIVA : PLLA Front End Divider
bits : 0 - 7 (8 bit)

Enumeration: DIVASelect

0 : _0

Divider output is 0 and PLLA is disabled.

1 : BYPASS

Divider is bypassed (divide by 1) and PLLA is enabled.

End of enumeration elements list.

PLLACOUNT : PLLA Counter
bits : 8 - 13 (6 bit)

MULA : PLLA Multiplier
bits : 16 - 26 (11 bit)

ONE : Must Be Set to 1
bits : 29 - 29 (1 bit)


PCK[7]

Programmable Clock Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[7] PCK[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Programmable Clock Source Selection
bits : 0 - 2 (3 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

SLCK is selected

1 : MAIN_CLK

MAINCK is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLLCKDIV is selected

4 : MCK

MCK is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 11 (8 bit)


MCKR

Master Clock Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCKR MCKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES MDIV UPLLDIV2

CSS : Master Clock Source Selection
bits : 0 - 1 (2 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

Slow Clock is selected

1 : MAIN_CLK

Main Clock is selected

2 : PLLA_CLK

PLLA Clock is selected

3 : UPLL_CLK

Divided UPLL Clock is selected

End of enumeration elements list.

PRES : Processor Clock Prescaler
bits : 4 - 6 (3 bit)

Enumeration: PRESSelect

0 : CLK_1

Selected clock

1 : CLK_2

Selected clock divided by 2

2 : CLK_4

Selected clock divided by 4

3 : CLK_8

Selected clock divided by 8

4 : CLK_16

Selected clock divided by 16

5 : CLK_32

Selected clock divided by 32

6 : CLK_64

Selected clock divided by 64

7 : CLK_3

Selected clock divided by 3

End of enumeration elements list.

MDIV : Master Clock Division
bits : 8 - 9 (2 bit)

Enumeration: MDIVSelect

0 : EQ_PCK

Master Clock is Prescaler Output Clock divided by 1.

1 : PCK_DIV2

Master Clock is Prescaler Output Clock divided by 2.

2 : PCK_DIV4

Master Clock is Prescaler Output Clock divided by 4.

3 : PCK_DIV3

Master Clock is Prescaler Output Clock divided by 3.

End of enumeration elements list.

UPLLDIV2 : UPLL Divider by 2
bits : 13 - 13 (1 bit)


USB

USB Clock Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB USB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBS USBDIV

USBS : USB Input Clock Selection
bits : 0 - 0 (1 bit)

USBDIV : Divider for USB_48M
bits : 8 - 11 (4 bit)


SCDR

System Clock Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCDR SCDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBCLK PCK0 PCK1 PCK2 PCK3 PCK4 PCK5 PCK6

USBCLK : Disable USB FS Clock
bits : 5 - 5 (1 bit)

PCK0 : Programmable Clock 0 Output Disable
bits : 8 - 8 (1 bit)

PCK1 : Programmable Clock 1 Output Disable
bits : 9 - 9 (1 bit)

PCK2 : Programmable Clock 2 Output Disable
bits : 10 - 10 (1 bit)

PCK3 : Programmable Clock 3 Output Disable
bits : 11 - 11 (1 bit)

PCK4 : Programmable Clock 4 Output Disable
bits : 12 - 12 (1 bit)

PCK5 : Programmable Clock 5 Output Disable
bits : 13 - 13 (1 bit)

PCK6 : Programmable Clock 6 Output Disable
bits : 14 - 14 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTS LOCKA MCKRDY LOCKU PCKRDY0 PCKRDY1 PCKRDY2 PCKRDY3 PCKRDY4 PCKRDY5 PCKRDY6 MOSCSELS MOSCRCS CFDEV XT32KERR

MOSCXTS : Main Crystal Oscillator Status Interrupt Enable
bits : 0 - 0 (1 bit)

LOCKA : PLLA Lock Interrupt Enable
bits : 1 - 1 (1 bit)

MCKRDY : Master Clock Ready Interrupt Enable
bits : 3 - 3 (1 bit)

LOCKU : UTMI PLL Lock Interrupt Enable
bits : 6 - 6 (1 bit)

PCKRDY0 : Programmable Clock Ready 0 Interrupt Enable
bits : 8 - 8 (1 bit)

PCKRDY1 : Programmable Clock Ready 1 Interrupt Enable
bits : 9 - 9 (1 bit)

PCKRDY2 : Programmable Clock Ready 2 Interrupt Enable
bits : 10 - 10 (1 bit)

PCKRDY3 : Programmable Clock Ready 3 Interrupt Enable
bits : 11 - 11 (1 bit)

PCKRDY4 : Programmable Clock Ready 4 Interrupt Enable
bits : 12 - 12 (1 bit)

PCKRDY5 : Programmable Clock Ready 5 Interrupt Enable
bits : 13 - 13 (1 bit)

PCKRDY6 : Programmable Clock Ready 6 Interrupt Enable
bits : 14 - 14 (1 bit)

MOSCSELS : Main Clock Source Oscillator Selection Status Interrupt Enable
bits : 16 - 16 (1 bit)

MOSCRCS : Main RC Oscillator Status Interrupt Enable
bits : 17 - 17 (1 bit)

CFDEV : Clock Failure Detector Event Interrupt Enable
bits : 18 - 18 (1 bit)

XT32KERR : 32.768 kHz Crystal Oscillator Error Interrupt Enable
bits : 21 - 21 (1 bit)


IDR

Interrupt Disable Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTS LOCKA MCKRDY LOCKU PCKRDY0 PCKRDY1 PCKRDY2 PCKRDY3 PCKRDY4 PCKRDY5 PCKRDY6 MOSCSELS MOSCRCS CFDEV XT32KERR

MOSCXTS : Main Crystal Oscillator Status Interrupt Disable
bits : 0 - 0 (1 bit)

LOCKA : PLLA Lock Interrupt Disable
bits : 1 - 1 (1 bit)

MCKRDY : Master Clock Ready Interrupt Disable
bits : 3 - 3 (1 bit)

LOCKU : UTMI PLL Lock Interrupt Disable
bits : 6 - 6 (1 bit)

PCKRDY0 : Programmable Clock Ready 0 Interrupt Disable
bits : 8 - 8 (1 bit)

PCKRDY1 : Programmable Clock Ready 1 Interrupt Disable
bits : 9 - 9 (1 bit)

PCKRDY2 : Programmable Clock Ready 2 Interrupt Disable
bits : 10 - 10 (1 bit)

PCKRDY3 : Programmable Clock Ready 3 Interrupt Disable
bits : 11 - 11 (1 bit)

PCKRDY4 : Programmable Clock Ready 4 Interrupt Disable
bits : 12 - 12 (1 bit)

PCKRDY5 : Programmable Clock Ready 5 Interrupt Disable
bits : 13 - 13 (1 bit)

PCKRDY6 : Programmable Clock Ready 6 Interrupt Disable
bits : 14 - 14 (1 bit)

MOSCSELS : Main Clock Source Oscillator Selection Status Interrupt Disable
bits : 16 - 16 (1 bit)

MOSCRCS : Main RC Status Interrupt Disable
bits : 17 - 17 (1 bit)

CFDEV : Clock Failure Detector Event Interrupt Disable
bits : 18 - 18 (1 bit)

XT32KERR : 32.768 kHz Crystal Oscillator Error Interrupt Disable
bits : 21 - 21 (1 bit)


SR

Status Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTS LOCKA MCKRDY LOCKU OSCSELS PCKRDY0 PCKRDY1 PCKRDY2 PCKRDY3 PCKRDY4 PCKRDY5 PCKRDY6 MOSCSELS MOSCRCS CFDEV CFDS FOS XT32KERR

MOSCXTS : Main Crystal Oscillator Status
bits : 0 - 0 (1 bit)

LOCKA : PLLA Lock Status
bits : 1 - 1 (1 bit)

MCKRDY : Master Clock Status
bits : 3 - 3 (1 bit)

LOCKU : UTMI PLL Lock Status
bits : 6 - 6 (1 bit)

OSCSELS : Slow Clock Source Oscillator Selection
bits : 7 - 7 (1 bit)

PCKRDY0 : Programmable Clock Ready 0 Status
bits : 8 - 8 (1 bit)

PCKRDY1 : Programmable Clock Ready 1 Status
bits : 9 - 9 (1 bit)

PCKRDY2 : Programmable Clock Ready 2 Status
bits : 10 - 10 (1 bit)

PCKRDY3 : Programmable Clock Ready 3 Status
bits : 11 - 11 (1 bit)

PCKRDY4 : Programmable Clock Ready 4 Status
bits : 12 - 12 (1 bit)

PCKRDY5 : Programmable Clock Ready 5 Status
bits : 13 - 13 (1 bit)

PCKRDY6 : Programmable Clock Ready 6 Status
bits : 14 - 14 (1 bit)

MOSCSELS : Main Clock Source Oscillator Selection Status
bits : 16 - 16 (1 bit)

MOSCRCS : Main RC Oscillator Status
bits : 17 - 17 (1 bit)

CFDEV : Clock Failure Detector Event
bits : 18 - 18 (1 bit)

CFDS : Clock Failure Detector Status
bits : 19 - 19 (1 bit)

FOS : Clock Failure Detector Fault Output Status
bits : 20 - 20 (1 bit)

XT32KERR : Slow Crystal Oscillator Error
bits : 21 - 21 (1 bit)


IMR

Interrupt Mask Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOSCXTS LOCKA MCKRDY LOCKU PCKRDY0 PCKRDY1 PCKRDY2 PCKRDY3 PCKRDY4 PCKRDY5 PCKRDY6 MOSCSELS MOSCRCS CFDEV XT32KERR

MOSCXTS : Main Crystal Oscillator Status Interrupt Mask
bits : 0 - 0 (1 bit)

LOCKA : PLLA Lock Interrupt Mask
bits : 1 - 1 (1 bit)

MCKRDY : Master Clock Ready Interrupt Mask
bits : 3 - 3 (1 bit)

LOCKU : UTMI PLL Lock Interrupt Mask
bits : 6 - 6 (1 bit)

PCKRDY0 : Programmable Clock Ready 0 Interrupt Mask
bits : 8 - 8 (1 bit)

PCKRDY1 : Programmable Clock Ready 1 Interrupt Mask
bits : 9 - 9 (1 bit)

PCKRDY2 : Programmable Clock Ready 2 Interrupt Mask
bits : 10 - 10 (1 bit)

PCKRDY3 : Programmable Clock Ready 3 Interrupt Mask
bits : 11 - 11 (1 bit)

PCKRDY4 : Programmable Clock Ready 4 Interrupt Mask
bits : 12 - 12 (1 bit)

PCKRDY5 : Programmable Clock Ready 5 Interrupt Mask
bits : 13 - 13 (1 bit)

PCKRDY6 : Programmable Clock Ready 6 Interrupt Mask
bits : 14 - 14 (1 bit)

MOSCSELS : Main Clock Source Oscillator Selection Status Interrupt Mask
bits : 16 - 16 (1 bit)

MOSCRCS : Main RC Status Interrupt Mask
bits : 17 - 17 (1 bit)

CFDEV : Clock Failure Detector Event Interrupt Mask
bits : 18 - 18 (1 bit)

XT32KERR : 32.768 kHz Crystal Oscillator Error Interrupt Mask
bits : 21 - 21 (1 bit)


FSMR

Fast Startup Mode Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSMR FSMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSTT0 FSTT1 FSTT2 FSTT3 FSTT4 FSTT5 FSTT6 FSTT7 FSTT8 FSTT9 FSTT10 FSTT11 FSTT12 FSTT13 FSTT14 FSTT15 RTTAL RTCAL USBAL LPM FLPM FFLPM

FSTT0 : Fast Startup Input Enable 0
bits : 0 - 0 (1 bit)

FSTT1 : Fast Startup Input Enable 1
bits : 1 - 1 (1 bit)

FSTT2 : Fast Startup Input Enable 2
bits : 2 - 2 (1 bit)

FSTT3 : Fast Startup Input Enable 3
bits : 3 - 3 (1 bit)

FSTT4 : Fast Startup Input Enable 4
bits : 4 - 4 (1 bit)

FSTT5 : Fast Startup Input Enable 5
bits : 5 - 5 (1 bit)

FSTT6 : Fast Startup Input Enable 6
bits : 6 - 6 (1 bit)

FSTT7 : Fast Startup Input Enable 7
bits : 7 - 7 (1 bit)

FSTT8 : Fast Startup Input Enable 8
bits : 8 - 8 (1 bit)

FSTT9 : Fast Startup Input Enable 9
bits : 9 - 9 (1 bit)

FSTT10 : Fast Startup Input Enable 10
bits : 10 - 10 (1 bit)

FSTT11 : Fast Startup Input Enable 11
bits : 11 - 11 (1 bit)

FSTT12 : Fast Startup Input Enable 12
bits : 12 - 12 (1 bit)

FSTT13 : Fast Startup Input Enable 13
bits : 13 - 13 (1 bit)

FSTT14 : Fast Startup Input Enable 14
bits : 14 - 14 (1 bit)

FSTT15 : Fast Startup Input Enable 15
bits : 15 - 15 (1 bit)

RTTAL : RTT Alarm Enable
bits : 16 - 16 (1 bit)

RTCAL : RTC Alarm Enable
bits : 17 - 17 (1 bit)

USBAL : USB Alarm Enable
bits : 18 - 18 (1 bit)

LPM : Low-power Mode
bits : 20 - 20 (1 bit)

FLPM : Flash Low-power Mode
bits : 21 - 22 (2 bit)

Enumeration: FLPMSelect

0 : FLASH_STANDBY

Flash is in Standby Mode when system enters Wait Mode

1 : FLASH_DEEP_POWERDOWN

Flash is in Deep-power-down mode when system enters Wait Mode

2 : FLASH_IDLE

Idle mode

End of enumeration elements list.

FFLPM : Force Flash Low-power Mode
bits : 23 - 23 (1 bit)


FSPR

Fast Startup Polarity Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSPR FSPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSTP0 FSTP1 FSTP2 FSTP3 FSTP4 FSTP5 FSTP6 FSTP7 FSTP8 FSTP9 FSTP10 FSTP11 FSTP12 FSTP13 FSTP14 FSTP15

FSTP0 : Fast Startup Input Polarity 0
bits : 0 - 0 (1 bit)

FSTP1 : Fast Startup Input Polarity 1
bits : 1 - 1 (1 bit)

FSTP2 : Fast Startup Input Polarity 2
bits : 2 - 2 (1 bit)

FSTP3 : Fast Startup Input Polarity 3
bits : 3 - 3 (1 bit)

FSTP4 : Fast Startup Input Polarity 4
bits : 4 - 4 (1 bit)

FSTP5 : Fast Startup Input Polarity 5
bits : 5 - 5 (1 bit)

FSTP6 : Fast Startup Input Polarity 6
bits : 6 - 6 (1 bit)

FSTP7 : Fast Startup Input Polarity 7
bits : 7 - 7 (1 bit)

FSTP8 : Fast Startup Input Polarity 8
bits : 8 - 8 (1 bit)

FSTP9 : Fast Startup Input Polarity 9
bits : 9 - 9 (1 bit)

FSTP10 : Fast Startup Input Polarity 10
bits : 10 - 10 (1 bit)

FSTP11 : Fast Startup Input Polarity 11
bits : 11 - 11 (1 bit)

FSTP12 : Fast Startup Input Polarity 12
bits : 12 - 12 (1 bit)

FSTP13 : Fast Startup Input Polarity 13
bits : 13 - 13 (1 bit)

FSTP14 : Fast Startup Input Polarity 14
bits : 14 - 14 (1 bit)

FSTP15 : Fast Startup Input Polarity 15
bits : 15 - 15 (1 bit)


FOCR

Fault Output Clear Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FOCR FOCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FOCLR

FOCLR : Fault Output Clear
bits : 0 - 0 (1 bit)


SCSR

System Clock Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKS USBCLK PCK0 PCK1 PCK2 PCK3 PCK4 PCK5 PCK6

HCLKS : HCLK Status
bits : 0 - 0 (1 bit)

USBCLK : USB FS Clock Status
bits : 5 - 5 (1 bit)

PCK0 : Programmable Clock 0 Output Status
bits : 8 - 8 (1 bit)

PCK1 : Programmable Clock 1 Output Status
bits : 9 - 9 (1 bit)

PCK2 : Programmable Clock 2 Output Status
bits : 10 - 10 (1 bit)

PCK3 : Programmable Clock 3 Output Status
bits : 11 - 11 (1 bit)

PCK4 : Programmable Clock 4 Output Status
bits : 12 - 12 (1 bit)

PCK5 : Programmable Clock 5 Output Status
bits : 13 - 13 (1 bit)

PCK6 : Programmable Clock 6 Output Status
bits : 14 - 14 (1 bit)


PCK[0]

Programmable Clock Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[0] PCK[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Programmable Clock Source Selection
bits : 0 - 2 (3 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

SLCK is selected

1 : MAIN_CLK

MAINCK is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLLCKDIV is selected

4 : MCK

MCK is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 11 (8 bit)


PCK[1]

Programmable Clock Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCK[1] PCK[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSS PRES

CSS : Programmable Clock Source Selection
bits : 0 - 2 (3 bit)

Enumeration: CSSSelect

0 : SLOW_CLK

SLCK is selected

1 : MAIN_CLK

MAINCK is selected

2 : PLLA_CLK

PLLACK is selected

3 : UPLL_CLK

UPLLCKDIV is selected

4 : MCK

MCK is selected

End of enumeration elements list.

PRES : Programmable Clock Prescaler
bits : 4 - 11 (8 bit)


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)

Enumeration: WPKEYSelect

5262659 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)



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