Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected
SDRAMC Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : SDRAMC Command Mode
bits : 0 - 2 (3 bit)
Enumeration: MODESelect
0 : NORMAL
Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM.
1 : NOP
The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
2 : ALLBANKS_PRECHARGE
The SDRAMC issues an 'All Banks Precharge' command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
3 : LOAD_MODEREG
The SDRAMC issues a 'Load Mode Register' command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM.
4 : AUTO_REFRESH
The SDRAMC issues an 'Auto-Refresh' Command when the SDRAM device is accessed regardless of the cycle. Previously, an 'All Banks Precharge' command must be issued. To activate this mode, command must be followed by a write to the SDRAM.
5 : EXT_LOAD_MODEREG
The SDRAMC issues an 'Extended Load Mode Register' command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the 'Extended Load Mode Register' command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1.
6 : DEEP_POWERDOWN
Deep power-down mode. Enters deep power-down mode.
End of enumeration elements list.
SDRAMC Low Power Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPCB : Low-power Configuration Bits
bits : 0 - 1 (2 bit)
Enumeration: LPCBSelect
0 : DISABLED
Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device.
1 : SELF_REFRESH
The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access.
2 : POWER_DOWN
The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access.
3 : DEEP_POWER_DOWN
The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM.
End of enumeration elements list.
PASR : Partial Array Self-refresh (only for low-power SDRAM)
bits : 4 - 6 (3 bit)
TCSR : Temperature Compensated Self-Refresh (only for low-power SDRAM)
bits : 8 - 9 (2 bit)
DS : Drive Strength (only for low-power SDRAM)
bits : 10 - 11 (2 bit)
TIMEOUT : Time to Define When Low-power Mode Is Enabled
bits : 12 - 13 (2 bit)
Enumeration: TIMEOUTSelect
0 : LP_LAST_XFER
The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer.
1 : LP_LAST_XFER_64
The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer.
2 : LP_LAST_XFER_128
The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer.
End of enumeration elements list.
SDRAMC Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RES : Refresh Error Status
bits : 0 - 0 (1 bit)
SDRAMC Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RES : Refresh Error Status
bits : 0 - 0 (1 bit)
SDRAMC Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RES : Refresh Error Status
bits : 0 - 0 (1 bit)
SDRAMC Interrupt Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RES : Refresh Error Status (cleared on read)
bits : 0 - 0 (1 bit)
SDRAMC Memory Device Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD : Memory Device Type
bits : 0 - 1 (2 bit)
Enumeration: MDSelect
0 : SDRAM
SDRAM
1 : LPSDRAM
Low-power SDRAM
End of enumeration elements list.
SDRAMC Configuration Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMRD : Load Mode Register Command to Active or Refresh Command
bits : 0 - 3 (4 bit)
UNAL : Support Unaligned Access
bits : 8 - 8 (1 bit)
Enumeration: UNALSelect
0 : UNSUPPORTED
Unaligned access is not supported.
1 : SUPPORTED
Unaligned access is supported.
End of enumeration elements list.
SDRAMC OCMS Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDR_SE : SDRAM Memory Controller Scrambling Enable
bits : 0 - 0 (1 bit)
SDRAMC OCMS KEY1 Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY1 : Off-chip Memory Scrambling (OCMS) Key Part 1
bits : 0 - 31 (32 bit)
SDRAMC OCMS KEY2 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY2 : Off-chip Memory Scrambling (OCMS) Key Part 2
bits : 0 - 31 (32 bit)
SDRAMC Refresh Timer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : SDRAMC Refresh Timer Count
bits : 0 - 11 (12 bit)
SDRAMC Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NC : Number of Column Bits
bits : 0 - 1 (2 bit)
Enumeration: NCSelect
0 : COL8
8 column bits
1 : COL9
9 column bits
2 : COL10
10 column bits
3 : COL11
11 column bits
End of enumeration elements list.
NR : Number of Row Bits
bits : 2 - 3 (2 bit)
Enumeration: NRSelect
0 : ROW11
11 row bits
1 : ROW12
12 row bits
2 : ROW13
13 row bits
End of enumeration elements list.
NB : Number of Banks
bits : 4 - 4 (1 bit)
Enumeration: NBSelect
0 : BANK2
2 banks
1 : BANK4
4 banks
End of enumeration elements list.
CAS : CAS Latency
bits : 5 - 6 (2 bit)
Enumeration: CASSelect
1 : LATENCY1
1 cycle CAS latency
2 : LATENCY2
2 cycle CAS latency
3 : LATENCY3
3 cycle CAS latency
End of enumeration elements list.
DBW : Data Bus Width
bits : 7 - 7 (1 bit)
TWR : Write Recovery Delay
bits : 8 - 11 (4 bit)
TRC_TRFC : Row Cycle Delay and Row Refresh Cycle
bits : 12 - 15 (4 bit)
TRP : Row Precharge Delay
bits : 16 - 19 (4 bit)
TRCD : Row to Column Delay
bits : 20 - 23 (4 bit)
TRAS : Active to Precharge Delay
bits : 24 - 27 (4 bit)
TXSR : Exit Self Refresh to Active Delay
bits : 28 - 31 (4 bit)
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