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EVSYS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1F4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRLA

CHANNEL

INTPEND

USER[12]

USER[13]

USER0

USER1

USER2

USER3

USER4

USER5

USER6

USER[14]

USER7

USER8

USER9

USER10

USER11

USER12

USER13

USER14

USER15

USER16

USER17

USER18

USER19

USER20

USER21

USER22

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

USER[15]

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

INTSTATUS

USER[16]

USER[17]

USER[18]

BUSYCH

USER[19]

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[20]

USER[21]

USER[22]

READYUSR

INTENCLR

INTENSET

INTFLAG

NONSECCHAN

NSCHKCHAN

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

NONSECUSER1

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

NSCHKUSER1

CHANNEL[0]-CHANNEL

CHANNEL[0]-CHINTENCLR

USER[0]

CHANNEL[0]-CHINTENSET

CHANNEL[0]-CHINTFLAG

CHANNEL[0]-CHSTATUS

USER[1]

NONSECUSER[0]

NSCHKUSER[0]

SWEVT

CHINTENCLR

CHANNEL[1]-CHANNEL[0]-CHANNEL

USER[2]

CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[1]-CHANNEL[0]-CHSTATUS

CHINTENSET

USER[3]

CHINTFLAG

USER[4]

CHSTATUS

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

USER[5]

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

PRICTRL

USER[6]

USER[7]

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

USER[8]

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

USER[9]

USER[10]

USER[11]

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS


CTRLA

Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST

SWRST : Software Reset
bits : 0 - 0 (1 bit)


CHANNEL

Channel n Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


INTPEND

Channel Pending Interrupt
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTPEND INTPEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID OVR EVD READY BUSY

ID : Channel ID
bits : 0 - 1 (2 bit)

OVR : Channel Overrun
bits : 8 - 8 (1 bit)

EVD : Channel Event Detected
bits : 9 - 9 (1 bit)

READY : Ready
bits : 14 - 14 (1 bit)

BUSY : Busy
bits : 15 - 15 (1 bit)


USER[12]

User Multiplexer n
address_offset : 0x100E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[12] USER[12] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[13]

User Multiplexer n
address_offset : 0x113B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[13] USER[13] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER0

User Multiplexer n
address_offset : 0x120 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER0 USER0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER1

User Multiplexer n
address_offset : 0x121 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER1 USER1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER2

User Multiplexer n
address_offset : 0x122 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER2 USER2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER3

User Multiplexer n
address_offset : 0x123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER3 USER3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER4

User Multiplexer n
address_offset : 0x124 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER4 USER4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER5

User Multiplexer n
address_offset : 0x125 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER5 USER5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER6

User Multiplexer n
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER6 USER6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[14]

User Multiplexer n
address_offset : 0x1269 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[14] USER[14] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER7

User Multiplexer n
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER7 USER7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER8

User Multiplexer n
address_offset : 0x128 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER8 USER8 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER9

User Multiplexer n
address_offset : 0x129 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER9 USER9 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER10

User Multiplexer n
address_offset : 0x12A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER10 USER10 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER11

User Multiplexer n
address_offset : 0x12B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER11 USER11 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER12

User Multiplexer n
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER12 USER12 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER13

User Multiplexer n
address_offset : 0x12D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER13 USER13 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER14

User Multiplexer n
address_offset : 0x12E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER14 USER14 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER15

User Multiplexer n
address_offset : 0x12F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER15 USER15 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER16

User Multiplexer n
address_offset : 0x130 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER16 USER16 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER17

User Multiplexer n
address_offset : 0x131 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER17 USER17 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER18

User Multiplexer n
address_offset : 0x132 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER18 USER18 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER19

User Multiplexer n
address_offset : 0x133 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER19 USER19 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER20

User Multiplexer n
address_offset : 0x134 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER20 USER20 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER21

User Multiplexer n
address_offset : 0x135 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER21 USER21 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER22

User Multiplexer n
address_offset : 0x136 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER22 USER22 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[15]

User Multiplexer n
address_offset : 0x1398 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[15] USER[15] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x13D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x13E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x13F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


INTSTATUS

Interrupt Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTSTATUS INTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHINT0 CHINT1 CHINT2 CHINT3

CHINT0 : Channel 0 Pending Interrupt
bits : 0 - 0 (1 bit)

CHINT1 : Channel 1 Pending Interrupt
bits : 1 - 1 (1 bit)

CHINT2 : Channel 2 Pending Interrupt
bits : 2 - 2 (1 bit)

CHINT3 : Channel 3 Pending Interrupt
bits : 3 - 3 (1 bit)


USER[16]

User Multiplexer n
address_offset : 0x14C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[16] USER[16] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[17]

User Multiplexer n
address_offset : 0x15F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[17] USER[17] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[18]

User Multiplexer n
address_offset : 0x172B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[18] USER[18] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


BUSYCH

Busy Channels
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUSYCH BUSYCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSYCH0 BUSYCH1 BUSYCH2 BUSYCH3

BUSYCH0 : Busy Channel 0
bits : 0 - 0 (1 bit)

BUSYCH1 : Busy Channel 1
bits : 1 - 1 (1 bit)

BUSYCH2 : Busy Channel 2
bits : 2 - 2 (1 bit)

BUSYCH3 : Busy Channel 3
bits : 3 - 3 (1 bit)


USER[19]

User Multiplexer n
address_offset : 0x185E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[19] USER[19] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x18D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x18E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x18F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[20]

User Multiplexer n
address_offset : 0x1992 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[20] USER[20] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[21]

User Multiplexer n
address_offset : 0x1AC7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[21] USER[21] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[22]

User Multiplexer n
address_offset : 0x1BFD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[22] USER[22] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


READYUSR

Ready Users
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

READYUSR READYUSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READYUSR0 READYUSR1 READYUSR2 READYUSR3

READYUSR0 : Ready User for Channel 0
bits : 0 - 0 (1 bit)

READYUSR1 : Ready User for Channel 1
bits : 1 - 1 (1 bit)

READYUSR2 : Ready User for Channel 2
bits : 2 - 2 (1 bit)

READYUSR3 : Ready User for Channel 3
bits : 3 - 3 (1 bit)


INTENCLR

Interrupt Enable Clear
address_offset : 0x1D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NSCHK

NSCHK : Non-Secure Check Interrupt Enable
bits : 0 - 0 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x1D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NSCHK

NSCHK : Non-Secure Check Interrupt Enable
bits : 0 - 0 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x1D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 NSCHK

NSCHK : Non-Secure Check
bits : 0 - 0 (1 bit)


NONSECCHAN

Channels Security Attribution
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NONSECCHAN NONSECCHAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 CHANNEL4 CHANNEL5 CHANNEL6 CHANNEL7

CHANNEL0 : Non-Secure for Channel 0
bits : 0 - 0 (1 bit)

CHANNEL1 : Non-Secure for Channel 1
bits : 1 - 1 (1 bit)

CHANNEL2 : Non-Secure for Channel 2
bits : 2 - 2 (1 bit)

CHANNEL3 : Non-Secure for Channel 3
bits : 3 - 3 (1 bit)

CHANNEL4 : Non-Secure for Channel 4
bits : 4 - 4 (1 bit)

CHANNEL5 : Non-Secure for Channel 5
bits : 5 - 5 (1 bit)

CHANNEL6 : Non-Secure for Channel 6
bits : 6 - 6 (1 bit)

CHANNEL7 : Non-Secure for Channel 7
bits : 7 - 7 (1 bit)


NSCHKCHAN

Non-Secure Channels Check
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSCHKCHAN NSCHKCHAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 CHANNEL4 CHANNEL5 CHANNEL6 CHANNEL7

CHANNEL0 : Channel 0 to be checked as non-secured
bits : 0 - 0 (1 bit)

CHANNEL1 : Channel 1 to be checked as non-secured
bits : 1 - 1 (1 bit)

CHANNEL2 : Channel 2 to be checked as non-secured
bits : 2 - 2 (1 bit)

CHANNEL3 : Channel 3 to be checked as non-secured
bits : 3 - 3 (1 bit)

CHANNEL4 : Channel 4 to be checked as non-secured
bits : 4 - 4 (1 bit)

CHANNEL5 : Channel 5 to be checked as non-secured
bits : 5 - 5 (1 bit)

CHANNEL6 : Channel 6 to be checked as non-secured
bits : 6 - 6 (1 bit)

CHANNEL7 : Channel 7 to be checked as non-secured
bits : 7 - 7 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


NONSECUSER1

Users Security Attribution
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NONSECUSER1 NONSECUSER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER0 USER1 USER2 USER3 USER4 USER5 USER6 USER7 USER8 USER9 USER10 USER11 USER12 USER13 USER14 USER15 USER16 USER17 USER18 USER19 USER20 USER21 USER22

USER0 : Non-Secure for User 0
bits : 0 - 0 (1 bit)

USER1 : Non-Secure for User 1
bits : 1 - 1 (1 bit)

USER2 : Non-Secure for User 2
bits : 2 - 2 (1 bit)

USER3 : Non-Secure for User 3
bits : 3 - 3 (1 bit)

USER4 : Non-Secure for User 4
bits : 4 - 4 (1 bit)

USER5 : Non-Secure for User 5
bits : 5 - 5 (1 bit)

USER6 : Non-Secure for User 6
bits : 6 - 6 (1 bit)

USER7 : Non-Secure for User 7
bits : 7 - 7 (1 bit)

USER8 : Non-Secure for User 8
bits : 8 - 8 (1 bit)

USER9 : Non-Secure for User 9
bits : 9 - 9 (1 bit)

USER10 : Non-Secure for User 10
bits : 10 - 10 (1 bit)

USER11 : Non-Secure for User 11
bits : 11 - 11 (1 bit)

USER12 : Non-Secure for User 12
bits : 12 - 12 (1 bit)

USER13 : Non-Secure for User 13
bits : 13 - 13 (1 bit)

USER14 : Non-Secure for User 14
bits : 14 - 14 (1 bit)

USER15 : Non-Secure for User 15
bits : 15 - 15 (1 bit)

USER16 : Non-Secure for User 16
bits : 16 - 16 (1 bit)

USER17 : Non-Secure for User 17
bits : 17 - 17 (1 bit)

USER18 : Non-Secure for User 18
bits : 18 - 18 (1 bit)

USER19 : Non-Secure for User 19
bits : 19 - 19 (1 bit)

USER20 : Non-Secure for User 20
bits : 20 - 20 (1 bit)

USER21 : Non-Secure for User 21
bits : 21 - 21 (1 bit)

USER22 : Non-Secure for User 22
bits : 22 - 22 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x1E7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


NSCHKUSER1

Non-Secure Users Check
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSCHKUSER1 NSCHKUSER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER0 USER1 USER2 USER3 USER4 USER5 USER6 USER7 USER8 USER9 USER10 USER11 USER12 USER13 USER14 USER15 USER16 USER17 USER18 USER19 USER20 USER21 USER22

USER0 : User 0 to be checked as non-secured
bits : 0 - 0 (1 bit)

USER1 : User 1 to be checked as non-secured
bits : 1 - 1 (1 bit)

USER2 : User 2 to be checked as non-secured
bits : 2 - 2 (1 bit)

USER3 : User 3 to be checked as non-secured
bits : 3 - 3 (1 bit)

USER4 : User 4 to be checked as non-secured
bits : 4 - 4 (1 bit)

USER5 : User 5 to be checked as non-secured
bits : 5 - 5 (1 bit)

USER6 : User 6 to be checked as non-secured
bits : 6 - 6 (1 bit)

USER7 : User 7 to be checked as non-secured
bits : 7 - 7 (1 bit)

USER8 : User 8 to be checked as non-secured
bits : 8 - 8 (1 bit)

USER9 : User 9 to be checked as non-secured
bits : 9 - 9 (1 bit)

USER10 : User 10 to be checked as non-secured
bits : 10 - 10 (1 bit)

USER11 : User 11 to be checked as non-secured
bits : 11 - 11 (1 bit)

USER12 : User 12 to be checked as non-secured
bits : 12 - 12 (1 bit)

USER13 : User 13 to be checked as non-secured
bits : 13 - 13 (1 bit)

USER14 : User 14 to be checked as non-secured
bits : 14 - 14 (1 bit)

USER15 : User 15 to be checked as non-secured
bits : 15 - 15 (1 bit)

USER16 : User 16 to be checked as non-secured
bits : 16 - 16 (1 bit)

USER17 : User 17 to be checked as non-secured
bits : 17 - 17 (1 bit)

USER18 : User 18 to be checked as non-secured
bits : 18 - 18 (1 bit)

USER19 : User 19 to be checked as non-secured
bits : 19 - 19 (1 bit)

USER20 : User 20 to be checked as non-secured
bits : 20 - 20 (1 bit)

USER21 : User 21 to be checked as non-secured
bits : 21 - 21 (1 bit)

USER22 : User 22 to be checked as non-secured
bits : 22 - 22 (1 bit)


CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHANNEL CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTENCLR CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


USER[0]

User Multiplexer n
address_offset : 0x240 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[0] USER[0] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTENSET CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHINTFLAG CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[0]-CHSTATUS CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[1]

User Multiplexer n
address_offset : 0x361 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[1] USER[1] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


NONSECUSER[0]

Users Security Attribution
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NONSECUSER[0] NONSECUSER[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER0 USER1 USER2 USER3 USER4 USER5 USER6 USER7 USER8 USER9 USER10 USER11 USER12 USER13 USER14 USER15 USER16 USER17 USER18 USER19 USER20 USER21 USER22

USER0 : Non-Secure for User 0
bits : 0 - 0 (1 bit)

USER1 : Non-Secure for User 1
bits : 1 - 1 (1 bit)

USER2 : Non-Secure for User 2
bits : 2 - 2 (1 bit)

USER3 : Non-Secure for User 3
bits : 3 - 3 (1 bit)

USER4 : Non-Secure for User 4
bits : 4 - 4 (1 bit)

USER5 : Non-Secure for User 5
bits : 5 - 5 (1 bit)

USER6 : Non-Secure for User 6
bits : 6 - 6 (1 bit)

USER7 : Non-Secure for User 7
bits : 7 - 7 (1 bit)

USER8 : Non-Secure for User 8
bits : 8 - 8 (1 bit)

USER9 : Non-Secure for User 9
bits : 9 - 9 (1 bit)

USER10 : Non-Secure for User 10
bits : 10 - 10 (1 bit)

USER11 : Non-Secure for User 11
bits : 11 - 11 (1 bit)

USER12 : Non-Secure for User 12
bits : 12 - 12 (1 bit)

USER13 : Non-Secure for User 13
bits : 13 - 13 (1 bit)

USER14 : Non-Secure for User 14
bits : 14 - 14 (1 bit)

USER15 : Non-Secure for User 15
bits : 15 - 15 (1 bit)

USER16 : Non-Secure for User 16
bits : 16 - 16 (1 bit)

USER17 : Non-Secure for User 17
bits : 17 - 17 (1 bit)

USER18 : Non-Secure for User 18
bits : 18 - 18 (1 bit)

USER19 : Non-Secure for User 19
bits : 19 - 19 (1 bit)

USER20 : Non-Secure for User 20
bits : 20 - 20 (1 bit)

USER21 : Non-Secure for User 21
bits : 21 - 21 (1 bit)

USER22 : Non-Secure for User 22
bits : 22 - 22 (1 bit)


NSCHKUSER[0]

Non-Secure Users Check
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSCHKUSER[0] NSCHKUSER[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USER0 USER1 USER2 USER3 USER4 USER5 USER6 USER7 USER8 USER9 USER10 USER11 USER12 USER13 USER14 USER15 USER16 USER17 USER18 USER19 USER20 USER21 USER22

USER0 : User 0 to be checked as non-secured
bits : 0 - 0 (1 bit)

USER1 : User 1 to be checked as non-secured
bits : 1 - 1 (1 bit)

USER2 : User 2 to be checked as non-secured
bits : 2 - 2 (1 bit)

USER3 : User 3 to be checked as non-secured
bits : 3 - 3 (1 bit)

USER4 : User 4 to be checked as non-secured
bits : 4 - 4 (1 bit)

USER5 : User 5 to be checked as non-secured
bits : 5 - 5 (1 bit)

USER6 : User 6 to be checked as non-secured
bits : 6 - 6 (1 bit)

USER7 : User 7 to be checked as non-secured
bits : 7 - 7 (1 bit)

USER8 : User 8 to be checked as non-secured
bits : 8 - 8 (1 bit)

USER9 : User 9 to be checked as non-secured
bits : 9 - 9 (1 bit)

USER10 : User 10 to be checked as non-secured
bits : 10 - 10 (1 bit)

USER11 : User 11 to be checked as non-secured
bits : 11 - 11 (1 bit)

USER12 : User 12 to be checked as non-secured
bits : 12 - 12 (1 bit)

USER13 : User 13 to be checked as non-secured
bits : 13 - 13 (1 bit)

USER14 : User 14 to be checked as non-secured
bits : 14 - 14 (1 bit)

USER15 : User 15 to be checked as non-secured
bits : 15 - 15 (1 bit)

USER16 : User 16 to be checked as non-secured
bits : 16 - 16 (1 bit)

USER17 : User 17 to be checked as non-secured
bits : 17 - 17 (1 bit)

USER18 : User 18 to be checked as non-secured
bits : 18 - 18 (1 bit)

USER19 : User 19 to be checked as non-secured
bits : 19 - 19 (1 bit)

USER20 : User 20 to be checked as non-secured
bits : 20 - 20 (1 bit)

USER21 : User 21 to be checked as non-secured
bits : 21 - 21 (1 bit)

USER22 : User 22 to be checked as non-secured
bits : 22 - 22 (1 bit)


SWEVT

Software Event
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWEVT SWEVT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANNEL0 CHANNEL1 CHANNEL2 CHANNEL3 CHANNEL4 CHANNEL5 CHANNEL6 CHANNEL7

CHANNEL0 : Channel 0 Software Selection
bits : 0 - 0 (1 bit)

CHANNEL1 : Channel 1 Software Selection
bits : 1 - 1 (1 bit)

CHANNEL2 : Channel 2 Software Selection
bits : 2 - 2 (1 bit)

CHANNEL3 : Channel 3 Software Selection
bits : 3 - 3 (1 bit)

CHANNEL4 : Channel 4 Software Selection
bits : 4 - 4 (1 bit)

CHANNEL5 : Channel 5 Software Selection
bits : 5 - 5 (1 bit)

CHANNEL6 : Channel 6 Software Selection
bits : 6 - 6 (1 bit)

CHANNEL7 : Channel 7 Software Selection
bits : 7 - 7 (1 bit)


CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENCLR CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


USER[2]

User Multiplexer n
address_offset : 0x483 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[2] USER[2] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTENSET CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


USER[3]

User Multiplexer n
address_offset : 0x5A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[3] USER[3] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHINTFLAG CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[4]

User Multiplexer n
address_offset : 0x6CA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[4] USER[4] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHSTATUS

Channel n Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[5]

User Multiplexer n
address_offset : 0x7EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[5] USER[5] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0x7F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


PRICTRL

Priority Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRICTRL PRICTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 PRI RREN

PRI : Channel Priority Number
bits : 0 - 1 (2 bit)

RREN : Round-Robin Scheduling Enable
bits : 7 - 7 (1 bit)


USER[6]

User Multiplexer n
address_offset : 0x915 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[6] USER[6] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[7]

User Multiplexer n
address_offset : 0xA3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[7] USER[7] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xB5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


USER[8]

User Multiplexer n
address_offset : 0xB64 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[8] USER[8] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xB7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)


USER[9]

User Multiplexer n
address_offset : 0xC8D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[9] USER[9] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[10]

User Multiplexer n
address_offset : 0xDB7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[10] USER[10] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


USER[11]

User Multiplexer n
address_offset : 0xEE2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER[11] USER[11] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CHANNEL

CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL

Channel n Control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EVGEN PATH EDGSEL RUNSTDBY ONDEMAND

EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)

PATH : Path Selection
bits : 8 - 9 (2 bit)

Enumeration: PATHSelect

0 : SYNCHRONOUS

Synchronous path

1 : RESYNCHRONIZED

Resynchronized path

2 : ASYNCHRONOUS

Asynchronous path

End of enumeration elements list.

EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)

Enumeration: EDGSELSelect

0 : NO_EVT_OUTPUT

No event output when using the resynchronized or synchronous path

1 : RISING_EDGE

Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path

2 : FALLING_EDGE

Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path

3 : BOTH_EDGES

Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path

End of enumeration elements list.

RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)

ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR

Channel n Interrupt Enable Clear
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET

Channel n Interrupt Enable Set
address_offset : 0xF5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG

Channel n Interrupt Flag Status and Clear
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OVR EVD

OVR : Channel Overrun
bits : 0 - 0 (1 bit)

EVD : Channel Event Detected
bits : 1 - 1 (1 bit)


CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS

Channel n Status
address_offset : 0xF7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RDYUSR BUSYCH

RDYUSR : Ready User
bits : 0 - 0 (1 bit)

BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)



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