\n
address_offset : 0x0 Bytes (0x0)
size : 0x1F4 byte (0x0)
mem_usage : registers
protection : not protected
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG
CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS
Control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWRST : Software Reset
bits : 0 - 0 (1 bit)
Channel n Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel Pending Interrupt
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Channel ID
bits : 0 - 1 (2 bit)
OVR : Channel Overrun
bits : 8 - 8 (1 bit)
EVD : Channel Event Detected
bits : 9 - 9 (1 bit)
READY : Ready
bits : 14 - 14 (1 bit)
BUSY : Busy
bits : 15 - 15 (1 bit)
User Multiplexer n
address_offset : 0x100E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x113B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x120 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x121 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x122 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x124 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x125 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x1269 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x128 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x129 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x12A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x12B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x12D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x12E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x12F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x130 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x131 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x132 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x133 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x134 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x135 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x136 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Control
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
User Multiplexer n
address_offset : 0x1398 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Interrupt Enable Clear
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x13D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x13E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
Channel n Status
address_offset : 0x13F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
Interrupt Status
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHINT0 : Channel 0 Pending Interrupt
bits : 0 - 0 (1 bit)
CHINT1 : Channel 1 Pending Interrupt
bits : 1 - 1 (1 bit)
CHINT2 : Channel 2 Pending Interrupt
bits : 2 - 2 (1 bit)
CHINT3 : Channel 3 Pending Interrupt
bits : 3 - 3 (1 bit)
User Multiplexer n
address_offset : 0x14C8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x15F9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x172B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Busy Channels
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSYCH0 : Busy Channel 0
bits : 0 - 0 (1 bit)
BUSYCH1 : Busy Channel 1
bits : 1 - 1 (1 bit)
BUSYCH2 : Busy Channel 2
bits : 2 - 2 (1 bit)
BUSYCH3 : Busy Channel 3
bits : 3 - 3 (1 bit)
User Multiplexer n
address_offset : 0x185E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Control
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x18C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x18D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x18E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
Channel n Status
address_offset : 0x18F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
User Multiplexer n
address_offset : 0x1992 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x1AC7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0x1BFD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Ready Users
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
READYUSR0 : Ready User for Channel 0
bits : 0 - 0 (1 bit)
READYUSR1 : Ready User for Channel 1
bits : 1 - 1 (1 bit)
READYUSR2 : Ready User for Channel 2
bits : 2 - 2 (1 bit)
READYUSR3 : Ready User for Channel 3
bits : 3 - 3 (1 bit)
Interrupt Enable Clear
address_offset : 0x1D4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSCHK : Non-Secure Check Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Enable Set
address_offset : 0x1D5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSCHK : Non-Secure Check Interrupt Enable
bits : 0 - 0 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x1D6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSCHK : Non-Secure Check
bits : 0 - 0 (1 bit)
Channels Security Attribution
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL0 : Non-Secure for Channel 0
bits : 0 - 0 (1 bit)
CHANNEL1 : Non-Secure for Channel 1
bits : 1 - 1 (1 bit)
CHANNEL2 : Non-Secure for Channel 2
bits : 2 - 2 (1 bit)
CHANNEL3 : Non-Secure for Channel 3
bits : 3 - 3 (1 bit)
CHANNEL4 : Non-Secure for Channel 4
bits : 4 - 4 (1 bit)
CHANNEL5 : Non-Secure for Channel 5
bits : 5 - 5 (1 bit)
CHANNEL6 : Non-Secure for Channel 6
bits : 6 - 6 (1 bit)
CHANNEL7 : Non-Secure for Channel 7
bits : 7 - 7 (1 bit)
Non-Secure Channels Check
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL0 : Channel 0 to be checked as non-secured
bits : 0 - 0 (1 bit)
CHANNEL1 : Channel 1 to be checked as non-secured
bits : 1 - 1 (1 bit)
CHANNEL2 : Channel 2 to be checked as non-secured
bits : 2 - 2 (1 bit)
CHANNEL3 : Channel 3 to be checked as non-secured
bits : 3 - 3 (1 bit)
CHANNEL4 : Channel 4 to be checked as non-secured
bits : 4 - 4 (1 bit)
CHANNEL5 : Channel 5 to be checked as non-secured
bits : 5 - 5 (1 bit)
CHANNEL6 : Channel 6 to be checked as non-secured
bits : 6 - 6 (1 bit)
CHANNEL7 : Channel 7 to be checked as non-secured
bits : 7 - 7 (1 bit)
Channel n Control
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Users Security Attribution
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USER0 : Non-Secure for User 0
bits : 0 - 0 (1 bit)
USER1 : Non-Secure for User 1
bits : 1 - 1 (1 bit)
USER2 : Non-Secure for User 2
bits : 2 - 2 (1 bit)
USER3 : Non-Secure for User 3
bits : 3 - 3 (1 bit)
USER4 : Non-Secure for User 4
bits : 4 - 4 (1 bit)
USER5 : Non-Secure for User 5
bits : 5 - 5 (1 bit)
USER6 : Non-Secure for User 6
bits : 6 - 6 (1 bit)
USER7 : Non-Secure for User 7
bits : 7 - 7 (1 bit)
USER8 : Non-Secure for User 8
bits : 8 - 8 (1 bit)
USER9 : Non-Secure for User 9
bits : 9 - 9 (1 bit)
USER10 : Non-Secure for User 10
bits : 10 - 10 (1 bit)
USER11 : Non-Secure for User 11
bits : 11 - 11 (1 bit)
USER12 : Non-Secure for User 12
bits : 12 - 12 (1 bit)
USER13 : Non-Secure for User 13
bits : 13 - 13 (1 bit)
USER14 : Non-Secure for User 14
bits : 14 - 14 (1 bit)
USER15 : Non-Secure for User 15
bits : 15 - 15 (1 bit)
USER16 : Non-Secure for User 16
bits : 16 - 16 (1 bit)
USER17 : Non-Secure for User 17
bits : 17 - 17 (1 bit)
USER18 : Non-Secure for User 18
bits : 18 - 18 (1 bit)
USER19 : Non-Secure for User 19
bits : 19 - 19 (1 bit)
USER20 : Non-Secure for User 20
bits : 20 - 20 (1 bit)
USER21 : Non-Secure for User 21
bits : 21 - 21 (1 bit)
USER22 : Non-Secure for User 22
bits : 22 - 22 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x1E4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x1E5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x1E6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
Channel n Status
address_offset : 0x1E7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
Non-Secure Users Check
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USER0 : User 0 to be checked as non-secured
bits : 0 - 0 (1 bit)
USER1 : User 1 to be checked as non-secured
bits : 1 - 1 (1 bit)
USER2 : User 2 to be checked as non-secured
bits : 2 - 2 (1 bit)
USER3 : User 3 to be checked as non-secured
bits : 3 - 3 (1 bit)
USER4 : User 4 to be checked as non-secured
bits : 4 - 4 (1 bit)
USER5 : User 5 to be checked as non-secured
bits : 5 - 5 (1 bit)
USER6 : User 6 to be checked as non-secured
bits : 6 - 6 (1 bit)
USER7 : User 7 to be checked as non-secured
bits : 7 - 7 (1 bit)
USER8 : User 8 to be checked as non-secured
bits : 8 - 8 (1 bit)
USER9 : User 9 to be checked as non-secured
bits : 9 - 9 (1 bit)
USER10 : User 10 to be checked as non-secured
bits : 10 - 10 (1 bit)
USER11 : User 11 to be checked as non-secured
bits : 11 - 11 (1 bit)
USER12 : User 12 to be checked as non-secured
bits : 12 - 12 (1 bit)
USER13 : User 13 to be checked as non-secured
bits : 13 - 13 (1 bit)
USER14 : User 14 to be checked as non-secured
bits : 14 - 14 (1 bit)
USER15 : User 15 to be checked as non-secured
bits : 15 - 15 (1 bit)
USER16 : User 16 to be checked as non-secured
bits : 16 - 16 (1 bit)
USER17 : User 17 to be checked as non-secured
bits : 17 - 17 (1 bit)
USER18 : User 18 to be checked as non-secured
bits : 18 - 18 (1 bit)
USER19 : User 19 to be checked as non-secured
bits : 19 - 19 (1 bit)
USER20 : User 20 to be checked as non-secured
bits : 20 - 20 (1 bit)
USER21 : User 21 to be checked as non-secured
bits : 21 - 21 (1 bit)
USER22 : User 22 to be checked as non-secured
bits : 22 - 22 (1 bit)
Channel n Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
User Multiplexer n
address_offset : 0x240 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Interrupt Enable Set
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
Channel n Status
address_offset : 0x27 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
User Multiplexer n
address_offset : 0x361 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Users Security Attribution
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USER0 : Non-Secure for User 0
bits : 0 - 0 (1 bit)
USER1 : Non-Secure for User 1
bits : 1 - 1 (1 bit)
USER2 : Non-Secure for User 2
bits : 2 - 2 (1 bit)
USER3 : Non-Secure for User 3
bits : 3 - 3 (1 bit)
USER4 : Non-Secure for User 4
bits : 4 - 4 (1 bit)
USER5 : Non-Secure for User 5
bits : 5 - 5 (1 bit)
USER6 : Non-Secure for User 6
bits : 6 - 6 (1 bit)
USER7 : Non-Secure for User 7
bits : 7 - 7 (1 bit)
USER8 : Non-Secure for User 8
bits : 8 - 8 (1 bit)
USER9 : Non-Secure for User 9
bits : 9 - 9 (1 bit)
USER10 : Non-Secure for User 10
bits : 10 - 10 (1 bit)
USER11 : Non-Secure for User 11
bits : 11 - 11 (1 bit)
USER12 : Non-Secure for User 12
bits : 12 - 12 (1 bit)
USER13 : Non-Secure for User 13
bits : 13 - 13 (1 bit)
USER14 : Non-Secure for User 14
bits : 14 - 14 (1 bit)
USER15 : Non-Secure for User 15
bits : 15 - 15 (1 bit)
USER16 : Non-Secure for User 16
bits : 16 - 16 (1 bit)
USER17 : Non-Secure for User 17
bits : 17 - 17 (1 bit)
USER18 : Non-Secure for User 18
bits : 18 - 18 (1 bit)
USER19 : Non-Secure for User 19
bits : 19 - 19 (1 bit)
USER20 : Non-Secure for User 20
bits : 20 - 20 (1 bit)
USER21 : Non-Secure for User 21
bits : 21 - 21 (1 bit)
USER22 : Non-Secure for User 22
bits : 22 - 22 (1 bit)
Non-Secure Users Check
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USER0 : User 0 to be checked as non-secured
bits : 0 - 0 (1 bit)
USER1 : User 1 to be checked as non-secured
bits : 1 - 1 (1 bit)
USER2 : User 2 to be checked as non-secured
bits : 2 - 2 (1 bit)
USER3 : User 3 to be checked as non-secured
bits : 3 - 3 (1 bit)
USER4 : User 4 to be checked as non-secured
bits : 4 - 4 (1 bit)
USER5 : User 5 to be checked as non-secured
bits : 5 - 5 (1 bit)
USER6 : User 6 to be checked as non-secured
bits : 6 - 6 (1 bit)
USER7 : User 7 to be checked as non-secured
bits : 7 - 7 (1 bit)
USER8 : User 8 to be checked as non-secured
bits : 8 - 8 (1 bit)
USER9 : User 9 to be checked as non-secured
bits : 9 - 9 (1 bit)
USER10 : User 10 to be checked as non-secured
bits : 10 - 10 (1 bit)
USER11 : User 11 to be checked as non-secured
bits : 11 - 11 (1 bit)
USER12 : User 12 to be checked as non-secured
bits : 12 - 12 (1 bit)
USER13 : User 13 to be checked as non-secured
bits : 13 - 13 (1 bit)
USER14 : User 14 to be checked as non-secured
bits : 14 - 14 (1 bit)
USER15 : User 15 to be checked as non-secured
bits : 15 - 15 (1 bit)
USER16 : User 16 to be checked as non-secured
bits : 16 - 16 (1 bit)
USER17 : User 17 to be checked as non-secured
bits : 17 - 17 (1 bit)
USER18 : User 18 to be checked as non-secured
bits : 18 - 18 (1 bit)
USER19 : User 19 to be checked as non-secured
bits : 19 - 19 (1 bit)
USER20 : User 20 to be checked as non-secured
bits : 20 - 20 (1 bit)
USER21 : User 21 to be checked as non-secured
bits : 21 - 21 (1 bit)
USER22 : User 22 to be checked as non-secured
bits : 22 - 22 (1 bit)
Software Event
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHANNEL0 : Channel 0 Software Selection
bits : 0 - 0 (1 bit)
CHANNEL1 : Channel 1 Software Selection
bits : 1 - 1 (1 bit)
CHANNEL2 : Channel 2 Software Selection
bits : 2 - 2 (1 bit)
CHANNEL3 : Channel 3 Software Selection
bits : 3 - 3 (1 bit)
CHANNEL4 : Channel 4 Software Selection
bits : 4 - 4 (1 bit)
CHANNEL5 : Channel 5 Software Selection
bits : 5 - 5 (1 bit)
CHANNEL6 : Channel 6 Software Selection
bits : 6 - 6 (1 bit)
CHANNEL7 : Channel 7 Software Selection
bits : 7 - 7 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
Channel n Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
User Multiplexer n
address_offset : 0x483 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Interrupt Enable Clear
address_offset : 0x4C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x4D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
Channel n Status
address_offset : 0x4F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
User Multiplexer n
address_offset : 0x5A6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
User Multiplexer n
address_offset : 0x6CA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
Channel n Control
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0x7C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
User Multiplexer n
address_offset : 0x7EF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Status
address_offset : 0x7F Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
Priority Control
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI : Channel Priority Number
bits : 0 - 1 (2 bit)
RREN : Round-Robin Scheduling Enable
bits : 7 - 7 (1 bit)
User Multiplexer n
address_offset : 0x915 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0xA3C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Control
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xB5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
User Multiplexer n
address_offset : 0xB64 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Status
address_offset : 0xB7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
User Multiplexer n
address_offset : 0xC8D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0xDB7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
User Multiplexer n
address_offset : 0xEE2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANNEL : Channel Event Selection
bits : 0 - 3 (4 bit)
Channel n Control
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVGEN : Event Generator Selection
bits : 0 - 5 (6 bit)
PATH : Path Selection
bits : 8 - 9 (2 bit)
Enumeration: PATHSelect
0 : SYNCHRONOUS
Synchronous path
1 : RESYNCHRONIZED
Resynchronized path
2 : ASYNCHRONOUS
Asynchronous path
End of enumeration elements list.
EDGSEL : Edge Detection Selection
bits : 10 - 11 (2 bit)
Enumeration: EDGSELSelect
0 : NO_EVT_OUTPUT
No event output when using the resynchronized or synchronous path
1 : RISING_EDGE
Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
2 : FALLING_EDGE
Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
3 : BOTH_EDGES
Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
End of enumeration elements list.
RUNSTDBY : Run in standby
bits : 14 - 14 (1 bit)
ONDEMAND : Generic Clock On Demand
bits : 15 - 15 (1 bit)
Channel n Interrupt Enable Clear
address_offset : 0xF4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Disable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Disable
bits : 1 - 1 (1 bit)
Channel n Interrupt Enable Set
address_offset : 0xF5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun Interrupt Enable
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected Interrupt Enable
bits : 1 - 1 (1 bit)
Channel n Interrupt Flag Status and Clear
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVR : Channel Overrun
bits : 0 - 0 (1 bit)
EVD : Channel Event Detected
bits : 1 - 1 (1 bit)
Channel n Status
address_offset : 0xF7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDYUSR : Ready User
bits : 0 - 0 (1 bit)
BUSYCH : Busy Channel
bits : 1 - 1 (1 bit)
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