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DWT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

COMP

PCSR

COMPARATOR[0]-DWT_COMP

COMPARATOR[0]-DWT_FUNCTION

COMPARATOR[1]-COMPARATOR[0]-DWT_COMP

COMPARATOR[1]-COMPARATOR[0]-DWT_FUNCTION

FUNCTION

LAR

LSR

DEVARCH

DEVTYPE

PIDR4

PIDR5

PIDR6

PIDR7

PIDR0

PIDR1

PIDR2

PIDR3

CIDR0

CIDR1

CIDR2

CIDR3


CTRL

DWT Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CYCCNTENA POSTPRESET POSTINIT CYCTAP SYNCTAP PCSAMPLENA EXCTRCENA CPIEVTENA EXCEVTENA SLEEPEVTENA LSUEVTENA FOLDEVTENA CYCEVTENA CYCDISS NOPRFCNT NOCYCCNT NOEXTTRIG NOTRCPKT NUMCOMP

CYCCNTENA : CYCCNT enable
bits : 0 - 0 (1 bit)

POSTPRESET : POSTCNT preset
bits : 1 - 4 (4 bit)

POSTINIT : POSTCNT initial
bits : 5 - 8 (4 bit)

CYCTAP : Cycle count tap
bits : 9 - 9 (1 bit)

SYNCTAP : Synchronization tap
bits : 10 - 11 (2 bit)

PCSAMPLENA : PC sample enable
bits : 12 - 12 (1 bit)

EXCTRCENA : Exception trace enable
bits : 16 - 16 (1 bit)

CPIEVTENA : CPI event enable
bits : 17 - 17 (1 bit)

EXCEVTENA : Exception event enable
bits : 18 - 18 (1 bit)

SLEEPEVTENA : Sleep event enable
bits : 19 - 19 (1 bit)

LSUEVTENA : LSU event enable
bits : 20 - 20 (1 bit)

FOLDEVTENA : Fold event enable
bits : 21 - 21 (1 bit)

CYCEVTENA : Cycle event enable
bits : 22 - 22 (1 bit)

CYCDISS : Cycle counter disabled secure
bits : 23 - 23 (1 bit)

NOPRFCNT : No profile counters
bits : 24 - 24 (1 bit)

NOCYCCNT : No cycle count
bits : 25 - 25 (1 bit)

NOEXTTRIG : No external triggers
bits : 26 - 26 (1 bit)

NOTRCPKT : No trace packets
bits : 27 - 27 (1 bit)

NUMCOMP : Number of comparators
bits : 28 - 31 (4 bit)


COMP

DWT Comparator Register n
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMP COMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Cycle/PC/data value or data address
bits : 0 - 31 (32 bit)


PCSR

DWT Program Counter Sample Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PCSR PCSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIASAMPLE

EIASAMPLE : Executed instruction address sample
bits : 0 - 31 (32 bit)


COMPARATOR[0]-DWT_COMP

DWT Comparator Register n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPARATOR[0]-DWT_COMP COMPARATOR[0]-DWT_COMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Cycle/PC/data value or data address
bits : 0 - 31 (32 bit)


COMPARATOR[0]-DWT_FUNCTION

DWT Function Register x
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPARATOR[0]-DWT_FUNCTION COMPARATOR[0]-DWT_FUNCTION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH ACTION DATAVSIZE MATCHED ID

MATCH : Match type
bits : 0 - 3 (4 bit)

ACTION : Action on match
bits : 4 - 5 (2 bit)

DATAVSIZE : Data value size
bits : 10 - 11 (2 bit)

MATCHED : Comparator matched
bits : 24 - 24 (1 bit)

ID : Identify capability
bits : 27 - 31 (5 bit)


COMPARATOR[1]-COMPARATOR[0]-DWT_COMP

DWT Comparator Register n
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPARATOR[1]-COMPARATOR[0]-DWT_COMP COMPARATOR[1]-COMPARATOR[0]-DWT_COMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Cycle/PC/data value or data address
bits : 0 - 31 (32 bit)


COMPARATOR[1]-COMPARATOR[0]-DWT_FUNCTION

DWT Function Register x
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPARATOR[1]-COMPARATOR[0]-DWT_FUNCTION COMPARATOR[1]-COMPARATOR[0]-DWT_FUNCTION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH ACTION DATAVSIZE MATCHED ID

MATCH : Match type
bits : 0 - 3 (4 bit)

ACTION : Action on match
bits : 4 - 5 (2 bit)

DATAVSIZE : Data value size
bits : 10 - 11 (2 bit)

MATCHED : Comparator matched
bits : 24 - 24 (1 bit)

ID : Identify capability
bits : 27 - 31 (5 bit)


FUNCTION

DWT Function Register x
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FUNCTION FUNCTION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH ACTION DATAVSIZE MATCHED ID

MATCH : Match type
bits : 0 - 3 (4 bit)

ACTION : Action on match
bits : 4 - 5 (2 bit)

DATAVSIZE : Data value size
bits : 10 - 11 (2 bit)

MATCHED : Comparator matched
bits : 24 - 24 (1 bit)

ID : Identify capability
bits : 27 - 31 (5 bit)


LAR

DWT Software Lock Access Register
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LAR LAR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY

KEY : Lock access control
bits : 0 - 31 (32 bit)

Enumeration: KEYSelect

0xC5ACCE55 : UNLOCK

Unlock key value

End of enumeration elements list.


LSR

DWT Software Lock Status Register
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LSR LSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLI SLK nTT

SLI : Software Lock implemented
bits : 0 - 0 (1 bit)

SLK : Software Lock status
bits : 1 - 1 (1 bit)

nTT : Not thirty-two bit
bits : 2 - 2 (1 bit)


DEVARCH

DWT Device Architecture Register
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVARCH DEVARCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARCHPART ARCHVER REVISION PRESENT ARCHITECT

ARCHPART : Architecture Part
bits : 0 - 11 (12 bit)

ARCHVER : Architecture Version
bits : 12 - 15 (4 bit)

REVISION : Revision
bits : 16 - 19 (4 bit)

PRESENT : DEVARCH Present
bits : 20 - 20 (1 bit)

ARCHITECT : Architect
bits : 21 - 31 (11 bit)


DEVTYPE

DWT Device Type Register
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVTYPE DEVTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAJOR SUB

MAJOR : Major type
bits : 0 - 3 (4 bit)

SUB : Sub-type
bits : 4 - 7 (4 bit)


PIDR4

DWT Peripheral Identification Register 4
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR4 PIDR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DES_2 SIZE

DES_2 : JEP106 continuation code
bits : 0 - 3 (4 bit)

SIZE : 4KB count
bits : 4 - 7 (4 bit)


PIDR5

DWT Peripheral Identification Register 5
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR5 PIDR5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR6

DWT Peripheral Identification Register 6
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR6 PIDR6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR7

DWT Peripheral Identification Register 7
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR7 PIDR7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PIDR0

DWT Peripheral Identification Register 0
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR0 PIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PART_0

PART_0 : Part number bits[7:0]
bits : 0 - 7 (8 bit)


PIDR1

DWT Peripheral Identification Register 1
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR1 PIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PART_1 DES_0

PART_1 : Part number bits[11:8]
bits : 0 - 3 (4 bit)

DES_0 : JEP106 identification code bits [3:0]
bits : 4 - 7 (4 bit)


PIDR2

DWT Peripheral Identification Register 2
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR2 PIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DES_1 JEDEC REVISION

DES_1 : JEP106 identification code bits[6:4]
bits : 0 - 2 (3 bit)

JEDEC : JEDEC assignee value is used
bits : 3 - 3 (1 bit)

REVISION : Component revision
bits : 4 - 7 (4 bit)


PIDR3

DWT Peripheral Identification Register 3
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIDR3 PIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMOD REVAND

CMOD : Customer Modified
bits : 0 - 3 (4 bit)

REVAND : RevAnd
bits : 4 - 7 (4 bit)


CIDR0

DWT Component Identification Register 0
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR0 CIDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_0

PRMBL_0 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)


CIDR1

DWT Component Identification Register 1
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR1 CIDR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_1 CLASS

PRMBL_1 : CoreSight component identification preamble
bits : 0 - 3 (4 bit)

CLASS : CoreSight component class
bits : 4 - 7 (4 bit)


CIDR2

DWT Component Identification Register 2
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR2 CIDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_2

PRMBL_2 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)


CIDR3

DWT Component Identification Register 3
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIDR3 CIDR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRMBL_3

PRMBL_3 : CoreSight component identification preamble
bits : 0 - 7 (8 bit)



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