\n

AC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRLA

CTRLB

COMPCTRL0

COMPCTRL1

SCALER[0]

EVCTRL

COMPCTRL[0]

SYNCBUSY

SCALER[1]

COMPCTRL[1]

INTENCLR

INTENSET

INTFLAG

STATUSA

STATUSB

DBGCTRL

WINCTRL

SCALER0

SCALER1


CTRLA

Control A
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLA CTRLA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SWRST ENABLE

SWRST : Software Reset
bits : 0 - 0 (1 bit)

ENABLE : Enable
bits : 1 - 1 (1 bit)


CTRLB

Control B
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CTRLB CTRLB write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 START0 START1

START0 : Comparator 0 Start Comparison
bits : 0 - 0 (1 bit)

START1 : Comparator 1 Start Comparison
bits : 1 - 1 (1 bit)


COMPCTRL0

Comparator Control n
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPCTRL0 COMPCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SINGLE INTSEL RUNSTDBY MUXNEG MUXPOS SWAP SPEED HYSTEN HYST FLEN OUT

ENABLE : Enable
bits : 1 - 1 (1 bit)

SINGLE : Single-Shot Mode
bits : 2 - 2 (1 bit)

INTSEL : Interrupt Selection
bits : 3 - 4 (2 bit)

Enumeration: INTSELSelect

0 : TOGGLE

Interrupt on comparator output toggle

1 : RISING

Interrupt on comparator output rising

2 : FALLING

Interrupt on comparator output falling

3 : EOC

Interrupt on end of comparison (single-shot mode only)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

MUXNEG : Negative Input Mux Selection
bits : 8 - 10 (3 bit)

Enumeration: MUXNEGSelect

0 : PIN0

I/O pin 0

1 : PIN1

I/O pin 1

2 : PIN2

I/O pin 2

3 : PIN3

I/O pin 3

4 : GND

Ground

5 : VSCALE

VDD scaler

6 : BANDGAP

Internal bandgap voltage

7 : OPAMP

OPAMP output (on AC1)

7 : DAC

DAC output (on AC0)

End of enumeration elements list.

MUXPOS : Positive Input Mux Selection
bits : 12 - 14 (3 bit)

Enumeration: MUXPOSSelect

0 : PIN0

I/O pin 0

1 : PIN1

I/O pin 1

2 : PIN2

I/O pin 2

3 : PIN3

I/O pin 3

4 : VSCALE

VDD Scaler

End of enumeration elements list.

SWAP : Swap Inputs and Invert
bits : 15 - 15 (1 bit)

SPEED : Speed Selection
bits : 16 - 17 (2 bit)

Enumeration: SPEEDSelect

0 : LOW

Low speed

1 : MEDLOW

Medium low speed

2 : MEDHIGH

Medium high speed

3 : HIGH

High speed

End of enumeration elements list.

HYSTEN : Hysteresis Enable
bits : 19 - 19 (1 bit)

HYST : Hysteresis Level
bits : 20 - 21 (2 bit)

Enumeration: HYSTSelect

0 : HYST50

50mV

1 : HYST70

70mV

2 : HYST90

90mV

3 : HYST110

110mV

End of enumeration elements list.

FLEN : Filter Length
bits : 24 - 26 (3 bit)

Enumeration: FLENSelect

0 : OFF

No filtering

1 : MAJ3

3-bit majority function (2 of 3)

2 : MAJ5

5-bit majority function (3 of 5)

End of enumeration elements list.

OUT : Output
bits : 28 - 29 (2 bit)

Enumeration: OUTSelect

0 : OFF

The output of COMPn is not routed to the COMPn I/O port

1 : ASYNC

The asynchronous output of COMPn is routed to the COMPn I/O port

2 : SYNC

The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port

End of enumeration elements list.


COMPCTRL1

Comparator Control n
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPCTRL1 COMPCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SINGLE INTSEL RUNSTDBY MUXNEG MUXPOS SWAP SPEED HYSTEN HYST FLEN OUT

ENABLE : Enable
bits : 1 - 1 (1 bit)

SINGLE : Single-Shot Mode
bits : 2 - 2 (1 bit)

INTSEL : Interrupt Selection
bits : 3 - 4 (2 bit)

Enumeration: INTSELSelect

0 : TOGGLE

Interrupt on comparator output toggle

1 : RISING

Interrupt on comparator output rising

2 : FALLING

Interrupt on comparator output falling

3 : EOC

Interrupt on end of comparison (single-shot mode only)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

MUXNEG : Negative Input Mux Selection
bits : 8 - 10 (3 bit)

Enumeration: MUXNEGSelect

0 : PIN0

I/O pin 0

1 : PIN1

I/O pin 1

2 : PIN2

I/O pin 2

3 : PIN3

I/O pin 3

4 : GND

Ground

5 : VSCALE

VDD scaler

6 : BANDGAP

Internal bandgap voltage

7 : OPAMP

OPAMP output (on AC1)

7 : DAC

DAC output (on AC0)

End of enumeration elements list.

MUXPOS : Positive Input Mux Selection
bits : 12 - 14 (3 bit)

Enumeration: MUXPOSSelect

0 : PIN0

I/O pin 0

1 : PIN1

I/O pin 1

2 : PIN2

I/O pin 2

3 : PIN3

I/O pin 3

4 : VSCALE

VDD Scaler

End of enumeration elements list.

SWAP : Swap Inputs and Invert
bits : 15 - 15 (1 bit)

SPEED : Speed Selection
bits : 16 - 17 (2 bit)

Enumeration: SPEEDSelect

0 : LOW

Low speed

1 : MEDLOW

Medium low speed

2 : MEDHIGH

Medium high speed

3 : HIGH

High speed

End of enumeration elements list.

HYSTEN : Hysteresis Enable
bits : 19 - 19 (1 bit)

HYST : Hysteresis Level
bits : 20 - 21 (2 bit)

Enumeration: HYSTSelect

0 : HYST50

50mV

1 : HYST70

70mV

2 : HYST90

90mV

3 : HYST110

110mV

End of enumeration elements list.

FLEN : Filter Length
bits : 24 - 26 (3 bit)

Enumeration: FLENSelect

0 : OFF

No filtering

1 : MAJ3

3-bit majority function (2 of 3)

2 : MAJ5

5-bit majority function (3 of 5)

End of enumeration elements list.

OUT : Output
bits : 28 - 29 (2 bit)

Enumeration: OUTSelect

0 : OFF

The output of COMPn is not routed to the COMPn I/O port

1 : ASYNC

The asynchronous output of COMPn is routed to the COMPn I/O port

2 : SYNC

The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port

End of enumeration elements list.


SCALER[0]

Scaler n
address_offset : 0x18 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCALER[0] SCALER[0] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE

VALUE : Scaler Value
bits : 0 - 5 (6 bit)


EVCTRL

Event Control
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVCTRL EVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPEO0 COMPEO1 WINEO0 COMPEI0 COMPEI1 INVEI0 INVEI1

COMPEO0 : Comparator 0 Event Output Enable
bits : 0 - 0 (1 bit)

COMPEO1 : Comparator 1 Event Output Enable
bits : 1 - 1 (1 bit)

WINEO0 : Window 0 Event Output Enable
bits : 4 - 4 (1 bit)

COMPEI0 : Comparator 0 Event Input Enable
bits : 8 - 8 (1 bit)

COMPEI1 : Comparator 1 Event Input Enable
bits : 9 - 9 (1 bit)

INVEI0 : Comparator 0 Input Event Invert Enable
bits : 12 - 12 (1 bit)

INVEI1 : Comparator 1 Input Event Invert Enable
bits : 13 - 13 (1 bit)


COMPCTRL[0]

Comparator Control n
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPCTRL[0] COMPCTRL[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SINGLE INTSEL RUNSTDBY MUXNEG MUXPOS SWAP SPEED HYSTEN HYST FLEN OUT

ENABLE : Enable
bits : 1 - 1 (1 bit)

SINGLE : Single-Shot Mode
bits : 2 - 2 (1 bit)

INTSEL : Interrupt Selection
bits : 3 - 4 (2 bit)

Enumeration: INTSELSelect

0 : TOGGLE

Interrupt on comparator output toggle

1 : RISING

Interrupt on comparator output rising

2 : FALLING

Interrupt on comparator output falling

3 : EOC

Interrupt on end of comparison (single-shot mode only)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

MUXNEG : Negative Input Mux Selection
bits : 8 - 10 (3 bit)

Enumeration: MUXNEGSelect

0 : PIN0

I/O pin 0

1 : PIN1

I/O pin 1

2 : PIN2

I/O pin 2

3 : PIN3

I/O pin 3

4 : GND

Ground

5 : VSCALE

VDD scaler

6 : BANDGAP

Internal bandgap voltage

7 : OPAMP

OPAMP output (on AC1)

7 : DAC

DAC output (on AC0)

End of enumeration elements list.

MUXPOS : Positive Input Mux Selection
bits : 12 - 14 (3 bit)

Enumeration: MUXPOSSelect

0 : PIN0

I/O pin 0

1 : PIN1

I/O pin 1

2 : PIN2

I/O pin 2

3 : PIN3

I/O pin 3

4 : VSCALE

VDD Scaler

End of enumeration elements list.

SWAP : Swap Inputs and Invert
bits : 15 - 15 (1 bit)

SPEED : Speed Selection
bits : 16 - 17 (2 bit)

Enumeration: SPEEDSelect

0 : LOW

Low speed

1 : MEDLOW

Medium low speed

2 : MEDHIGH

Medium high speed

3 : HIGH

High speed

End of enumeration elements list.

HYSTEN : Hysteresis Enable
bits : 19 - 19 (1 bit)

HYST : Hysteresis Level
bits : 20 - 21 (2 bit)

Enumeration: HYSTSelect

0 : HYST50

50mV

1 : HYST70

70mV

2 : HYST90

90mV

3 : HYST110

110mV

End of enumeration elements list.

FLEN : Filter Length
bits : 24 - 26 (3 bit)

Enumeration: FLENSelect

0 : OFF

No filtering

1 : MAJ3

3-bit majority function (2 of 3)

2 : MAJ5

5-bit majority function (3 of 5)

End of enumeration elements list.

OUT : Output
bits : 28 - 29 (2 bit)

Enumeration: OUTSelect

0 : OFF

The output of COMPn is not routed to the COMPn I/O port

1 : ASYNC

The asynchronous output of COMPn is routed to the COMPn I/O port

2 : SYNC

The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port

End of enumeration elements list.


SYNCBUSY

Synchronization Busy
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST ENABLE WINCTRL COMPCTRL0 COMPCTRL1

SWRST : Software Reset Synchronization Busy
bits : 0 - 0 (1 bit)

ENABLE : Enable Synchronization Busy
bits : 1 - 1 (1 bit)

WINCTRL : WINCTRL Synchronization Busy
bits : 2 - 2 (1 bit)

COMPCTRL0 : COMPCTRL 0 Synchronization Busy
bits : 3 - 3 (1 bit)

COMPCTRL1 : COMPCTRL 1 Synchronization Busy
bits : 4 - 4 (1 bit)


SCALER[1]

Scaler n
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCALER[1] SCALER[1] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE

VALUE : Scaler Value
bits : 0 - 5 (6 bit)


COMPCTRL[1]

Comparator Control n
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMPCTRL[1] COMPCTRL[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SINGLE INTSEL RUNSTDBY MUXNEG MUXPOS SWAP SPEED HYSTEN HYST FLEN OUT

ENABLE : Enable
bits : 1 - 1 (1 bit)

SINGLE : Single-Shot Mode
bits : 2 - 2 (1 bit)

INTSEL : Interrupt Selection
bits : 3 - 4 (2 bit)

Enumeration: INTSELSelect

0 : TOGGLE

Interrupt on comparator output toggle

1 : RISING

Interrupt on comparator output rising

2 : FALLING

Interrupt on comparator output falling

3 : EOC

Interrupt on end of comparison (single-shot mode only)

End of enumeration elements list.

RUNSTDBY : Run in Standby
bits : 6 - 6 (1 bit)

MUXNEG : Negative Input Mux Selection
bits : 8 - 10 (3 bit)

Enumeration: MUXNEGSelect

0 : PIN0

I/O pin 0

1 : PIN1

I/O pin 1

2 : PIN2

I/O pin 2

3 : PIN3

I/O pin 3

4 : GND

Ground

5 : VSCALE

VDD scaler

6 : BANDGAP

Internal bandgap voltage

7 : OPAMP

OPAMP output (on AC1)

7 : DAC

DAC output (on AC0)

End of enumeration elements list.

MUXPOS : Positive Input Mux Selection
bits : 12 - 14 (3 bit)

Enumeration: MUXPOSSelect

0 : PIN0

I/O pin 0

1 : PIN1

I/O pin 1

2 : PIN2

I/O pin 2

3 : PIN3

I/O pin 3

4 : VSCALE

VDD Scaler

End of enumeration elements list.

SWAP : Swap Inputs and Invert
bits : 15 - 15 (1 bit)

SPEED : Speed Selection
bits : 16 - 17 (2 bit)

Enumeration: SPEEDSelect

0 : LOW

Low speed

1 : MEDLOW

Medium low speed

2 : MEDHIGH

Medium high speed

3 : HIGH

High speed

End of enumeration elements list.

HYSTEN : Hysteresis Enable
bits : 19 - 19 (1 bit)

HYST : Hysteresis Level
bits : 20 - 21 (2 bit)

Enumeration: HYSTSelect

0 : HYST50

50mV

1 : HYST70

70mV

2 : HYST90

90mV

3 : HYST110

110mV

End of enumeration elements list.

FLEN : Filter Length
bits : 24 - 26 (3 bit)

Enumeration: FLENSelect

0 : OFF

No filtering

1 : MAJ3

3-bit majority function (2 of 3)

2 : MAJ5

5-bit majority function (3 of 5)

End of enumeration elements list.

OUT : Output
bits : 28 - 29 (2 bit)

Enumeration: OUTSelect

0 : OFF

The output of COMPn is not routed to the COMPn I/O port

1 : ASYNC

The asynchronous output of COMPn is routed to the COMPn I/O port

2 : SYNC

The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port

End of enumeration elements list.


INTENCLR

Interrupt Enable Clear
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENCLR INTENCLR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 COMP0 COMP1 WIN0

COMP0 : Comparator 0 Interrupt Enable
bits : 0 - 0 (1 bit)

COMP1 : Comparator 1 Interrupt Enable
bits : 1 - 1 (1 bit)

WIN0 : Window 0 Interrupt Enable
bits : 4 - 4 (1 bit)


INTENSET

Interrupt Enable Set
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENSET INTENSET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 COMP0 COMP1 WIN0

COMP0 : Comparator 0 Interrupt Enable
bits : 0 - 0 (1 bit)

COMP1 : Comparator 1 Interrupt Enable
bits : 1 - 1 (1 bit)

WIN0 : Window 0 Interrupt Enable
bits : 4 - 4 (1 bit)


INTFLAG

Interrupt Flag Status and Clear
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFLAG INTFLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 COMP0 COMP1 WIN0

COMP0 : Comparator 0
bits : 0 - 0 (1 bit)

COMP1 : Comparator 1
bits : 1 - 1 (1 bit)

WIN0 : Window 0
bits : 4 - 4 (1 bit)


STATUSA

Status A
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSA STATUSA read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STATE0 STATE1 WSTATE0

STATE0 : Comparator 0 Current State
bits : 0 - 0 (1 bit)

STATE1 : Comparator 1 Current State
bits : 1 - 1 (1 bit)

WSTATE0 : Window 0 Current State
bits : 4 - 5 (2 bit)

Enumeration: WSTATE0Select

0 : ABOVE

Signal is above window

1 : INSIDE

Signal is inside window

2 : BELOW

Signal is below window

End of enumeration elements list.


STATUSB

Status B
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUSB STATUSB read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 READY0 READY1

READY0 : Comparator 0 Ready
bits : 0 - 0 (1 bit)

READY1 : Comparator 1 Ready
bits : 1 - 1 (1 bit)


DBGCTRL

Debug Control
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGCTRL DBGCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DBGRUN

DBGRUN : Debug Run
bits : 0 - 0 (1 bit)


WINCTRL

Window Control
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WINCTRL WINCTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WEN0 WINTSEL0

WEN0 : Window 0 Mode Enable
bits : 0 - 0 (1 bit)

WINTSEL0 : Window 0 Interrupt Selection
bits : 1 - 2 (2 bit)

Enumeration: WINTSEL0Select

0 : ABOVE

Interrupt on signal above window

1 : INSIDE

Interrupt on signal inside window

2 : BELOW

Interrupt on signal below window

3 : OUTSIDE

Interrupt on signal outside window

End of enumeration elements list.


SCALER0

Scaler n
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCALER0 SCALER0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE

VALUE : Scaler Value
bits : 0 - 5 (6 bit)


SCALER1

Scaler n
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCALER1 SCALER1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 VALUE

VALUE : Scaler Value
bits : 0 - 5 (6 bit)



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