\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Enable Clear
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOD33RDY : BOD33 Ready
bits : 0 - 0 (1 bit)
BOD33DET : BOD33 Detection
bits : 1 - 1 (1 bit)
B33SRDY : BOD33 Synchronization Ready
bits : 2 - 2 (1 bit)
BOD12RDY : BOD12 Ready
bits : 3 - 3 (1 bit)
BOD12DET : BOD12 Detection
bits : 4 - 4 (1 bit)
B12SRDY : BOD12 Synchronization Ready
bits : 5 - 5 (1 bit)
VREGRDY : Voltage Regulator Ready
bits : 8 - 8 (1 bit)
VCORERDY : VDDCORE Ready
bits : 10 - 10 (1 bit)
ULPVREFRDY : ULPVREF Voltage Reference Ready
bits : 11 - 11 (1 bit)
BOD33 Control
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable
bits : 1 - 1 (1 bit)
HYST : Hysteresis Enable
bits : 2 - 2 (1 bit)
ACTION : Action when Threshold Crossed
bits : 3 - 4 (2 bit)
Enumeration: ACTIONSelect
0x0 : NONE
No action
0x1 : RESET
The BOD33 generates a reset
0x2 : INT
The BOD33 generates an interrupt
0x3 : BKUP
The BOD33 puts the device in backup sleep mode if VMON=0
End of enumeration elements list.
STDBYCFG : Configuration in Standby mode
bits : 5 - 5 (1 bit)
RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)
ACTCFG : Configuration in Active mode
bits : 8 - 8 (1 bit)
REFSEL : BOD33 Voltage Reference Selection
bits : 11 - 11 (1 bit)
Enumeration: REFSELSelect
0 : SEL_VREFDETREF
Selects VREFDETREF for the BOD33
1 : SEL_ULPVREF
Selects ULPVREF for the BOD33
End of enumeration elements list.
PSEL : Prescaler Select
bits : 12 - 15 (4 bit)
Enumeration: PSELSelect
0x0 : DIV2
Divide clock by 2
0x1 : DIV4
Divide clock by 4
0x2 : DIV8
Divide clock by 8
0x3 : DIV16
Divide clock by 16
0x4 : DIV32
Divide clock by 32
0x5 : DIV64
Divide clock by 64
0x6 : DIV128
Divide clock by 128
0x7 : DIV256
Divide clock by 256
0x8 : DIV512
Divide clock by 512
0x9 : DIV1024
Divide clock by 1024
0xA : DIV2048
Divide clock by 2048
0xB : DIV4096
Divide clock by 4096
0xC : DIV8192
Divide clock by 8192
0xD : DIV16384
Divide clock by 16384
0xE : DIV32768
Divide clock by 32768
0xF : DIV65536
Divide clock by 65536
End of enumeration elements list.
LEVEL : Threshold Level for VDD
bits : 16 - 21 (6 bit)
BOD12 Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable
bits : 1 - 1 (1 bit)
HYST : Hysteresis Enable
bits : 2 - 2 (1 bit)
ACTION : Action when Threshold Crossed
bits : 3 - 4 (2 bit)
Enumeration: ACTIONSelect
0x0 : NONE
No action
0x1 : RESET
The BOD12 generates a reset
0x2 : INT
The BOD12 generates an interrupt
End of enumeration elements list.
STDBYCFG : Configuration in Standby mode
bits : 5 - 5 (1 bit)
RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)
ACTCFG : Configuration in Active mode
bits : 8 - 8 (1 bit)
PSEL : Prescaler Select
bits : 12 - 15 (4 bit)
Enumeration: PSELSelect
0x0 : DIV2
Divide clock by 2
0x1 : DIV4
Divide clock by 4
0x2 : DIV8
Divide clock by 8
0x3 : DIV16
Divide clock by 16
0x4 : DIV32
Divide clock by 32
0x5 : DIV64
Divide clock by 64
0x6 : DIV128
Divide clock by 128
0x7 : DIV256
Divide clock by 256
0x8 : DIV512
Divide clock by 512
0x9 : DIV1024
Divide clock by 1024
0xA : DIV2048
Divide clock by 2048
0xB : DIV4096
Divide clock by 4096
0xC : DIV8192
Divide clock by 8192
0xD : DIV16384
Divide clock by 16384
0xE : DIV32768
Divide clock by 32768
0xF : DIV65536
Divide clock by 65536
End of enumeration elements list.
LEVEL : Threshold Level
bits : 16 - 21 (6 bit)
VREG Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable
bits : 1 - 1 (1 bit)
SEL : Voltage Regulator Selection in active mode
bits : 2 - 3 (2 bit)
Enumeration: SELSelect
0x0 : LDO
LDO selection
0x1 : BUCK
Buck selection
End of enumeration elements list.
STDBYPL0 : Standby in PL0
bits : 5 - 5 (1 bit)
RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)
LPEFF : Low Power efficiency
bits : 8 - 8 (1 bit)
VREFSEL : Voltage Regulator Voltage Reference Selection
bits : 9 - 9 (1 bit)
VSVSTEP : Voltage Scaling Voltage Step
bits : 16 - 19 (4 bit)
VSPER : Voltage Scaling Period
bits : 24 - 31 (8 bit)
VREF Control
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEN : Temperature Sensor Output Enable
bits : 1 - 1 (1 bit)
VREFOE : Voltage Reference Output Enable
bits : 2 - 2 (1 bit)
TSSEL : Temperature Sensor Selection
bits : 3 - 3 (1 bit)
RUNSTDBY : Run during Standby
bits : 6 - 6 (1 bit)
ONDEMAND : On Demand Control
bits : 7 - 7 (1 bit)
SEL : Voltage Reference Selection
bits : 16 - 19 (4 bit)
Enumeration: SELSelect
0x0 : 1V0
1.0V voltage reference typical value
0x1 : 1V1
1.1V voltage reference typical value
0x2 : 1V2
1.2V voltage reference typical value
0x3 : 1V25
1.25V voltage reference typical value
0x4 : 2V0
2.0V voltage reference typical value
0x5 : 2V2
2.2V voltage reference typical value
0x6 : 2V4
2.4V voltage reference typical value
0x7 : 2V5
2.5V voltage reference typical value
End of enumeration elements list.
Event Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOD33DETEO : BOD33 Detection Event Output Enable
bits : 1 - 1 (1 bit)
BOD12DETEO : BOD12 Detection Event Output Enable
bits : 4 - 4 (1 bit)
VREG Suspend Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREGSEN : Enable Voltage Regulator Suspend
bits : 0 - 0 (1 bit)
Interrupt Enable Set
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOD33RDY : BOD33 Ready
bits : 0 - 0 (1 bit)
BOD33DET : BOD33 Detection
bits : 1 - 1 (1 bit)
B33SRDY : BOD33 Synchronization Ready
bits : 2 - 2 (1 bit)
BOD12RDY : BOD12 Ready
bits : 3 - 3 (1 bit)
BOD12DET : BOD12 Detection
bits : 4 - 4 (1 bit)
B12SRDY : BOD12 Synchronization Ready
bits : 5 - 5 (1 bit)
VREGRDY : Voltage Regulator Ready
bits : 8 - 8 (1 bit)
VCORERDY : VDDCORE Ready
bits : 10 - 10 (1 bit)
ULPVREFRDY : ULPVREF Voltage Reference Ready
bits : 11 - 11 (1 bit)
Interrupt Flag Status and Clear
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOD33RDY : BOD33 Ready
bits : 0 - 0 (1 bit)
BOD33DET : BOD33 Detection
bits : 1 - 1 (1 bit)
B33SRDY : BOD33 Synchronization Ready
bits : 2 - 2 (1 bit)
BOD12RDY : BOD12 Ready
bits : 3 - 3 (1 bit)
BOD12DET : BOD12 Detection
bits : 4 - 4 (1 bit)
B12SRDY : BOD12 Synchronization Ready
bits : 5 - 5 (1 bit)
VREGRDY : Voltage Regulator Ready
bits : 8 - 8 (1 bit)
VCORERDY : VDDCORE Ready
bits : 10 - 10 (1 bit)
ULPVREFRDY : ULPVREF Voltage Reference Ready
bits : 11 - 11 (1 bit)
Power and Clocks Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOD33RDY : BOD33 Ready
bits : 0 - 0 (1 bit)
BOD33DET : BOD33 Detection
bits : 1 - 1 (1 bit)
B33SRDY : BOD33 Synchronization Ready
bits : 2 - 2 (1 bit)
BOD12RDY : BOD12 Ready
bits : 3 - 3 (1 bit)
BOD12DET : BOD12 Detection
bits : 4 - 4 (1 bit)
B12SRDY : BOD12 Synchronization Ready
bits : 5 - 5 (1 bit)
VREGRDY : Voltage Regulator Ready
bits : 8 - 8 (1 bit)
VCORERDY : VDDCORE Ready
bits : 10 - 10 (1 bit)
ULPVREFRDY : Low Power Voltage Reference Ready
bits : 12 - 12 (1 bit)
ULPBIASRDY : Low Power Voltage Bias Ready
bits : 13 - 13 (1 bit)
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