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QUADSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

DLR

CCR

AR

ABR

DR

PSMKR

PSMAR

PIR

LPTR

DCR

SR

FCR


CR

control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN ABORT DMAEN TCEN SSHIFT DFM FSEL FTHRES TEIE TCIE FTIE SMIE TOIE APMS PMM PRESCALER

EN : Enable
bits : 0 - 0 (1 bit)

ABORT : Abort request
bits : 1 - 1 (1 bit)

DMAEN : DMA enable
bits : 2 - 2 (1 bit)

TCEN : Timeout counter enable
bits : 3 - 3 (1 bit)

SSHIFT : Sample shift
bits : 4 - 4 (1 bit)

DFM : Dual-flash mode
bits : 6 - 6 (1 bit)

FSEL : FLASH memory selection
bits : 7 - 7 (1 bit)

FTHRES : IFO threshold level
bits : 8 - 12 (5 bit)

TEIE : Transfer error interrupt enable
bits : 16 - 16 (1 bit)

TCIE : Transfer complete interrupt enable
bits : 17 - 17 (1 bit)

FTIE : FIFO threshold interrupt enable
bits : 18 - 18 (1 bit)

SMIE : Status match interrupt enable
bits : 19 - 19 (1 bit)

TOIE : TimeOut interrupt enable
bits : 20 - 20 (1 bit)

APMS : Automatic poll mode stop
bits : 22 - 22 (1 bit)

PMM : Polling match mode
bits : 23 - 23 (1 bit)

PRESCALER : Clock prescaler
bits : 24 - 31 (8 bit)


DLR

data length register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DLR DLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DL

DL : Data length
bits : 0 - 31 (32 bit)


CCR

communication configuration register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSTRUCTION IMODE ADMODE ADSIZE ABMODE ABSIZE DCYC DMODE FMODE SIOO DHHC DDRM

INSTRUCTION : Instruction
bits : 0 - 7 (8 bit)

IMODE : Instruction mode
bits : 8 - 9 (2 bit)

ADMODE : Address mode
bits : 10 - 11 (2 bit)

ADSIZE : Address size
bits : 12 - 13 (2 bit)

ABMODE : Alternate bytes mode
bits : 14 - 15 (2 bit)

ABSIZE : Alternate bytes size
bits : 16 - 17 (2 bit)

DCYC : Number of dummy cycles
bits : 18 - 22 (5 bit)

DMODE : Data mode
bits : 24 - 25 (2 bit)

FMODE : Functional mode
bits : 26 - 27 (2 bit)

SIOO : Send instruction only once mode
bits : 28 - 28 (1 bit)

DHHC : DDR hold half cycle
bits : 30 - 30 (1 bit)

DDRM : Double data rate mode
bits : 31 - 31 (1 bit)


AR

address register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AR AR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Address
bits : 0 - 31 (32 bit)


ABR

ABR
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABR ABR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALTERNATE

ALTERNATE : ALTERNATE
bits : 0 - 31 (32 bit)


DR

data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Data
bits : 0 - 31 (32 bit)


PSMKR

polling status mask register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSMKR PSMKR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Status mask
bits : 0 - 31 (32 bit)


PSMAR

polling status match register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSMAR PSMAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MATCH

MATCH : Status match
bits : 0 - 31 (32 bit)


PIR

polling interval register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIR PIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERVAL

INTERVAL : Polling interval
bits : 0 - 15 (16 bit)


LPTR

low-power timeout register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPTR LPTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT

TIMEOUT : Timeout period
bits : 0 - 15 (16 bit)


DCR

device configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCR DCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKMODE CSHT FSIZE

CKMODE : Mode 0 / mode 3
bits : 0 - 0 (1 bit)

CSHT : Chip select high time
bits : 8 - 10 (3 bit)

FSIZE : FLASH memory size
bits : 16 - 20 (5 bit)


SR

status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEF TCF FTF SMF TOF BUSY FLEVEL

TEF : Transfer error flag
bits : 0 - 0 (1 bit)

TCF : Transfer complete flag
bits : 1 - 1 (1 bit)

FTF : FIFO threshold flag
bits : 2 - 2 (1 bit)

SMF : Status match flag
bits : 3 - 3 (1 bit)

TOF : Timeout flag
bits : 4 - 4 (1 bit)

BUSY : Busy
bits : 5 - 5 (1 bit)

FLEVEL : FIFO level
bits : 8 - 14 (7 bit)


FCR

flag clear register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCR FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTEF CTCF CSMF CTOF

CTEF : Clear transfer error flag
bits : 0 - 0 (1 bit)

CTCF : Clear transfer complete flag
bits : 1 - 1 (1 bit)

CSMF : Clear status match flag
bits : 3 - 3 (1 bit)

CTOF : Clear timeout flag
bits : 4 - 4 (1 bit)



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