Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected
PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV
PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD
PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM
PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD
PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV
PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD
PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM
PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD
PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR
PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY
PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD
PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD
PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD
PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT
PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT
PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD
PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV
PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD
PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM
PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD
PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR
PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY
PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD
PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD
PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD
PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT
PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT
PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD
PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV
PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD
PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM
PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD
PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV
PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD
PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM
PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD
PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR
PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY
PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD
PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD
PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD
PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT
PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT
PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD
PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV
PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD
PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM
PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD
PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV
PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM
PWM Clock Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVA : CLKA Divide Factor
bits : 0 - 7 (8 bit)
Enumeration: DIVASelect
0 : CLKA_POFF
CLKA clock is turned off
1 : PREA
CLKA clock is clock selected by PREA
End of enumeration elements list.
PREA : CLKA Source Clock Selection
bits : 8 - 11 (4 bit)
Enumeration: PREASelect
0x0 : CLK
Peripheral clock
0x1 : CLK_DIV2
Peripheral clock/2
0x2 : CLK_DIV4
Peripheral clock/4
0x3 : CLK_DIV8
Peripheral clock/8
0x4 : CLK_DIV16
Peripheral clock/16
0x5 : CLK_DIV32
Peripheral clock/32
0x6 : CLK_DIV64
Peripheral clock/64
0x7 : CLK_DIV128
Peripheral clock/128
0x8 : CLK_DIV256
Peripheral clock/256
0x9 : CLK_DIV512
Peripheral clock/512
0xA : CLK_DIV1024
Peripheral clock/1024
End of enumeration elements list.
DIVB : CLKB Divide Factor
bits : 16 - 23 (8 bit)
Enumeration: DIVBSelect
0 : CLKB_POFF
CLKB clock is turned off
1 : PREB
CLKB clock is clock selected by PREB
End of enumeration elements list.
PREB : CLKB Source Clock Selection
bits : 24 - 27 (4 bit)
Enumeration: PREBSelect
0x0 : CLK
Peripheral clock
0x1 : CLK_DIV2
Peripheral clock/2
0x2 : CLK_DIV4
Peripheral clock/4
0x3 : CLK_DIV8
Peripheral clock/8
0x4 : CLK_DIV16
Peripheral clock/16
0x5 : CLK_DIV32
Peripheral clock/32
0x6 : CLK_DIV64
Peripheral clock/64
0x7 : CLK_DIV128
Peripheral clock/128
0x8 : CLK_DIV256
Peripheral clock/256
0x9 : CLK_DIV512
Peripheral clock/512
0xA : CLK_DIV1024
Peripheral clock/1024
End of enumeration elements list.
PWM Clock Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVA : CLKA Divide Factor
bits : 0 - 7 (8 bit)
Enumeration: DIVASelect
0 : CLKA_POFF
CLKA clock is turned off
1 : PREA
CLKA clock is clock selected by PREA
End of enumeration elements list.
PREA : CLKA Source Clock Selection
bits : 8 - 11 (4 bit)
Enumeration: PREASelect
0x0 : CLK
Peripheral clock
0x1 : CLK_DIV2
Peripheral clock/2
0x2 : CLK_DIV4
Peripheral clock/4
0x3 : CLK_DIV8
Peripheral clock/8
0x4 : CLK_DIV16
Peripheral clock/16
0x5 : CLK_DIV32
Peripheral clock/32
0x6 : CLK_DIV64
Peripheral clock/64
0x7 : CLK_DIV128
Peripheral clock/128
0x8 : CLK_DIV256
Peripheral clock/256
0x9 : CLK_DIV512
Peripheral clock/512
0xA : CLK_DIV1024
Peripheral clock/1024
End of enumeration elements list.
DIVB : CLKB Divide Factor
bits : 16 - 23 (8 bit)
Enumeration: DIVBSelect
0 : CLKB_POFF
CLKB clock is turned off
1 : PREB
CLKB clock is clock selected by PREB
End of enumeration elements list.
PREB : CLKB Source Clock Selection
bits : 24 - 27 (4 bit)
Enumeration: PREBSelect
0x0 : CLK
Peripheral clock
0x1 : CLK_DIV2
Peripheral clock/2
0x2 : CLK_DIV4
Peripheral clock/4
0x3 : CLK_DIV8
Peripheral clock/8
0x4 : CLK_DIV16
Peripheral clock/16
0x5 : CLK_DIV32
Peripheral clock/32
0x6 : CLK_DIV64
Peripheral clock/64
0x7 : CLK_DIV128
Peripheral clock/128
0x8 : CLK_DIV256
Peripheral clock/256
0x9 : CLK_DIV512
Peripheral clock/512
0xA : CLK_DIV1024
Peripheral clock/1024
End of enumeration elements list.
PWM Comparison 0 Value Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Channel Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
Enumeration: CPRESelect
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
Enumeration: CALGSelect
0x0 : LEFT_ALIGNED
Left aligned
0x1 : CENTER_ALIGNED
Center aligned
End of enumeration elements list.
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
Enumeration: CPOLSelect
0x0 : LOW_POLARITY
Waveform starts at low level
0x1 : HIGH_POLARITY
Waveform starts at high level
End of enumeration elements list.
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
Enumeration: CESSelect
0x0 : SINGLE_EVENT
At the end of PWM period
0x1 : DOUBLE_EVENT
At half of PWM period AND at the end of PWM period
End of enumeration elements list.
UPDS : Update Selection
bits : 11 - 11 (1 bit)
Enumeration: UPDSSelect
0x0 : UPDATE_AT_PERIOD
At the next end of PWM period
0x1 : UPDATE_AT_HALF_PERIOD
At the next end of Half PWM period
End of enumeration elements list.
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
PWM Clock Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVA : CLKA Divide Factor
bits : 0 - 7 (8 bit)
access : read-write
Enumeration: DIVASelect
0 : CLKA_POFF
CLKA clock is turned off
1 : PREA
CLKA clock is clock selected by PREA
End of enumeration elements list.
PREA : CLKA Source Clock Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration: PREASelect
0x0 : CLK
Peripheral clock
0x1 : CLK_DIV2
Peripheral clock/2
0x2 : CLK_DIV4
Peripheral clock/4
0x3 : CLK_DIV8
Peripheral clock/8
0x4 : CLK_DIV16
Peripheral clock/16
0x5 : CLK_DIV32
Peripheral clock/32
0x6 : CLK_DIV64
Peripheral clock/64
0x7 : CLK_DIV128
Peripheral clock/128
0x8 : CLK_DIV256
Peripheral clock/256
0x9 : CLK_DIV512
Peripheral clock/512
0xA : CLK_DIV1024
Peripheral clock/1024
End of enumeration elements list.
DIVB : CLKB Divide Factor
bits : 16 - 23 (8 bit)
access : read-write
Enumeration: DIVBSelect
0 : CLKB_POFF
CLKB clock is turned off
1 : PREB
CLKB clock is clock selected by PREB
End of enumeration elements list.
PREB : CLKB Source Clock Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration: PREBSelect
0x0 : CLK
Peripheral clock
0x1 : CLK_DIV2
Peripheral clock/2
0x2 : CLK_DIV4
Peripheral clock/4
0x3 : CLK_DIV8
Peripheral clock/8
0x4 : CLK_DIV16
Peripheral clock/16
0x5 : CLK_DIV32
Peripheral clock/32
0x6 : CLK_DIV64
Peripheral clock/64
0x7 : CLK_DIV128
Peripheral clock/128
0x8 : CLK_DIV256
Peripheral clock/256
0x9 : CLK_DIV512
Peripheral clock/512
0xA : CLK_DIV1024
Peripheral clock/1024
End of enumeration elements list.
PWM Comparison 0 Value Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Channel Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
Enumeration: CPRESelect
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
Enumeration: CALGSelect
0x0 : LEFT_ALIGNED
Left aligned
0x1 : CENTER_ALIGNED
Center aligned
End of enumeration elements list.
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
Enumeration: CPOLSelect
0x0 : LOW_POLARITY
Waveform starts at low level
0x1 : HIGH_POLARITY
Waveform starts at high level
End of enumeration elements list.
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
Enumeration: CESSelect
0x0 : SINGLE_EVENT
At the end of PWM period
0x1 : DOUBLE_EVENT
At half of PWM period AND at the end of PWM period
End of enumeration elements list.
UPDS : Update Selection
bits : 11 - 11 (1 bit)
Enumeration: UPDSSelect
0x0 : UPDATE_AT_PERIOD
At the next end of PWM period
0x1 : UPDATE_AT_HALF_PERIOD
At the next end of Half PWM period
End of enumeration elements list.
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
PWM Interrupt Enable Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Enable
bits : 0 - 0 (1 bit)
CHID1 : Counter Event on Channel 1 Interrupt Enable
bits : 1 - 1 (1 bit)
CHID2 : Counter Event on Channel 2 Interrupt Enable
bits : 2 - 2 (1 bit)
CHID3 : Counter Event on Channel 3 Interrupt Enable
bits : 3 - 3 (1 bit)
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)
PWM Interrupt Enable Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Enable
bits : 0 - 0 (1 bit)
CHID1 : Counter Event on Channel 1 Interrupt Enable
bits : 1 - 1 (1 bit)
CHID2 : Counter Event on Channel 2 Interrupt Enable
bits : 2 - 2 (1 bit)
CHID3 : Counter Event on Channel 3 Interrupt Enable
bits : 3 - 3 (1 bit)
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)
PWM Channel Period Update Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
PWM Interrupt Enable Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Counter Event on Channel 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Counter Event on Channel 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Counter Event on Channel 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
PWM Channel Period Update Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
PWM Comparison 0 Value Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Comparison 0 Value Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 0 Value Update Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Comparison 0 Value Update Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 0 Mode Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Comparison 0 Mode Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 0 Mode Update Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Comparison 0 Mode Update Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Interrupt Disable Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Disable
bits : 0 - 0 (1 bit)
CHID1 : Counter Event on Channel 1 Interrupt Disable
bits : 1 - 1 (1 bit)
CHID2 : Counter Event on Channel 2 Interrupt Disable
bits : 2 - 2 (1 bit)
CHID3 : Counter Event on Channel 3 Interrupt Disable
bits : 3 - 3 (1 bit)
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Disable
bits : 16 - 16 (1 bit)
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Disable
bits : 17 - 17 (1 bit)
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Disable
bits : 18 - 18 (1 bit)
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Disable
bits : 19 - 19 (1 bit)
PWM Interrupt Disable Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Disable
bits : 0 - 0 (1 bit)
CHID1 : Counter Event on Channel 1 Interrupt Disable
bits : 1 - 1 (1 bit)
CHID2 : Counter Event on Channel 2 Interrupt Disable
bits : 2 - 2 (1 bit)
CHID3 : Counter Event on Channel 3 Interrupt Disable
bits : 3 - 3 (1 bit)
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Disable
bits : 16 - 16 (1 bit)
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Disable
bits : 17 - 17 (1 bit)
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Disable
bits : 18 - 18 (1 bit)
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Disable
bits : 19 - 19 (1 bit)
PWM Channel Counter Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
PWM Interrupt Disable Register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Counter Event on Channel 1 Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Counter Event on Channel 2 Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Counter Event on Channel 3 Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
PWM Channel Counter Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
PWM Comparison 1 Value Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 1 Value Update Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 1 Mode Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 1 Mode Update Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 2 Value Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 2 Value Update Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 2 Mode Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 2 Mode Update Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 3 Value Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 3 Value Update Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 3 Mode Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 3 Mode Update Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 4 Value Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 4 Value Update Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Event Line 0 Mode Register 0
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
PWM Comparison 4 Mode Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 4 Mode Update Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Interrupt Mask Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Mask
bits : 0 - 0 (1 bit)
CHID1 : Counter Event on Channel 1 Interrupt Mask
bits : 1 - 1 (1 bit)
CHID2 : Counter Event on Channel 2 Interrupt Mask
bits : 2 - 2 (1 bit)
CHID3 : Counter Event on Channel 3 Interrupt Mask
bits : 3 - 3 (1 bit)
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Mask
bits : 16 - 16 (1 bit)
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Mask
bits : 17 - 17 (1 bit)
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Mask
bits : 18 - 18 (1 bit)
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Mask
bits : 19 - 19 (1 bit)
PWM Interrupt Mask Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Mask
bits : 0 - 0 (1 bit)
CHID1 : Counter Event on Channel 1 Interrupt Mask
bits : 1 - 1 (1 bit)
CHID2 : Counter Event on Channel 2 Interrupt Mask
bits : 2 - 2 (1 bit)
CHID3 : Counter Event on Channel 3 Interrupt Mask
bits : 3 - 3 (1 bit)
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Mask
bits : 16 - 16 (1 bit)
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Mask
bits : 17 - 17 (1 bit)
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Mask
bits : 18 - 18 (1 bit)
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Mask
bits : 19 - 19 (1 bit)
PWM Channel Dead Time Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Interrupt Mask Register 1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0 Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Counter Event on Channel 1 Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Counter Event on Channel 2 Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Counter Event on Channel 3 Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
FCHID0 : Fault Protection Trigger on Channel 0 Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
FCHID1 : Fault Protection Trigger on Channel 1 Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
FCHID2 : Fault Protection Trigger on Channel 2 Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
FCHID3 : Fault Protection Trigger on Channel 3 Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
PWM Channel Dead Time Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Comparison 5 Value Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 5 Value Update Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 5 Mode Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 5 Mode Update Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 6 Value Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 6 Value Update Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 6 Mode Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 6 Mode Update Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Comparison 7 Value Register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
access : read-write
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Comparison 7 Value Update Register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
access : write-only
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
access : write-only
PWM Comparison 7 Mode Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
access : read-write
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
access : read-write
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
access : read-write
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
access : read-write
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
access : read-write
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
access : read-write
PWM Comparison 7 Mode Update Register
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
access : write-only
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
access : write-only
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
access : write-only
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
access : write-only
PWM Interrupt Status Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0
bits : 0 - 0 (1 bit)
CHID1 : Counter Event on Channel 1
bits : 1 - 1 (1 bit)
CHID2 : Counter Event on Channel 2
bits : 2 - 2 (1 bit)
CHID3 : Counter Event on Channel 3
bits : 3 - 3 (1 bit)
FCHID0 : Fault Protection Trigger on Channel 0
bits : 16 - 16 (1 bit)
FCHID1 : Fault Protection Trigger on Channel 1
bits : 17 - 17 (1 bit)
FCHID2 : Fault Protection Trigger on Channel 2
bits : 18 - 18 (1 bit)
FCHID3 : Fault Protection Trigger on Channel 3
bits : 19 - 19 (1 bit)
PWM Interrupt Status Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0
bits : 0 - 0 (1 bit)
CHID1 : Counter Event on Channel 1
bits : 1 - 1 (1 bit)
CHID2 : Counter Event on Channel 2
bits : 2 - 2 (1 bit)
CHID3 : Counter Event on Channel 3
bits : 3 - 3 (1 bit)
FCHID0 : Fault Protection Trigger on Channel 0
bits : 16 - 16 (1 bit)
FCHID1 : Fault Protection Trigger on Channel 1
bits : 17 - 17 (1 bit)
FCHID2 : Fault Protection Trigger on Channel 2
bits : 18 - 18 (1 bit)
FCHID3 : Fault Protection Trigger on Channel 3
bits : 19 - 19 (1 bit)
PWM Channel Dead Time Update Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Interrupt Status Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Counter Event on Channel 0
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Counter Event on Channel 1
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Counter Event on Channel 2
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Counter Event on Channel 3
bits : 3 - 3 (1 bit)
access : read-only
FCHID0 : Fault Protection Trigger on Channel 0
bits : 16 - 16 (1 bit)
access : read-only
FCHID1 : Fault Protection Trigger on Channel 1
bits : 17 - 17 (1 bit)
access : read-only
FCHID2 : Fault Protection Trigger on Channel 2
bits : 18 - 18 (1 bit)
access : read-only
FCHID3 : Fault Protection Trigger on Channel 3
bits : 19 - 19 (1 bit)
access : read-only
PWM Channel Dead Time Update Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Sync Channels Mode Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC0 : Synchronous Channel 0
bits : 0 - 0 (1 bit)
SYNC1 : Synchronous Channel 1
bits : 1 - 1 (1 bit)
SYNC2 : Synchronous Channel 2
bits : 2 - 2 (1 bit)
SYNC3 : Synchronous Channel 3
bits : 3 - 3 (1 bit)
UPDM : Synchronous Channels Update Mode
bits : 16 - 17 (2 bit)
Enumeration: UPDMSelect
0x0 : MODE0
Manual write of double buffer registers and manual update of synchronous channels
0x1 : MODE1
Manual write of double buffer registers and automatic update of synchronous channels
0x2 : MODE2
Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels
End of enumeration elements list.
PTRM : DMA Controller Transfer Request Mode
bits : 20 - 20 (1 bit)
PTRCS : DMA Controller Transfer Request Comparison Selection
bits : 21 - 23 (3 bit)
PWM Sync Channels Mode Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC0 : Synchronous Channel 0
bits : 0 - 0 (1 bit)
SYNC1 : Synchronous Channel 1
bits : 1 - 1 (1 bit)
SYNC2 : Synchronous Channel 2
bits : 2 - 2 (1 bit)
SYNC3 : Synchronous Channel 3
bits : 3 - 3 (1 bit)
UPDM : Synchronous Channels Update Mode
bits : 16 - 17 (2 bit)
Enumeration: UPDMSelect
0x0 : MODE0
Manual write of double buffer registers and manual update of synchronous channels
0x1 : MODE1
Manual write of double buffer registers and automatic update of synchronous channels
0x2 : MODE2
Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels
End of enumeration elements list.
PTRM : DMA Controller Transfer Request Mode
bits : 20 - 20 (1 bit)
PTRCS : DMA Controller Transfer Request Comparison Selection
bits : 21 - 23 (3 bit)
PWM Sync Channels Mode Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC0 : Synchronous Channel 0
bits : 0 - 0 (1 bit)
access : read-write
SYNC1 : Synchronous Channel 1
bits : 1 - 1 (1 bit)
access : read-write
SYNC2 : Synchronous Channel 2
bits : 2 - 2 (1 bit)
access : read-write
SYNC3 : Synchronous Channel 3
bits : 3 - 3 (1 bit)
access : read-write
UPDM : Synchronous Channels Update Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration: UPDMSelect
0x0 : MODE0
Manual write of double buffer registers and manual update of synchronous channels
0x1 : MODE1
Manual write of double buffer registers and automatic update of synchronous channels
0x2 : MODE2
Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels
End of enumeration elements list.
PTRM : DMA Controller Transfer Request Mode
bits : 20 - 20 (1 bit)
access : read-write
PTRCS : DMA Controller Transfer Request Comparison Selection
bits : 21 - 23 (3 bit)
access : read-write
PWM Channel Mode Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
Enumeration: CPRESelect
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
Enumeration: CALGSelect
0x0 : LEFT_ALIGNED
Left aligned
0x1 : CENTER_ALIGNED
Center aligned
End of enumeration elements list.
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
Enumeration: CPOLSelect
0x0 : LOW_POLARITY
Waveform starts at low level
0x1 : HIGH_POLARITY
Waveform starts at high level
End of enumeration elements list.
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
Enumeration: CESSelect
0x0 : SINGLE_EVENT
At the end of PWM period
0x1 : DOUBLE_EVENT
At half of PWM period AND at the end of PWM period
End of enumeration elements list.
UPDS : Update Selection
bits : 11 - 11 (1 bit)
Enumeration: UPDSSelect
0x0 : UPDATE_AT_PERIOD
At the next end of PWM period
0x1 : UPDATE_AT_HALF_PERIOD
At the next end of Half PWM period
End of enumeration elements list.
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
PWM Channel Mode Register (ch_num = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
UPDS : Update Selection
bits : 11 - 11 (1 bit)
access : read-write
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
access : read-write
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
access : read-write
PWM Channel Duty Cycle Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
PWM Channel Duty Cycle Register (ch_num = 0)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
PWM Channel Duty Cycle Update Register (ch_num = 0)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
PWM Channel Period Register (ch_num = 0)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
PWM Channel Period Update Register (ch_num = 0)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
PWM Channel Counter Register (ch_num = 0)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Channel Dead Time Register (ch_num = 0)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Channel Dead Time Update Register (ch_num = 0)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Channel Mode Register (ch_num = 1)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
UPDS : Update Selection
bits : 11 - 11 (1 bit)
access : read-write
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
access : read-write
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 1)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 1)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 1)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 1)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 1)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 1)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 1)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM DMA Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DMADUTY : Duty-Cycle Holding Register for DMA Access
bits : 0 - 23 (24 bit)
PWM DMA Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DMADUTY : Duty-Cycle Holding Register for DMA Access
bits : 0 - 23 (24 bit)
PWM DMA Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DMADUTY : Duty-Cycle Holding Register for DMA Access
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Mode Register (ch_num = 2)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
UPDS : Update Selection
bits : 11 - 11 (1 bit)
access : read-write
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
access : read-write
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 2)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 2)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 2)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Period Update Register (ch_num = 2)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Counter Register (ch_num = 2)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Channel Dead Time Register (ch_num = 2)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Channel Dead Time Update Register (ch_num = 2)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Channel Mode Register (ch_num = 3)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
access : read-write
UPDS : Update Selection
bits : 11 - 11 (1 bit)
access : read-write
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
access : read-write
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
access : read-write
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
access : read-write
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
access : read-write
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
access : read-write
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 3)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
access : read-write
PWM Channel Duty Cycle Update Register (ch_num = 3)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Channel Period Register (ch_num = 3)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
access : read-write
PWM Comparison 0 Value Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Channel Period Update Register (ch_num = 3)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Comparison 0 Value Update Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Channel Counter Register (ch_num = 3)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
access : read-only
PWM Comparison 0 Mode Register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Channel Dead Time Register (ch_num = 3)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
access : read-write
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
access : read-write
PWM Comparison 0 Mode Update Register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Channel Dead Time Update Register (ch_num = 3)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
access : write-only
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
access : write-only
PWM Sync Channels Update Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDULOCK : Synchronous Channels Update Unlock
bits : 0 - 0 (1 bit)
PWM Sync Channels Update Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDULOCK : Synchronous Channels Update Unlock
bits : 0 - 0 (1 bit)
PWM Sync Channels Update Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPDULOCK : Synchronous Channels Update Unlock
bits : 0 - 0 (1 bit)
access : read-write
PWM Sync Channels Update Period Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPR : Update Period
bits : 0 - 3 (4 bit)
UPRCNT : Update Period Counter
bits : 4 - 7 (4 bit)
PWM Sync Channels Update Period Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPR : Update Period
bits : 0 - 3 (4 bit)
UPRCNT : Update Period Counter
bits : 4 - 7 (4 bit)
PWM Sync Channels Update Period Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPR : Update Period
bits : 0 - 3 (4 bit)
access : read-write
UPRCNT : Update Period Counter
bits : 4 - 7 (4 bit)
access : read-write
PWM Sync Channels Update Period Update Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPRUPD : Update Period Update
bits : 0 - 3 (4 bit)
PWM Sync Channels Update Period Update Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPRUPD : Update Period Update
bits : 0 - 3 (4 bit)
PWM Sync Channels Update Period Update Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
UPRUPD : Update Period Update
bits : 0 - 3 (4 bit)
access : write-only
PWM Interrupt Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Enable
bits : 0 - 0 (1 bit)
UNRE : Synchronous Channels Update Underrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
CMPM0 : Comparison 0 Match Interrupt Enable
bits : 8 - 8 (1 bit)
CMPM1 : Comparison 1 Match Interrupt Enable
bits : 9 - 9 (1 bit)
CMPM2 : Comparison 2 Match Interrupt Enable
bits : 10 - 10 (1 bit)
CMPM3 : Comparison 3 Match Interrupt Enable
bits : 11 - 11 (1 bit)
CMPM4 : Comparison 4 Match Interrupt Enable
bits : 12 - 12 (1 bit)
CMPM5 : Comparison 5 Match Interrupt Enable
bits : 13 - 13 (1 bit)
CMPM6 : Comparison 6 Match Interrupt Enable
bits : 14 - 14 (1 bit)
CMPM7 : Comparison 7 Match Interrupt Enable
bits : 15 - 15 (1 bit)
CMPU0 : Comparison 0 Update Interrupt Enable
bits : 16 - 16 (1 bit)
CMPU1 : Comparison 1 Update Interrupt Enable
bits : 17 - 17 (1 bit)
CMPU2 : Comparison 2 Update Interrupt Enable
bits : 18 - 18 (1 bit)
CMPU3 : Comparison 3 Update Interrupt Enable
bits : 19 - 19 (1 bit)
CMPU4 : Comparison 4 Update Interrupt Enable
bits : 20 - 20 (1 bit)
CMPU5 : Comparison 5 Update Interrupt Enable
bits : 21 - 21 (1 bit)
CMPU6 : Comparison 6 Update Interrupt Enable
bits : 22 - 22 (1 bit)
CMPU7 : Comparison 7 Update Interrupt Enable
bits : 23 - 23 (1 bit)
PWM Interrupt Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Enable
bits : 0 - 0 (1 bit)
UNRE : Synchronous Channels Update Underrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
CMPM0 : Comparison 0 Match Interrupt Enable
bits : 8 - 8 (1 bit)
CMPM1 : Comparison 1 Match Interrupt Enable
bits : 9 - 9 (1 bit)
CMPM2 : Comparison 2 Match Interrupt Enable
bits : 10 - 10 (1 bit)
CMPM3 : Comparison 3 Match Interrupt Enable
bits : 11 - 11 (1 bit)
CMPM4 : Comparison 4 Match Interrupt Enable
bits : 12 - 12 (1 bit)
CMPM5 : Comparison 5 Match Interrupt Enable
bits : 13 - 13 (1 bit)
CMPM6 : Comparison 6 Match Interrupt Enable
bits : 14 - 14 (1 bit)
CMPM7 : Comparison 7 Match Interrupt Enable
bits : 15 - 15 (1 bit)
CMPU0 : Comparison 0 Update Interrupt Enable
bits : 16 - 16 (1 bit)
CMPU1 : Comparison 1 Update Interrupt Enable
bits : 17 - 17 (1 bit)
CMPU2 : Comparison 2 Update Interrupt Enable
bits : 18 - 18 (1 bit)
CMPU3 : Comparison 3 Update Interrupt Enable
bits : 19 - 19 (1 bit)
CMPU4 : Comparison 4 Update Interrupt Enable
bits : 20 - 20 (1 bit)
CMPU5 : Comparison 5 Update Interrupt Enable
bits : 21 - 21 (1 bit)
CMPU6 : Comparison 6 Update Interrupt Enable
bits : 22 - 22 (1 bit)
CMPU7 : Comparison 7 Update Interrupt Enable
bits : 23 - 23 (1 bit)
PWM Interrupt Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
UNRE : Synchronous Channels Update Underrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
CMPM0 : Comparison 0 Match Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
CMPM1 : Comparison 1 Match Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
CMPM2 : Comparison 2 Match Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
CMPM3 : Comparison 3 Match Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
CMPM4 : Comparison 4 Match Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
CMPM5 : Comparison 5 Match Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
CMPM6 : Comparison 6 Match Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
CMPM7 : Comparison 7 Match Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
CMPU0 : Comparison 0 Update Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
CMPU1 : Comparison 1 Update Interrupt Enable
bits : 17 - 17 (1 bit)
access : write-only
CMPU2 : Comparison 2 Update Interrupt Enable
bits : 18 - 18 (1 bit)
access : write-only
CMPU3 : Comparison 3 Update Interrupt Enable
bits : 19 - 19 (1 bit)
access : write-only
CMPU4 : Comparison 4 Update Interrupt Enable
bits : 20 - 20 (1 bit)
access : write-only
CMPU5 : Comparison 5 Update Interrupt Enable
bits : 21 - 21 (1 bit)
access : write-only
CMPU6 : Comparison 6 Update Interrupt Enable
bits : 22 - 22 (1 bit)
access : write-only
CMPU7 : Comparison 7 Update Interrupt Enable
bits : 23 - 23 (1 bit)
access : write-only
PWM Interrupt Disable Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Disable
bits : 0 - 0 (1 bit)
UNRE : Synchronous Channels Update Underrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
CMPM0 : Comparison 0 Match Interrupt Disable
bits : 8 - 8 (1 bit)
CMPM1 : Comparison 1 Match Interrupt Disable
bits : 9 - 9 (1 bit)
CMPM2 : Comparison 2 Match Interrupt Disable
bits : 10 - 10 (1 bit)
CMPM3 : Comparison 3 Match Interrupt Disable
bits : 11 - 11 (1 bit)
CMPM4 : Comparison 4 Match Interrupt Disable
bits : 12 - 12 (1 bit)
CMPM5 : Comparison 5 Match Interrupt Disable
bits : 13 - 13 (1 bit)
CMPM6 : Comparison 6 Match Interrupt Disable
bits : 14 - 14 (1 bit)
CMPM7 : Comparison 7 Match Interrupt Disable
bits : 15 - 15 (1 bit)
CMPU0 : Comparison 0 Update Interrupt Disable
bits : 16 - 16 (1 bit)
CMPU1 : Comparison 1 Update Interrupt Disable
bits : 17 - 17 (1 bit)
CMPU2 : Comparison 2 Update Interrupt Disable
bits : 18 - 18 (1 bit)
CMPU3 : Comparison 3 Update Interrupt Disable
bits : 19 - 19 (1 bit)
CMPU4 : Comparison 4 Update Interrupt Disable
bits : 20 - 20 (1 bit)
CMPU5 : Comparison 5 Update Interrupt Disable
bits : 21 - 21 (1 bit)
CMPU6 : Comparison 6 Update Interrupt Disable
bits : 22 - 22 (1 bit)
CMPU7 : Comparison 7 Update Interrupt Disable
bits : 23 - 23 (1 bit)
PWM Interrupt Disable Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Disable
bits : 0 - 0 (1 bit)
UNRE : Synchronous Channels Update Underrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
CMPM0 : Comparison 0 Match Interrupt Disable
bits : 8 - 8 (1 bit)
CMPM1 : Comparison 1 Match Interrupt Disable
bits : 9 - 9 (1 bit)
CMPM2 : Comparison 2 Match Interrupt Disable
bits : 10 - 10 (1 bit)
CMPM3 : Comparison 3 Match Interrupt Disable
bits : 11 - 11 (1 bit)
CMPM4 : Comparison 4 Match Interrupt Disable
bits : 12 - 12 (1 bit)
CMPM5 : Comparison 5 Match Interrupt Disable
bits : 13 - 13 (1 bit)
CMPM6 : Comparison 6 Match Interrupt Disable
bits : 14 - 14 (1 bit)
CMPM7 : Comparison 7 Match Interrupt Disable
bits : 15 - 15 (1 bit)
CMPU0 : Comparison 0 Update Interrupt Disable
bits : 16 - 16 (1 bit)
CMPU1 : Comparison 1 Update Interrupt Disable
bits : 17 - 17 (1 bit)
CMPU2 : Comparison 2 Update Interrupt Disable
bits : 18 - 18 (1 bit)
CMPU3 : Comparison 3 Update Interrupt Disable
bits : 19 - 19 (1 bit)
CMPU4 : Comparison 4 Update Interrupt Disable
bits : 20 - 20 (1 bit)
CMPU5 : Comparison 5 Update Interrupt Disable
bits : 21 - 21 (1 bit)
CMPU6 : Comparison 6 Update Interrupt Disable
bits : 22 - 22 (1 bit)
CMPU7 : Comparison 7 Update Interrupt Disable
bits : 23 - 23 (1 bit)
PWM Interrupt Disable Register 2
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
UNRE : Synchronous Channels Update Underrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
CMPM0 : Comparison 0 Match Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
CMPM1 : Comparison 1 Match Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
CMPM2 : Comparison 2 Match Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
CMPM3 : Comparison 3 Match Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
CMPM4 : Comparison 4 Match Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
CMPM5 : Comparison 5 Match Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
CMPM6 : Comparison 6 Match Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
CMPM7 : Comparison 7 Match Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
CMPU0 : Comparison 0 Update Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
CMPU1 : Comparison 1 Update Interrupt Disable
bits : 17 - 17 (1 bit)
access : write-only
CMPU2 : Comparison 2 Update Interrupt Disable
bits : 18 - 18 (1 bit)
access : write-only
CMPU3 : Comparison 3 Update Interrupt Disable
bits : 19 - 19 (1 bit)
access : write-only
CMPU4 : Comparison 4 Update Interrupt Disable
bits : 20 - 20 (1 bit)
access : write-only
CMPU5 : Comparison 5 Update Interrupt Disable
bits : 21 - 21 (1 bit)
access : write-only
CMPU6 : Comparison 6 Update Interrupt Disable
bits : 22 - 22 (1 bit)
access : write-only
CMPU7 : Comparison 7 Update Interrupt Disable
bits : 23 - 23 (1 bit)
access : write-only
PWM Interrupt Mask Register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Mask
bits : 0 - 0 (1 bit)
UNRE : Synchronous Channels Update Underrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
CMPM0 : Comparison 0 Match Interrupt Mask
bits : 8 - 8 (1 bit)
CMPM1 : Comparison 1 Match Interrupt Mask
bits : 9 - 9 (1 bit)
CMPM2 : Comparison 2 Match Interrupt Mask
bits : 10 - 10 (1 bit)
CMPM3 : Comparison 3 Match Interrupt Mask
bits : 11 - 11 (1 bit)
CMPM4 : Comparison 4 Match Interrupt Mask
bits : 12 - 12 (1 bit)
CMPM5 : Comparison 5 Match Interrupt Mask
bits : 13 - 13 (1 bit)
CMPM6 : Comparison 6 Match Interrupt Mask
bits : 14 - 14 (1 bit)
CMPM7 : Comparison 7 Match Interrupt Mask
bits : 15 - 15 (1 bit)
CMPU0 : Comparison 0 Update Interrupt Mask
bits : 16 - 16 (1 bit)
CMPU1 : Comparison 1 Update Interrupt Mask
bits : 17 - 17 (1 bit)
CMPU2 : Comparison 2 Update Interrupt Mask
bits : 18 - 18 (1 bit)
CMPU3 : Comparison 3 Update Interrupt Mask
bits : 19 - 19 (1 bit)
CMPU4 : Comparison 4 Update Interrupt Mask
bits : 20 - 20 (1 bit)
CMPU5 : Comparison 5 Update Interrupt Mask
bits : 21 - 21 (1 bit)
CMPU6 : Comparison 6 Update Interrupt Mask
bits : 22 - 22 (1 bit)
CMPU7 : Comparison 7 Update Interrupt Mask
bits : 23 - 23 (1 bit)
PWM Interrupt Mask Register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Mask
bits : 0 - 0 (1 bit)
UNRE : Synchronous Channels Update Underrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
CMPM0 : Comparison 0 Match Interrupt Mask
bits : 8 - 8 (1 bit)
CMPM1 : Comparison 1 Match Interrupt Mask
bits : 9 - 9 (1 bit)
CMPM2 : Comparison 2 Match Interrupt Mask
bits : 10 - 10 (1 bit)
CMPM3 : Comparison 3 Match Interrupt Mask
bits : 11 - 11 (1 bit)
CMPM4 : Comparison 4 Match Interrupt Mask
bits : 12 - 12 (1 bit)
CMPM5 : Comparison 5 Match Interrupt Mask
bits : 13 - 13 (1 bit)
CMPM6 : Comparison 6 Match Interrupt Mask
bits : 14 - 14 (1 bit)
CMPM7 : Comparison 7 Match Interrupt Mask
bits : 15 - 15 (1 bit)
CMPU0 : Comparison 0 Update Interrupt Mask
bits : 16 - 16 (1 bit)
CMPU1 : Comparison 1 Update Interrupt Mask
bits : 17 - 17 (1 bit)
CMPU2 : Comparison 2 Update Interrupt Mask
bits : 18 - 18 (1 bit)
CMPU3 : Comparison 3 Update Interrupt Mask
bits : 19 - 19 (1 bit)
CMPU4 : Comparison 4 Update Interrupt Mask
bits : 20 - 20 (1 bit)
CMPU5 : Comparison 5 Update Interrupt Mask
bits : 21 - 21 (1 bit)
CMPU6 : Comparison 6 Update Interrupt Mask
bits : 22 - 22 (1 bit)
CMPU7 : Comparison 7 Update Interrupt Mask
bits : 23 - 23 (1 bit)
PWM Interrupt Mask Register 2
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
UNRE : Synchronous Channels Update Underrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
CMPM0 : Comparison 0 Match Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
CMPM1 : Comparison 1 Match Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
CMPM2 : Comparison 2 Match Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
CMPM3 : Comparison 3 Match Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
CMPM4 : Comparison 4 Match Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
CMPM5 : Comparison 5 Match Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
CMPM6 : Comparison 6 Match Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
CMPM7 : Comparison 7 Match Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
CMPU0 : Comparison 0 Update Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
CMPU1 : Comparison 1 Update Interrupt Mask
bits : 17 - 17 (1 bit)
access : read-only
CMPU2 : Comparison 2 Update Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-only
CMPU3 : Comparison 3 Update Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-only
CMPU4 : Comparison 4 Update Interrupt Mask
bits : 20 - 20 (1 bit)
access : read-only
CMPU5 : Comparison 5 Update Interrupt Mask
bits : 21 - 21 (1 bit)
access : read-only
CMPU6 : Comparison 6 Update Interrupt Mask
bits : 22 - 22 (1 bit)
access : read-only
CMPU7 : Comparison 7 Update Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-only
PWM Comparison 0 Value Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Comparison 0 Value Update Register
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Comparison 0 Mode Register
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Comparison 0 Mode Update Register
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
PWM Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
PWM Comparison 0 Value Update Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Channel Duty Cycle Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
PWM Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only
PWM Comparison 0 Value Update Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Channel Duty Cycle Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
PWM Interrupt Status Register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update
bits : 0 - 0 (1 bit)
UNRE : Synchronous Channels Update Underrun Error
bits : 3 - 3 (1 bit)
CMPM0 : Comparison 0 Match
bits : 8 - 8 (1 bit)
CMPM1 : Comparison 1 Match
bits : 9 - 9 (1 bit)
CMPM2 : Comparison 2 Match
bits : 10 - 10 (1 bit)
CMPM3 : Comparison 3 Match
bits : 11 - 11 (1 bit)
CMPM4 : Comparison 4 Match
bits : 12 - 12 (1 bit)
CMPM5 : Comparison 5 Match
bits : 13 - 13 (1 bit)
CMPM6 : Comparison 6 Match
bits : 14 - 14 (1 bit)
CMPM7 : Comparison 7 Match
bits : 15 - 15 (1 bit)
CMPU0 : Comparison 0 Update
bits : 16 - 16 (1 bit)
CMPU1 : Comparison 1 Update
bits : 17 - 17 (1 bit)
CMPU2 : Comparison 2 Update
bits : 18 - 18 (1 bit)
CMPU3 : Comparison 3 Update
bits : 19 - 19 (1 bit)
CMPU4 : Comparison 4 Update
bits : 20 - 20 (1 bit)
CMPU5 : Comparison 5 Update
bits : 21 - 21 (1 bit)
CMPU6 : Comparison 6 Update
bits : 22 - 22 (1 bit)
CMPU7 : Comparison 7 Update
bits : 23 - 23 (1 bit)
PWM Interrupt Status Register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update
bits : 0 - 0 (1 bit)
UNRE : Synchronous Channels Update Underrun Error
bits : 3 - 3 (1 bit)
CMPM0 : Comparison 0 Match
bits : 8 - 8 (1 bit)
CMPM1 : Comparison 1 Match
bits : 9 - 9 (1 bit)
CMPM2 : Comparison 2 Match
bits : 10 - 10 (1 bit)
CMPM3 : Comparison 3 Match
bits : 11 - 11 (1 bit)
CMPM4 : Comparison 4 Match
bits : 12 - 12 (1 bit)
CMPM5 : Comparison 5 Match
bits : 13 - 13 (1 bit)
CMPM6 : Comparison 6 Match
bits : 14 - 14 (1 bit)
CMPM7 : Comparison 7 Match
bits : 15 - 15 (1 bit)
CMPU0 : Comparison 0 Update
bits : 16 - 16 (1 bit)
CMPU1 : Comparison 1 Update
bits : 17 - 17 (1 bit)
CMPU2 : Comparison 2 Update
bits : 18 - 18 (1 bit)
CMPU3 : Comparison 3 Update
bits : 19 - 19 (1 bit)
CMPU4 : Comparison 4 Update
bits : 20 - 20 (1 bit)
CMPU5 : Comparison 5 Update
bits : 21 - 21 (1 bit)
CMPU6 : Comparison 6 Update
bits : 22 - 22 (1 bit)
CMPU7 : Comparison 7 Update
bits : 23 - 23 (1 bit)
PWM Interrupt Status Register 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WRDY : Write Ready for Synchronous Channels Update
bits : 0 - 0 (1 bit)
access : read-only
UNRE : Synchronous Channels Update Underrun Error
bits : 3 - 3 (1 bit)
access : read-only
CMPM0 : Comparison 0 Match
bits : 8 - 8 (1 bit)
access : read-only
CMPM1 : Comparison 1 Match
bits : 9 - 9 (1 bit)
access : read-only
CMPM2 : Comparison 2 Match
bits : 10 - 10 (1 bit)
access : read-only
CMPM3 : Comparison 3 Match
bits : 11 - 11 (1 bit)
access : read-only
CMPM4 : Comparison 4 Match
bits : 12 - 12 (1 bit)
access : read-only
CMPM5 : Comparison 5 Match
bits : 13 - 13 (1 bit)
access : read-only
CMPM6 : Comparison 6 Match
bits : 14 - 14 (1 bit)
access : read-only
CMPM7 : Comparison 7 Match
bits : 15 - 15 (1 bit)
access : read-only
CMPU0 : Comparison 0 Update
bits : 16 - 16 (1 bit)
access : read-only
CMPU1 : Comparison 1 Update
bits : 17 - 17 (1 bit)
access : read-only
CMPU2 : Comparison 2 Update
bits : 18 - 18 (1 bit)
access : read-only
CMPU3 : Comparison 3 Update
bits : 19 - 19 (1 bit)
access : read-only
CMPU4 : Comparison 4 Update
bits : 20 - 20 (1 bit)
access : read-only
CMPU5 : Comparison 5 Update
bits : 21 - 21 (1 bit)
access : read-only
CMPU6 : Comparison 6 Update
bits : 22 - 22 (1 bit)
access : read-only
CMPU7 : Comparison 7 Update
bits : 23 - 23 (1 bit)
access : read-only
PWM Channel Mode Update Register (ch_num = 0)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
PWM Channel Mode Update Register (ch_num = 0)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
PWM Channel Mode Update Register (ch_num = 0)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
access : write-only
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
access : write-only
PWM Channel Mode Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
Enumeration: CPRESelect
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
Enumeration: CALGSelect
0x0 : LEFT_ALIGNED
Left aligned
0x1 : CENTER_ALIGNED
Center aligned
End of enumeration elements list.
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
Enumeration: CPOLSelect
0x0 : LOW_POLARITY
Waveform starts at low level
0x1 : HIGH_POLARITY
Waveform starts at high level
End of enumeration elements list.
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
Enumeration: CESSelect
0x0 : SINGLE_EVENT
At the end of PWM period
0x1 : DOUBLE_EVENT
At half of PWM period AND at the end of PWM period
End of enumeration elements list.
UPDS : Update Selection
bits : 11 - 11 (1 bit)
Enumeration: UPDSSelect
0x0 : UPDATE_AT_PERIOD
At the next end of PWM period
0x1 : UPDATE_AT_HALF_PERIOD
At the next end of Half PWM period
End of enumeration elements list.
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
PWM Channel Mode Update Register (ch_num = 1)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
PWM Channel Mode Update Register (ch_num = 1)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
PWM Channel Mode Update Register (ch_num = 1)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
access : write-only
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
access : write-only
PWM Channel Duty Cycle Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
PWM Channel Duty Cycle Update Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
PWM Channel Period Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
PWM External Trigger Register (trg_num = 1)
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Maximum Counter value
bits : 0 - 23 (24 bit)
TRGMODE : External Trigger Mode
bits : 24 - 25 (2 bit)
Enumeration: TRGMODESelect
0x0 : OFF
External trigger is not enabled.
0x1 : MODE1
External PWM Reset Mode
0x2 : MODE2
External PWM Start Mode
0x3 : MODE3
Cycle-by-cycle Duty Mode
End of enumeration elements list.
TRGEDGE : Edge Selection
bits : 28 - 28 (1 bit)
Enumeration: TRGEDGESelect
0 : FALLING_ZERO
TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
1 : RISING_ONE
TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
End of enumeration elements list.
TRGFILT : Filtered input
bits : 29 - 29 (1 bit)
TRGSRC : Trigger Source
bits : 30 - 30 (1 bit)
RFEN : Recoverable Fault Enable
bits : 31 - 31 (1 bit)
PWM External Trigger Register (trg_num = 1)
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Maximum Counter value
bits : 0 - 23 (24 bit)
TRGMODE : External Trigger Mode
bits : 24 - 25 (2 bit)
Enumeration: TRGMODESelect
0x0 : OFF
External trigger is not enabled.
0x1 : MODE1
External PWM Reset Mode
0x2 : MODE2
External PWM Start Mode
0x3 : MODE3
Cycle-by-cycle Duty Mode
End of enumeration elements list.
TRGEDGE : Edge Selection
bits : 28 - 28 (1 bit)
Enumeration: TRGEDGESelect
0 : FALLING_ZERO
TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
1 : RISING_ONE
TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
End of enumeration elements list.
TRGFILT : Filtered input
bits : 29 - 29 (1 bit)
TRGSRC : Trigger Source
bits : 30 - 30 (1 bit)
RFEN : Recoverable Fault Enable
bits : 31 - 31 (1 bit)
PWM External Trigger Register (trg_num = 1)
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Maximum Counter value
bits : 0 - 23 (24 bit)
access : read-write
TRGMODE : External Trigger Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration: TRGMODESelect
0x0 : OFF
External trigger is not enabled.
0x1 : MODE1
External PWM Reset Mode
0x2 : MODE2
External PWM Start Mode
0x3 : MODE3
Cycle-by-cycle Duty Mode
End of enumeration elements list.
TRGEDGE : Edge Selection
bits : 28 - 28 (1 bit)
access : read-write
Enumeration: TRGEDGESelect
0 : FALLING_ZERO
TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
1 : RISING_ONE
TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
End of enumeration elements list.
TRGFILT : Filtered input
bits : 29 - 29 (1 bit)
access : read-write
TRGSRC : Trigger Source
bits : 30 - 30 (1 bit)
access : read-write
RFEN : Recoverable Fault Enable
bits : 31 - 31 (1 bit)
access : read-write
PWM Channel Period Update Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
PWM Leading-Edge Blanking Register (trg_num = 1)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBDELAY : Leading-Edge Blanking Delay for TRGINx
bits : 0 - 6 (7 bit)
PWMLFEN : PWML Falling Edge Enable
bits : 16 - 16 (1 bit)
PWMLREN : PWML Rising Edge Enable
bits : 17 - 17 (1 bit)
PWMHFEN : PWMH Falling Edge Enable
bits : 18 - 18 (1 bit)
PWMHREN : PWMH Rising Edge Enable
bits : 19 - 19 (1 bit)
PWM Leading-Edge Blanking Register (trg_num = 1)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBDELAY : Leading-Edge Blanking Delay for TRGINx
bits : 0 - 6 (7 bit)
PWMLFEN : PWML Falling Edge Enable
bits : 16 - 16 (1 bit)
PWMLREN : PWML Rising Edge Enable
bits : 17 - 17 (1 bit)
PWMHFEN : PWMH Falling Edge Enable
bits : 18 - 18 (1 bit)
PWMHREN : PWMH Rising Edge Enable
bits : 19 - 19 (1 bit)
PWM Leading-Edge Blanking Register (trg_num = 1)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBDELAY : Leading-Edge Blanking Delay for TRGINx
bits : 0 - 6 (7 bit)
access : read-write
PWMLFEN : PWML Falling Edge Enable
bits : 16 - 16 (1 bit)
access : read-write
PWMLREN : PWML Rising Edge Enable
bits : 17 - 17 (1 bit)
access : read-write
PWMHFEN : PWMH Falling Edge Enable
bits : 18 - 18 (1 bit)
access : read-write
PWMHREN : PWMH Rising Edge Enable
bits : 19 - 19 (1 bit)
access : read-write
PWM Channel Counter Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
PWM Channel Dead Time Register
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Channel Dead Time Update Register
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Output Override Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OOVH0 : Output Override Value for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OOVH1 : Output Override Value for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OOVH2 : Output Override Value for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OOVH3 : Output Override Value for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OOVL0 : Output Override Value for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OOVL1 : Output Override Value for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OOVL2 : Output Override Value for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OOVL3 : Output Override Value for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Override Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OOVH0 : Output Override Value for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OOVH1 : Output Override Value for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OOVH2 : Output Override Value for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OOVH3 : Output Override Value for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OOVL0 : Output Override Value for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OOVL1 : Output Override Value for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OOVL2 : Output Override Value for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OOVL3 : Output Override Value for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Override Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OOVH0 : Output Override Value for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : read-write
OOVH1 : Output Override Value for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : read-write
OOVH2 : Output Override Value for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : read-write
OOVH3 : Output Override Value for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : read-write
OOVL0 : Output Override Value for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : read-write
OOVL1 : Output Override Value for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : read-write
OOVL2 : Output Override Value for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : read-write
OOVL3 : Output Override Value for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : read-write
PWM Channel Mode Update Register (ch_num = 2)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
PWM Channel Mode Update Register (ch_num = 2)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
PWM Channel Mode Update Register (ch_num = 2)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
access : write-only
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
access : write-only
PWM External Trigger Register (trg_num = 2)
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Maximum Counter value
bits : 0 - 23 (24 bit)
TRGMODE : External Trigger Mode
bits : 24 - 25 (2 bit)
Enumeration: TRGMODESelect
0x0 : OFF
External trigger is not enabled.
0x1 : MODE1
External PWM Reset Mode
0x2 : MODE2
External PWM Start Mode
0x3 : MODE3
Cycle-by-cycle Duty Mode
End of enumeration elements list.
TRGEDGE : Edge Selection
bits : 28 - 28 (1 bit)
Enumeration: TRGEDGESelect
0 : FALLING_ZERO
TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
1 : RISING_ONE
TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
End of enumeration elements list.
TRGFILT : Filtered input
bits : 29 - 29 (1 bit)
TRGSRC : Trigger Source
bits : 30 - 30 (1 bit)
RFEN : Recoverable Fault Enable
bits : 31 - 31 (1 bit)
PWM External Trigger Register (trg_num = 2)
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Maximum Counter value
bits : 0 - 23 (24 bit)
TRGMODE : External Trigger Mode
bits : 24 - 25 (2 bit)
Enumeration: TRGMODESelect
0x0 : OFF
External trigger is not enabled.
0x1 : MODE1
External PWM Reset Mode
0x2 : MODE2
External PWM Start Mode
0x3 : MODE3
Cycle-by-cycle Duty Mode
End of enumeration elements list.
TRGEDGE : Edge Selection
bits : 28 - 28 (1 bit)
Enumeration: TRGEDGESelect
0 : FALLING_ZERO
TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
1 : RISING_ONE
TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
End of enumeration elements list.
TRGFILT : Filtered input
bits : 29 - 29 (1 bit)
TRGSRC : Trigger Source
bits : 30 - 30 (1 bit)
RFEN : Recoverable Fault Enable
bits : 31 - 31 (1 bit)
PWM External Trigger Register (trg_num = 2)
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXCNT : Maximum Counter value
bits : 0 - 23 (24 bit)
access : read-write
TRGMODE : External Trigger Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration: TRGMODESelect
0x0 : OFF
External trigger is not enabled.
0x1 : MODE1
External PWM Reset Mode
0x2 : MODE2
External PWM Start Mode
0x3 : MODE3
Cycle-by-cycle Duty Mode
End of enumeration elements list.
TRGEDGE : Edge Selection
bits : 28 - 28 (1 bit)
access : read-write
Enumeration: TRGEDGESelect
0 : FALLING_ZERO
TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0
1 : RISING_ONE
TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1
End of enumeration elements list.
TRGFILT : Filtered input
bits : 29 - 29 (1 bit)
access : read-write
TRGSRC : Trigger Source
bits : 30 - 30 (1 bit)
access : read-write
RFEN : Recoverable Fault Enable
bits : 31 - 31 (1 bit)
access : read-write
PWM Leading-Edge Blanking Register (trg_num = 2)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBDELAY : Leading-Edge Blanking Delay for TRGINx
bits : 0 - 6 (7 bit)
PWMLFEN : PWML Falling Edge Enable
bits : 16 - 16 (1 bit)
PWMLREN : PWML Rising Edge Enable
bits : 17 - 17 (1 bit)
PWMHFEN : PWMH Falling Edge Enable
bits : 18 - 18 (1 bit)
PWMHREN : PWMH Rising Edge Enable
bits : 19 - 19 (1 bit)
PWM Leading-Edge Blanking Register (trg_num = 2)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBDELAY : Leading-Edge Blanking Delay for TRGINx
bits : 0 - 6 (7 bit)
PWMLFEN : PWML Falling Edge Enable
bits : 16 - 16 (1 bit)
PWMLREN : PWML Rising Edge Enable
bits : 17 - 17 (1 bit)
PWMHFEN : PWMH Falling Edge Enable
bits : 18 - 18 (1 bit)
PWMHREN : PWMH Rising Edge Enable
bits : 19 - 19 (1 bit)
PWM Leading-Edge Blanking Register (trg_num = 2)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBDELAY : Leading-Edge Blanking Delay for TRGINx
bits : 0 - 6 (7 bit)
access : read-write
PWMLFEN : PWML Falling Edge Enable
bits : 16 - 16 (1 bit)
access : read-write
PWMLREN : PWML Rising Edge Enable
bits : 17 - 17 (1 bit)
access : read-write
PWMHFEN : PWMH Falling Edge Enable
bits : 18 - 18 (1 bit)
access : read-write
PWMHREN : PWMH Rising Edge Enable
bits : 19 - 19 (1 bit)
access : read-write
PWM Channel Mode Update Register (ch_num = 3)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
PWM Channel Mode Update Register (ch_num = 3)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
PWM Channel Mode Update Register (ch_num = 3)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPOLUP : Channel Polarity Update
bits : 9 - 9 (1 bit)
access : write-only
CPOLINVUP : Channel Polarity Inversion Update
bits : 13 - 13 (1 bit)
access : write-only
PWM Output Selection Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSH0 : Output Selection for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSH1 : Output Selection for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSH2 : Output Selection for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSH3 : Output Selection for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSL0 : Output Selection for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSL1 : Output Selection for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSL2 : Output Selection for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSL3 : Output Selection for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSH0 : Output Selection for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSH1 : Output Selection for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSH2 : Output Selection for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSH3 : Output Selection for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSL0 : Output Selection for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSL1 : Output Selection for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSL2 : Output Selection for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSL3 : Output Selection for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSH0 : Output Selection for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : read-write
OSH1 : Output Selection for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : read-write
OSH2 : Output Selection for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : read-write
OSH3 : Output Selection for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : read-write
OSL0 : Output Selection for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : read-write
OSL1 : Output Selection for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : read-write
OSL2 : Output Selection for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : read-write
OSL3 : Output Selection for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : read-write
PWM Output Selection Set Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSSH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSSH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSSH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSSH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSSL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSSL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSSL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSSL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Set Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSSH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSSH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSSH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSSH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSSL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSSL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSSL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSSL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Set Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSSH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only
OSSH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only
OSSH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only
OSSH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only
OSSL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only
OSSL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only
OSSL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only
OSSL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only
PWM Output Selection Clear Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSCH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSCH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSCH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSCH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSCL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSCL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSCL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSCL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Clear Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSCH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSCH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSCH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSCH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSCL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSCL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSCL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSCL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Clear Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSCH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only
OSCH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only
OSCH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only
OSCH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only
OSCL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only
OSCL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only
OSCL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only
OSCL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only
PWM Comparison 0 Value Register
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Comparison 0 Value Update Register
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Comparison 0 Mode Register
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Comparison 0 Mode Update Register
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Output Selection Set Update Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSSUPH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSSUPH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSSUPH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSSUPH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSSUPL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSSUPL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSSUPL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSSUPL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Set Update Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSSUPH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSSUPH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSSUPH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSSUPH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSSUPL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSSUPL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSSUPL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSSUPL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Set Update Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSSUPH0 : Output Selection Set for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only
OSSUPH1 : Output Selection Set for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only
OSSUPH2 : Output Selection Set for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only
OSSUPH3 : Output Selection Set for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only
OSSUPL0 : Output Selection Set for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only
OSSUPL1 : Output Selection Set for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only
OSSUPL2 : Output Selection Set for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only
OSSUPL3 : Output Selection Set for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only
PWM Output Selection Clear Update Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSCUPH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSCUPH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSCUPH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSCUPH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSCUPL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSCUPL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSCUPL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSCUPL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Clear Update Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSCUPH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
OSCUPH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
OSCUPH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
OSCUPH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
OSCUPL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
OSCUPL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
OSCUPL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
OSCUPL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
PWM Output Selection Clear Update Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OSCUPH0 : Output Selection Clear for PWMH output of the channel 0
bits : 0 - 0 (1 bit)
access : write-only
OSCUPH1 : Output Selection Clear for PWMH output of the channel 1
bits : 1 - 1 (1 bit)
access : write-only
OSCUPH2 : Output Selection Clear for PWMH output of the channel 2
bits : 2 - 2 (1 bit)
access : write-only
OSCUPH3 : Output Selection Clear for PWMH output of the channel 3
bits : 3 - 3 (1 bit)
access : write-only
OSCUPL0 : Output Selection Clear for PWML output of the channel 0
bits : 16 - 16 (1 bit)
access : write-only
OSCUPL1 : Output Selection Clear for PWML output of the channel 1
bits : 17 - 17 (1 bit)
access : write-only
OSCUPL2 : Output Selection Clear for PWML output of the channel 2
bits : 18 - 18 (1 bit)
access : write-only
OSCUPL3 : Output Selection Clear for PWML output of the channel 3
bits : 19 - 19 (1 bit)
access : write-only
PWM Fault Mode Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPOL : Fault Polarity
bits : 0 - 7 (8 bit)
FMOD : Fault Activation Mode
bits : 8 - 15 (8 bit)
FFIL : Fault Filtering
bits : 16 - 23 (8 bit)
PWM Fault Mode Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPOL : Fault Polarity
bits : 0 - 7 (8 bit)
FMOD : Fault Activation Mode
bits : 8 - 15 (8 bit)
FFIL : Fault Filtering
bits : 16 - 23 (8 bit)
PWM Fault Mode Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPOL : Fault Polarity
bits : 0 - 7 (8 bit)
access : read-write
FMOD : Fault Activation Mode
bits : 8 - 15 (8 bit)
access : read-write
FFIL : Fault Filtering
bits : 16 - 23 (8 bit)
access : read-write
PWM Fault Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIV : Fault Input Value
bits : 0 - 7 (8 bit)
FS : Fault Status
bits : 8 - 15 (8 bit)
PWM Fault Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIV : Fault Input Value
bits : 0 - 7 (8 bit)
FS : Fault Status
bits : 8 - 15 (8 bit)
PWM Fault Status Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIV : Fault Input Value
bits : 0 - 7 (8 bit)
access : read-only
FS : Fault Status
bits : 8 - 15 (8 bit)
access : read-only
PWM Fault Clear Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FCLR : Fault Clear
bits : 0 - 7 (8 bit)
PWM Fault Clear Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FCLR : Fault Clear
bits : 0 - 7 (8 bit)
PWM Fault Clear Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FCLR : Fault Clear
bits : 0 - 7 (8 bit)
access : write-only
PWM Channel Mode Register
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
Enumeration: CPRESelect
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
Enumeration: CALGSelect
0x0 : LEFT_ALIGNED
Left aligned
0x1 : CENTER_ALIGNED
Center aligned
End of enumeration elements list.
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
Enumeration: CPOLSelect
0x0 : LOW_POLARITY
Waveform starts at low level
0x1 : HIGH_POLARITY
Waveform starts at high level
End of enumeration elements list.
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
Enumeration: CESSelect
0x0 : SINGLE_EVENT
At the end of PWM period
0x1 : DOUBLE_EVENT
At half of PWM period AND at the end of PWM period
End of enumeration elements list.
UPDS : Update Selection
bits : 11 - 11 (1 bit)
Enumeration: UPDSSelect
0x0 : UPDATE_AT_PERIOD
At the next end of PWM period
0x1 : UPDATE_AT_HALF_PERIOD
At the next end of Half PWM period
End of enumeration elements list.
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
PWM Channel Duty Cycle Register
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
PWM Channel Duty Cycle Update Register
address_offset : 0x668 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
PWM Channel Period Register
address_offset : 0x66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
PWM Channel Period Update Register
address_offset : 0x670 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
PWM Channel Counter Register
address_offset : 0x674 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
PWM Channel Dead Time Register
address_offset : 0x678 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Channel Dead Time Update Register
address_offset : 0x67C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Fault Protection Value Register 1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPVH0 : Fault Protection Value for PWMH output on channel 0
bits : 0 - 0 (1 bit)
FPVH1 : Fault Protection Value for PWMH output on channel 1
bits : 1 - 1 (1 bit)
FPVH2 : Fault Protection Value for PWMH output on channel 2
bits : 2 - 2 (1 bit)
FPVH3 : Fault Protection Value for PWMH output on channel 3
bits : 3 - 3 (1 bit)
FPVL0 : Fault Protection Value for PWML output on channel 0
bits : 16 - 16 (1 bit)
FPVL1 : Fault Protection Value for PWML output on channel 1
bits : 17 - 17 (1 bit)
FPVL2 : Fault Protection Value for PWML output on channel 2
bits : 18 - 18 (1 bit)
FPVL3 : Fault Protection Value for PWML output on channel 3
bits : 19 - 19 (1 bit)
PWM Fault Protection Value Register 1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPVH0 : Fault Protection Value for PWMH output on channel 0
bits : 0 - 0 (1 bit)
FPVH1 : Fault Protection Value for PWMH output on channel 1
bits : 1 - 1 (1 bit)
FPVH2 : Fault Protection Value for PWMH output on channel 2
bits : 2 - 2 (1 bit)
FPVH3 : Fault Protection Value for PWMH output on channel 3
bits : 3 - 3 (1 bit)
FPVL0 : Fault Protection Value for PWML output on channel 0
bits : 16 - 16 (1 bit)
FPVL1 : Fault Protection Value for PWML output on channel 1
bits : 17 - 17 (1 bit)
FPVL2 : Fault Protection Value for PWML output on channel 2
bits : 18 - 18 (1 bit)
FPVL3 : Fault Protection Value for PWML output on channel 3
bits : 19 - 19 (1 bit)
PWM Fault Protection Value Register 1
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPVH0 : Fault Protection Value for PWMH output on channel 0
bits : 0 - 0 (1 bit)
access : read-write
FPVH1 : Fault Protection Value for PWMH output on channel 1
bits : 1 - 1 (1 bit)
access : read-write
FPVH2 : Fault Protection Value for PWMH output on channel 2
bits : 2 - 2 (1 bit)
access : read-write
FPVH3 : Fault Protection Value for PWMH output on channel 3
bits : 3 - 3 (1 bit)
access : read-write
FPVL0 : Fault Protection Value for PWML output on channel 0
bits : 16 - 16 (1 bit)
access : read-write
FPVL1 : Fault Protection Value for PWML output on channel 1
bits : 17 - 17 (1 bit)
access : read-write
FPVL2 : Fault Protection Value for PWML output on channel 2
bits : 18 - 18 (1 bit)
access : read-write
FPVL3 : Fault Protection Value for PWML output on channel 3
bits : 19 - 19 (1 bit)
access : read-write
PWM Comparison 0 Value Register
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Comparison 0 Value Update Register
address_offset : 0x694 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Comparison 0 Mode Register
address_offset : 0x698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Comparison 0 Mode Update Register
address_offset : 0x69C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Fault Protection Enable Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPE0 : Fault Protection Enable for channel 0
bits : 0 - 7 (8 bit)
FPE1 : Fault Protection Enable for channel 1
bits : 8 - 15 (8 bit)
FPE2 : Fault Protection Enable for channel 2
bits : 16 - 23 (8 bit)
FPE3 : Fault Protection Enable for channel 3
bits : 24 - 31 (8 bit)
PWM Fault Protection Enable Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPE0 : Fault Protection Enable for channel 0
bits : 0 - 7 (8 bit)
FPE1 : Fault Protection Enable for channel 1
bits : 8 - 15 (8 bit)
FPE2 : Fault Protection Enable for channel 2
bits : 16 - 23 (8 bit)
FPE3 : Fault Protection Enable for channel 3
bits : 24 - 31 (8 bit)
PWM Fault Protection Enable Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPE0 : Fault Protection Enable for channel 0
bits : 0 - 7 (8 bit)
access : read-write
FPE1 : Fault Protection Enable for channel 1
bits : 8 - 15 (8 bit)
access : read-write
FPE2 : Fault Protection Enable for channel 2
bits : 16 - 23 (8 bit)
access : read-write
FPE3 : Fault Protection Enable for channel 3
bits : 24 - 31 (8 bit)
access : read-write
PWM Event Line 0 Mode Register 0
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
PWM Event Line 0 Mode Register 0
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write
PWM Disable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
PWM Disable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
PWM Comparison 0 Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Channel Duty Cycle Update Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
PWM Disable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only
PWM Comparison 0 Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Channel Duty Cycle Update Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
PWM Event Line 0 Mode Register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
PWM Event Line 0 Mode Register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
access : read-write
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
access : read-write
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
access : read-write
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
access : read-write
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
access : read-write
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
access : read-write
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
access : read-write
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
access : read-write
PWM Comparison 0 Value Register
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Comparison 0 Value Update Register
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Comparison 0 Mode Register
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Comparison 0 Mode Update Register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Channel Mode Register
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
Enumeration: CPRESelect
0x0 : MCK
Peripheral clock
0x1 : MCK_DIV_2
Peripheral clock/2
0x2 : MCK_DIV_4
Peripheral clock/4
0x3 : MCK_DIV_8
Peripheral clock/8
0x4 : MCK_DIV_16
Peripheral clock/16
0x5 : MCK_DIV_32
Peripheral clock/32
0x6 : MCK_DIV_64
Peripheral clock/64
0x7 : MCK_DIV_128
Peripheral clock/128
0x8 : MCK_DIV_256
Peripheral clock/256
0x9 : MCK_DIV_512
Peripheral clock/512
0xA : MCK_DIV_1024
Peripheral clock/1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
Enumeration: CALGSelect
0x0 : LEFT_ALIGNED
Left aligned
0x1 : CENTER_ALIGNED
Center aligned
End of enumeration elements list.
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
Enumeration: CPOLSelect
0x0 : LOW_POLARITY
Waveform starts at low level
0x1 : HIGH_POLARITY
Waveform starts at high level
End of enumeration elements list.
CES : Counter Event Selection
bits : 10 - 10 (1 bit)
Enumeration: CESSelect
0x0 : SINGLE_EVENT
At the end of PWM period
0x1 : DOUBLE_EVENT
At half of PWM period AND at the end of PWM period
End of enumeration elements list.
UPDS : Update Selection
bits : 11 - 11 (1 bit)
Enumeration: UPDSSelect
0x0 : UPDATE_AT_PERIOD
At the next end of PWM period
0x1 : UPDATE_AT_HALF_PERIOD
At the next end of Half PWM period
End of enumeration elements list.
DPOLI : Disabled Polarity Inverted
bits : 12 - 12 (1 bit)
TCTS : Timer Counter Trigger Selection
bits : 13 - 13 (1 bit)
DTE : Dead-Time Generator Enable
bits : 16 - 16 (1 bit)
DTHI : Dead-Time PWMHx Output Inverted
bits : 17 - 17 (1 bit)
DTLI : Dead-Time PWMLx Output Inverted
bits : 18 - 18 (1 bit)
PPM : Push-Pull Mode
bits : 19 - 19 (1 bit)
PWM Channel Duty Cycle Register
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty-Cycle
bits : 0 - 23 (24 bit)
PWM Channel Duty Cycle Update Register
address_offset : 0x8C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CDTYUPD : Channel Duty-Cycle Update
bits : 0 - 23 (24 bit)
PWM Channel Period Register
address_offset : 0x8CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
PWM Channel Period Update Register
address_offset : 0x8D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CPRDUPD : Channel Period Update
bits : 0 - 23 (24 bit)
PWM Channel Counter Register
address_offset : 0x8D4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 23 (24 bit)
PWM Channel Dead Time Register
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTH : Dead-Time Value for PWMHx Output
bits : 0 - 15 (16 bit)
DTL : Dead-Time Value for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Channel Dead Time Update Register
address_offset : 0x8DC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DTHUPD : Dead-Time Value Update for PWMHx Output
bits : 0 - 15 (16 bit)
DTLUPD : Dead-Time Value Update for PWMLx Output
bits : 16 - 31 (16 bit)
PWM Comparison 0 Value Register
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Comparison 0 Value Update Register
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Comparison 0 Mode Register
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Comparison 0 Mode Update Register
address_offset : 0x9AC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Spread Spectrum Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRD : Spread Spectrum Limit Value
bits : 0 - 23 (24 bit)
SPRDM : Spread Spectrum Counter Mode
bits : 24 - 24 (1 bit)
PWM Spread Spectrum Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRD : Spread Spectrum Limit Value
bits : 0 - 23 (24 bit)
SPRDM : Spread Spectrum Counter Mode
bits : 24 - 24 (1 bit)
PWM Spread Spectrum Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRD : Spread Spectrum Limit Value
bits : 0 - 23 (24 bit)
access : read-write
SPRDM : Spread Spectrum Counter Mode
bits : 24 - 24 (1 bit)
access : read-write
PWM Spread Spectrum Update Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SPRDUP : Spread Spectrum Limit Value Update
bits : 0 - 23 (24 bit)
PWM Spread Spectrum Update Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SPRDUP : Spread Spectrum Limit Value Update
bits : 0 - 23 (24 bit)
PWM Spread Spectrum Update Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SPRDUP : Spread Spectrum Limit Value Update
bits : 0 - 23 (24 bit)
access : write-only
PWM Stepper Motor Mode Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN0 : Gray Count ENable
bits : 0 - 0 (1 bit)
GCEN1 : Gray Count ENable
bits : 1 - 1 (1 bit)
DOWN0 : DOWN Count
bits : 16 - 16 (1 bit)
DOWN1 : DOWN Count
bits : 17 - 17 (1 bit)
PWM Stepper Motor Mode Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN0 : Gray Count ENable
bits : 0 - 0 (1 bit)
GCEN1 : Gray Count ENable
bits : 1 - 1 (1 bit)
DOWN0 : DOWN Count
bits : 16 - 16 (1 bit)
DOWN1 : DOWN Count
bits : 17 - 17 (1 bit)
PWM Stepper Motor Mode Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN0 : Gray Count ENable
bits : 0 - 0 (1 bit)
access : read-write
GCEN1 : Gray Count ENable
bits : 1 - 1 (1 bit)
access : read-write
DOWN0 : DOWN Count
bits : 16 - 16 (1 bit)
access : read-write
DOWN1 : DOWN Count
bits : 17 - 17 (1 bit)
access : read-write
PWM Comparison 0 Value Register
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CV : Comparison x Value
bits : 0 - 23 (24 bit)
CVM : Comparison x Value Mode
bits : 24 - 24 (1 bit)
Enumeration: CVMSelect
0x0 : COMPARE_AT_INCREMENT
Compare when counter is incrementing
0x1 : COMPARE_AT_DECREMENT
Compare when counter is decrementing
End of enumeration elements list.
PWM Comparison 0 Value Update Register
address_offset : 0xB44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CVUPD : Comparison x Value Update
bits : 0 - 23 (24 bit)
CVMUPD : Comparison x Value Mode Update
bits : 24 - 24 (1 bit)
PWM Comparison 0 Mode Register
address_offset : 0xB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEN : Comparison x Enable
bits : 0 - 0 (1 bit)
CTR : Comparison x Trigger
bits : 4 - 7 (4 bit)
CPR : Comparison x Period
bits : 8 - 11 (4 bit)
CPRCNT : Comparison x Period Counter
bits : 12 - 15 (4 bit)
CUPR : Comparison x Update Period
bits : 16 - 19 (4 bit)
CUPRCNT : Comparison x Update Period Counter
bits : 20 - 23 (4 bit)
PWM Comparison 0 Mode Update Register
address_offset : 0xB4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
PWM Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
PWM Comparison 0 Mode Update Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Channel Period Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
PWM Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : read-only
PWM Comparison 0 Mode Update Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CENUPD : Comparison x Enable Update
bits : 0 - 0 (1 bit)
CTRUPD : Comparison x Trigger Update
bits : 4 - 7 (4 bit)
CPRUPD : Comparison x Period Update
bits : 8 - 11 (4 bit)
CUPRUPD : Comparison x Update Period Update
bits : 16 - 19 (4 bit)
PWM Channel Period Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 23 (24 bit)
PWM Fault Protection Value 2 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPZH0 : Fault Protection to Hi-Z for PWMH output on channel 0
bits : 0 - 0 (1 bit)
FPZH1 : Fault Protection to Hi-Z for PWMH output on channel 1
bits : 1 - 1 (1 bit)
FPZH2 : Fault Protection to Hi-Z for PWMH output on channel 2
bits : 2 - 2 (1 bit)
FPZH3 : Fault Protection to Hi-Z for PWMH output on channel 3
bits : 3 - 3 (1 bit)
FPZL0 : Fault Protection to Hi-Z for PWML output on channel 0
bits : 16 - 16 (1 bit)
FPZL1 : Fault Protection to Hi-Z for PWML output on channel 1
bits : 17 - 17 (1 bit)
FPZL2 : Fault Protection to Hi-Z for PWML output on channel 2
bits : 18 - 18 (1 bit)
FPZL3 : Fault Protection to Hi-Z for PWML output on channel 3
bits : 19 - 19 (1 bit)
PWM Fault Protection Value 2 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPZH0 : Fault Protection to Hi-Z for PWMH output on channel 0
bits : 0 - 0 (1 bit)
FPZH1 : Fault Protection to Hi-Z for PWMH output on channel 1
bits : 1 - 1 (1 bit)
FPZH2 : Fault Protection to Hi-Z for PWMH output on channel 2
bits : 2 - 2 (1 bit)
FPZH3 : Fault Protection to Hi-Z for PWMH output on channel 3
bits : 3 - 3 (1 bit)
FPZL0 : Fault Protection to Hi-Z for PWML output on channel 0
bits : 16 - 16 (1 bit)
FPZL1 : Fault Protection to Hi-Z for PWML output on channel 1
bits : 17 - 17 (1 bit)
FPZL2 : Fault Protection to Hi-Z for PWML output on channel 2
bits : 18 - 18 (1 bit)
FPZL3 : Fault Protection to Hi-Z for PWML output on channel 3
bits : 19 - 19 (1 bit)
PWM Fault Protection Value 2 Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPZH0 : Fault Protection to Hi-Z for PWMH output on channel 0
bits : 0 - 0 (1 bit)
access : read-write
FPZH1 : Fault Protection to Hi-Z for PWMH output on channel 1
bits : 1 - 1 (1 bit)
access : read-write
FPZH2 : Fault Protection to Hi-Z for PWMH output on channel 2
bits : 2 - 2 (1 bit)
access : read-write
FPZH3 : Fault Protection to Hi-Z for PWMH output on channel 3
bits : 3 - 3 (1 bit)
access : read-write
FPZL0 : Fault Protection to Hi-Z for PWML output on channel 0
bits : 16 - 16 (1 bit)
access : read-write
FPZL1 : Fault Protection to Hi-Z for PWML output on channel 1
bits : 17 - 17 (1 bit)
access : read-write
FPZL2 : Fault Protection to Hi-Z for PWML output on channel 2
bits : 18 - 18 (1 bit)
access : read-write
FPZL3 : Fault Protection to Hi-Z for PWML output on channel 3
bits : 19 - 19 (1 bit)
access : read-write
PWM Write Protection Control Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WPCMD : Write Protection Command
bits : 0 - 1 (2 bit)
Enumeration: WPCMDSelect
0x0 : DISABLE_SW_PROT
Disables the software write protection of the register groups of which the bit WPRGx is at '1'.
0x1 : ENABLE_SW_PROT
Enables the software write protection of the register groups of which the bit WPRGx is at '1'.
0x2 : ENABLE_HW_PROT
Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface.
End of enumeration elements list.
WPRG0 : Write Protection Register Group 0
bits : 2 - 2 (1 bit)
WPRG1 : Write Protection Register Group 1
bits : 3 - 3 (1 bit)
WPRG2 : Write Protection Register Group 2
bits : 4 - 4 (1 bit)
WPRG3 : Write Protection Register Group 3
bits : 5 - 5 (1 bit)
WPRG4 : Write Protection Register Group 4
bits : 6 - 6 (1 bit)
WPRG5 : Write Protection Register Group 5
bits : 7 - 7 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x50574D : PASSWD
Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0
End of enumeration elements list.
PWM Write Protection Control Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WPCMD : Write Protection Command
bits : 0 - 1 (2 bit)
Enumeration: WPCMDSelect
0x0 : DISABLE_SW_PROT
Disables the software write protection of the register groups of which the bit WPRGx is at '1'.
0x1 : ENABLE_SW_PROT
Enables the software write protection of the register groups of which the bit WPRGx is at '1'.
0x2 : ENABLE_HW_PROT
Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface.
End of enumeration elements list.
WPRG0 : Write Protection Register Group 0
bits : 2 - 2 (1 bit)
WPRG1 : Write Protection Register Group 1
bits : 3 - 3 (1 bit)
WPRG2 : Write Protection Register Group 2
bits : 4 - 4 (1 bit)
WPRG3 : Write Protection Register Group 3
bits : 5 - 5 (1 bit)
WPRG4 : Write Protection Register Group 4
bits : 6 - 6 (1 bit)
WPRG5 : Write Protection Register Group 5
bits : 7 - 7 (1 bit)
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
Enumeration: WPKEYSelect
0x50574D : PASSWD
Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0
End of enumeration elements list.
PWM Write Protection Control Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WPCMD : Write Protection Command
bits : 0 - 1 (2 bit)
access : write-only
Enumeration: WPCMDSelect
0x0 : DISABLE_SW_PROT
Disables the software write protection of the register groups of which the bit WPRGx is at '1'.
0x1 : ENABLE_SW_PROT
Enables the software write protection of the register groups of which the bit WPRGx is at '1'.
0x2 : ENABLE_HW_PROT
Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface.
End of enumeration elements list.
WPRG0 : Write Protection Register Group 0
bits : 2 - 2 (1 bit)
access : write-only
WPRG1 : Write Protection Register Group 1
bits : 3 - 3 (1 bit)
access : write-only
WPRG2 : Write Protection Register Group 2
bits : 4 - 4 (1 bit)
access : write-only
WPRG3 : Write Protection Register Group 3
bits : 5 - 5 (1 bit)
access : write-only
WPRG4 : Write Protection Register Group 4
bits : 6 - 6 (1 bit)
access : write-only
WPRG5 : Write Protection Register Group 5
bits : 7 - 7 (1 bit)
access : write-only
WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : write-only
Enumeration: WPKEYSelect
0x50574D : PASSWD
Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0
End of enumeration elements list.
PWM Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPSWS0 : Write Protect SW Status
bits : 0 - 0 (1 bit)
WPSWS1 : Write Protect SW Status
bits : 1 - 1 (1 bit)
WPSWS2 : Write Protect SW Status
bits : 2 - 2 (1 bit)
WPSWS3 : Write Protect SW Status
bits : 3 - 3 (1 bit)
WPSWS4 : Write Protect SW Status
bits : 4 - 4 (1 bit)
WPSWS5 : Write Protect SW Status
bits : 5 - 5 (1 bit)
WPVS : Write Protect Violation Status
bits : 7 - 7 (1 bit)
WPHWS0 : Write Protect HW Status
bits : 8 - 8 (1 bit)
WPHWS1 : Write Protect HW Status
bits : 9 - 9 (1 bit)
WPHWS2 : Write Protect HW Status
bits : 10 - 10 (1 bit)
WPHWS3 : Write Protect HW Status
bits : 11 - 11 (1 bit)
WPHWS4 : Write Protect HW Status
bits : 12 - 12 (1 bit)
WPHWS5 : Write Protect HW Status
bits : 13 - 13 (1 bit)
WPVSRC : Write Protect Violation Source
bits : 16 - 31 (16 bit)
PWM Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPSWS0 : Write Protect SW Status
bits : 0 - 0 (1 bit)
WPSWS1 : Write Protect SW Status
bits : 1 - 1 (1 bit)
WPSWS2 : Write Protect SW Status
bits : 2 - 2 (1 bit)
WPSWS3 : Write Protect SW Status
bits : 3 - 3 (1 bit)
WPSWS4 : Write Protect SW Status
bits : 4 - 4 (1 bit)
WPSWS5 : Write Protect SW Status
bits : 5 - 5 (1 bit)
WPVS : Write Protect Violation Status
bits : 7 - 7 (1 bit)
WPHWS0 : Write Protect HW Status
bits : 8 - 8 (1 bit)
WPHWS1 : Write Protect HW Status
bits : 9 - 9 (1 bit)
WPHWS2 : Write Protect HW Status
bits : 10 - 10 (1 bit)
WPHWS3 : Write Protect HW Status
bits : 11 - 11 (1 bit)
WPHWS4 : Write Protect HW Status
bits : 12 - 12 (1 bit)
WPHWS5 : Write Protect HW Status
bits : 13 - 13 (1 bit)
WPVSRC : Write Protect Violation Source
bits : 16 - 31 (16 bit)
PWM Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPSWS0 : Write Protect SW Status
bits : 0 - 0 (1 bit)
access : read-only
WPSWS1 : Write Protect SW Status
bits : 1 - 1 (1 bit)
access : read-only
WPSWS2 : Write Protect SW Status
bits : 2 - 2 (1 bit)
access : read-only
WPSWS3 : Write Protect SW Status
bits : 3 - 3 (1 bit)
access : read-only
WPSWS4 : Write Protect SW Status
bits : 4 - 4 (1 bit)
access : read-only
WPSWS5 : Write Protect SW Status
bits : 5 - 5 (1 bit)
access : read-only
WPVS : Write Protect Violation Status
bits : 7 - 7 (1 bit)
access : read-only
WPHWS0 : Write Protect HW Status
bits : 8 - 8 (1 bit)
access : read-only
WPHWS1 : Write Protect HW Status
bits : 9 - 9 (1 bit)
access : read-only
WPHWS2 : Write Protect HW Status
bits : 10 - 10 (1 bit)
access : read-only
WPHWS3 : Write Protect HW Status
bits : 11 - 11 (1 bit)
access : read-only
WPHWS4 : Write Protect HW Status
bits : 12 - 12 (1 bit)
access : read-only
WPHWS5 : Write Protect HW Status
bits : 13 - 13 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 16 - 31 (16 bit)
access : read-only
PWM Event Line 0 Mode Register 0
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSEL0 : Comparison 0 Selection
bits : 0 - 0 (1 bit)
CSEL1 : Comparison 1 Selection
bits : 1 - 1 (1 bit)
CSEL2 : Comparison 2 Selection
bits : 2 - 2 (1 bit)
CSEL3 : Comparison 3 Selection
bits : 3 - 3 (1 bit)
CSEL4 : Comparison 4 Selection
bits : 4 - 4 (1 bit)
CSEL5 : Comparison 5 Selection
bits : 5 - 5 (1 bit)
CSEL6 : Comparison 6 Selection
bits : 6 - 6 (1 bit)
CSEL7 : Comparison 7 Selection
bits : 7 - 7 (1 bit)
Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
VERSION : Version of the Hardware Module
bits : 0 - 11 (12 bit)
access : read-only
MFN : Metal Fix Number
bits : 16 - 18 (3 bit)
access : read-only
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