\n
address_offset : 0x0 Bytes (0x0)
size : 0x3E0 byte (0x0)
mem_usage : registers
protection : not protected
MediaLB Control 0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MLBEN : MediaLB Enable
bits : 0 - 0 (1 bit)
MLBCLK : MLBCLK (MediaLB clock) Speed Select
bits : 2 - 4 (3 bit)
Enumeration: MLBCLKSelect
0x0 : _256_FS
256xFs (for MLBPEN = 0)
0x1 : _512_FS
512xFs (for MLBPEN = 0)
0x2 : _1024_FS
1024xFs (for MLBPEN = 0)
End of enumeration elements list.
ZERO : Must be Written to 0
bits : 5 - 5 (1 bit)
MLBLK : MediaLB Lock Status (read-only)
bits : 7 - 7 (1 bit)
ASYRETRY : Asynchronous Tx Packet Retry
bits : 12 - 12 (1 bit)
CTLRETRY : Control Tx Packet Retry
bits : 14 - 14 (1 bit)
FCNT : The number of frames per sub-buffer for synchronous channels
bits : 15 - 17 (3 bit)
Enumeration: FCNTSelect
0x0 : _1_FRAME
1 frame per sub-buffer (Operation is the same as Standard mode.)
0x1 : _2_FRAMES
2 frames per sub-buffer
0x2 : _4_FRAMES
4 frames per sub-buffer
0x3 : _8_FRAMES
8 frames per sub-buffer
0x4 : _16_FRAMES
16 frames per sub-buffer
0x5 : _32_FRAMES
32 frames per sub-buffer
0x6 : _64_FRAMES
64 frames per sub-buffer
End of enumeration elements list.
HBI Channel Mask 0 Register 0
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHM : Bitwise Channel Mask Bit [31:0]
bits : 0 - 31 (32 bit)
HBI Channel Error 0 Register 0
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CERR : Bitwise Channel Error Bit [31:0]
bits : 0 - 31 (32 bit)
HBI Channel Busy 0 Register 0
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHB : Bitwise Channel Busy Bit [31:0]
bits : 0 - 31 (32 bit)
MediaLB Channel Status1 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCS : MediaLB Channel Status [63:32] (cleared by writing a 0)
bits : 0 - 31 (32 bit)
MIF Data 0 Register 0
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)
HBI Channel Mask 0 Register 0
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHM : Bitwise Channel Mask Bit [31:0]
bits : 0 - 31 (32 bit)
MIF Data Write Enable 0 Register 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)
HBI Channel Error 0 Register 0
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CERR : Bitwise Channel Error Bit [31:0]
bits : 0 - 31 (32 bit)
HBI Channel Busy 0 Register 0
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHB : Bitwise Channel Busy Bit [31:0]
bits : 0 - 31 (32 bit)
MediaLB System Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTSYSCMD : Reset System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 0 - 0 (1 bit)
LKSYSCMD : Network Lock System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 1 - 1 (1 bit)
ULKSYSCMD : Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 2 - 2 (1 bit)
CSSYSCMD : Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 3 - 3 (1 bit)
SWSYSCMD : Software System Command Detected in the System Quadlet (cleared by writing a 0)
bits : 4 - 4 (1 bit)
SERVREQ : Service Request Enabled
bits : 5 - 5 (1 bit)
MediaLB System Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SD0 : System Data (Byte 0)
bits : 0 - 7 (8 bit)
SD1 : System Data (Byte 1)
bits : 8 - 15 (8 bit)
SD2 : System Data (Byte 2)
bits : 16 - 23 (8 bit)
SD3 : System Data (Byte 3)
bits : 24 - 31 (8 bit)
MIF Data 0 Register 0
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)
MIF Data Write Enable 0 Register 0
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)
MediaLB Interrupt Enable Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISOC_PE : Isochronous Rx Protocol Error Enable
bits : 0 - 0 (1 bit)
ISOC_BUFO : Isochronous Rx Buffer Overflow Enable
bits : 1 - 1 (1 bit)
SYNC_PE : Synchronous Protocol Error Enable
bits : 16 - 16 (1 bit)
ARX_DONE : Asynchronous Rx Done Enable
bits : 17 - 17 (1 bit)
ARX_PE : Asynchronous Rx Protocol Error Enable
bits : 18 - 18 (1 bit)
ARX_BREAK : Asynchronous Rx Break Enable
bits : 19 - 19 (1 bit)
ATX_DONE : Asynchronous Tx Packet Done Enable
bits : 20 - 20 (1 bit)
ATX_PE : Asynchronous Tx Protocol Error Enable
bits : 21 - 21 (1 bit)
ATX_BREAK : Asynchronous Tx Break Enable
bits : 22 - 22 (1 bit)
CRX_DONE : Control Rx Packet Done Enable
bits : 24 - 24 (1 bit)
CRX_PE : Control Rx Protocol Error Enable
bits : 25 - 25 (1 bit)
CRX_BREAK : Control Rx Break Enable
bits : 26 - 26 (1 bit)
CTX_DONE : Control Tx Packet Done Enable
bits : 27 - 27 (1 bit)
CTX_PE : Control Tx Protocol Error Enable
bits : 28 - 28 (1 bit)
CTX_BREAK : Control Tx Break Enable
bits : 29 - 29 (1 bit)
MIF Data 0 Register 0
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)
MIF Data Write Enable 0 Register 0
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)
MediaLB Control 1 Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : MediaLB Lock Error Status (cleared by writing a 0)
bits : 6 - 6 (1 bit)
CLKM : MediaLB Clock Missing Status (cleared by writing a 0)
bits : 7 - 7 (1 bit)
NDA : Node Device Address
bits : 8 - 15 (8 bit)
AHB Control Register
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCE : Software Clear Enable
bits : 0 - 0 (1 bit)
SMX : AHB Interrupt Mux Enable
bits : 1 - 1 (1 bit)
DMA_MODE : DMA Mode
bits : 2 - 2 (1 bit)
MPB : DMA Packet Buffering Mode
bits : 4 - 4 (1 bit)
Enumeration: MPBSelect
0 : SINGLE_PACKET
Single-packet mode
1 : MULTIPLE_PACKET
Multiple-packet mode
End of enumeration elements list.
AHB Channel Status 0 Register 0
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHS : Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
bits : 0 - 31 (32 bit)
AHB Channel Status 0 Register 0
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHS : Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
bits : 0 - 31 (32 bit)
MIF Data 0 Register 0
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)
AHB Channel Mask 0 Register 0
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHM : Bitwise Channel Mask Bits 31 to 0
bits : 0 - 31 (32 bit)
AHB Channel Mask 0 Register 0
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHM : Bitwise Channel Mask Bits 31 to 0
bits : 0 - 31 (32 bit)
MIF Data Write Enable 0 Register 0
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)
AHB Channel Status 0 Register 0
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHS : Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
bits : 0 - 31 (32 bit)
AHB Channel Mask 0 Register 0
address_offset : 0x7B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHM : Bitwise Channel Mask Bits 31 to 0
bits : 0 - 31 (32 bit)
HBI Control Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RST0 : Address Generation Unit 0 Software Reset
bits : 0 - 0 (1 bit)
RST1 : Address Generation Unit 1 Software Reset
bits : 1 - 1 (1 bit)
EN : HBI Enable
bits : 15 - 15 (1 bit)
HBI Channel Mask 0 Register 0
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHM : Bitwise Channel Mask Bit [31:0]
bits : 0 - 31 (32 bit)
HBI Channel Mask 0 Register 0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHM : Bitwise Channel Mask Bit [31:0]
bits : 0 - 31 (32 bit)
HBI Channel Error 0 Register 0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CERR : Bitwise Channel Error Bit [31:0]
bits : 0 - 31 (32 bit)
HBI Channel Error 0 Register 0
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CERR : Bitwise Channel Error Bit [31:0]
bits : 0 - 31 (32 bit)
HBI Channel Busy 0 Register 0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHB : Bitwise Channel Busy Bit [31:0]
bits : 0 - 31 (32 bit)
HBI Channel Busy 0 Register 0
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHB : Bitwise Channel Busy Bit [31:0]
bits : 0 - 31 (32 bit)
AHB Channel Status 0 Register 0
address_offset : 0xB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHS : Interrupt Status for Logical Channels [31:0] (cleared by writing a 1)
bits : 0 - 31 (32 bit)
AHB Channel Mask 0 Register 0
address_offset : 0xB8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHM : Bitwise Channel Mask Bits 31 to 0
bits : 0 - 31 (32 bit)
MediaLB Channel Status 0 Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCS : MediaLB Channel Status [31:0] (cleared by writing a 0)
bits : 0 - 31 (32 bit)
MIF Data 0 Register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)
MIF Data 0 Register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)
MIF Data 0 Register 0
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)
MIF Data 0 Register 0
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRT or DBR Data
bits : 0 - 31 (32 bit)
MIF Data Write Enable 0 Register 0
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)
MIF Data Write Enable 0 Register 0
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)
MIF Data Write Enable 0 Register 0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)
MIF Data Write Enable 0 Register 0
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Bitwise Write Enable for CTR Data - bits[31:0]
bits : 0 - 31 (32 bit)
MIF Control Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XCMP : Transfer Complete (Write 0 to Clear)
bits : 0 - 0 (1 bit)
MIF Address Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : CTR or DBR Address
bits : 0 - 13 (14 bit)
TB : Target Location Bit
bits : 30 - 30 (1 bit)
Enumeration: TBSelect
0 : CTR
Selects CTR
1 : DBR
Selects DBR
End of enumeration elements list.
WNR : Write-Not-Read Selection
bits : 31 - 31 (1 bit)
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