\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
Supply Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VROFF : Voltage Regulator Off
bits : 2 - 2 (1 bit)
Enumeration: VROFFSelect
0 : NO_EFFECT
No effect.
1 : STOP_VREG
If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator.
End of enumeration elements list.
XTALSEL : Crystal Oscillator Select
bits : 3 - 3 (1 bit)
Enumeration: XTALSELSelect
0 : NO_EFFECT
No effect.
1 : CRYSTAL_SEL
If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output.
End of enumeration elements list.
KEY : Password
bits : 24 - 31 (8 bit)
Enumeration: KEYSelect
0xA5 : PASSWD
Writing any other value in this field aborts the write operation.
End of enumeration elements list.
Supply Controller Wake-up Inputs Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPEN0 : Wake-up Input Enable 0 to 0
bits : 0 - 0 (1 bit)
Enumeration: WKUPEN0Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN1 : Wake-up Input Enable 0 to 1
bits : 1 - 1 (1 bit)
Enumeration: WKUPEN1Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN2 : Wake-up Input Enable 0 to 2
bits : 2 - 2 (1 bit)
Enumeration: WKUPEN2Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN3 : Wake-up Input Enable 0 to 3
bits : 3 - 3 (1 bit)
Enumeration: WKUPEN3Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN4 : Wake-up Input Enable 0 to 4
bits : 4 - 4 (1 bit)
Enumeration: WKUPEN4Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN5 : Wake-up Input Enable 0 to 5
bits : 5 - 5 (1 bit)
Enumeration: WKUPEN5Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN6 : Wake-up Input Enable 0 to 6
bits : 6 - 6 (1 bit)
Enumeration: WKUPEN6Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN7 : Wake-up Input Enable 0 to 7
bits : 7 - 7 (1 bit)
Enumeration: WKUPEN7Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN8 : Wake-up Input Enable 0 to 8
bits : 8 - 8 (1 bit)
Enumeration: WKUPEN8Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN9 : Wake-up Input Enable 0 to 9
bits : 9 - 9 (1 bit)
Enumeration: WKUPEN9Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN10 : Wake-up Input Enable 0 to 10
bits : 10 - 10 (1 bit)
Enumeration: WKUPEN10Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN11 : Wake-up Input Enable 0 to 11
bits : 11 - 11 (1 bit)
Enumeration: WKUPEN11Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN12 : Wake-up Input Enable 0 to 12
bits : 12 - 12 (1 bit)
Enumeration: WKUPEN12Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPEN13 : Wake-up Input Enable 0 to 13
bits : 13 - 13 (1 bit)
Enumeration: WKUPEN13Select
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input is enabled for a wake-up of the core power supply.
End of enumeration elements list.
WKUPT0 : Wake-up Input Type 0 to 0
bits : 16 - 16 (1 bit)
Enumeration: WKUPT0Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT1 : Wake-up Input Type 0 to 1
bits : 17 - 17 (1 bit)
Enumeration: WKUPT1Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT2 : Wake-up Input Type 0 to 2
bits : 18 - 18 (1 bit)
Enumeration: WKUPT2Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT3 : Wake-up Input Type 0 to 3
bits : 19 - 19 (1 bit)
Enumeration: WKUPT3Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT4 : Wake-up Input Type 0 to 4
bits : 20 - 20 (1 bit)
Enumeration: WKUPT4Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT5 : Wake-up Input Type 0 to 5
bits : 21 - 21 (1 bit)
Enumeration: WKUPT5Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT6 : Wake-up Input Type 0 to 6
bits : 22 - 22 (1 bit)
Enumeration: WKUPT6Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT7 : Wake-up Input Type 0 to 7
bits : 23 - 23 (1 bit)
Enumeration: WKUPT7Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT8 : Wake-up Input Type 0 to 8
bits : 24 - 24 (1 bit)
Enumeration: WKUPT8Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT9 : Wake-up Input Type 0 to 9
bits : 25 - 25 (1 bit)
Enumeration: WKUPT9Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT10 : Wake-up Input Type 0 to 10
bits : 26 - 26 (1 bit)
Enumeration: WKUPT10Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT11 : Wake-up Input Type 0 to 11
bits : 27 - 27 (1 bit)
Enumeration: WKUPT11Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT12 : Wake-up Input Type 0 to 12
bits : 28 - 28 (1 bit)
Enumeration: WKUPT12Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
WKUPT13 : Wake-up Input Type 0 to 13
bits : 29 - 29 (1 bit)
Enumeration: WKUPT13Select
0 : LOW
A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply.
1 : HIGH
A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply.
End of enumeration elements list.
Supply Controller Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WKUPS : WKUP Wake-up Status (cleared on read)
bits : 1 - 1 (1 bit)
Enumeration: WKUPSSelect
0 : NO
No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
End of enumeration elements list.
SMWS : Supply Monitor Detection Wake-up Status (cleared on read)
bits : 2 - 2 (1 bit)
Enumeration: SMWSSelect
0 : NO
No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
End of enumeration elements list.
BODRSTS : Brownout Detector Reset Status (cleared on read)
bits : 3 - 3 (1 bit)
Enumeration: BODRSTSSelect
0 : NO
No core brownout rising edge event has been detected since the last read of the SUPC_SR.
1 : PRESENT
At least one brownout output rising edge event has been detected since the last read of the SUPC_SR.
End of enumeration elements list.
SMRSTS : Supply Monitor Reset Status (cleared on read)
bits : 4 - 4 (1 bit)
Enumeration: SMRSTSSelect
0 : NO
No supply monitor detection has generated a core reset since the last read of the SUPC_SR.
1 : PRESENT
At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
End of enumeration elements list.
SMS : Supply Monitor Status (cleared on read)
bits : 5 - 5 (1 bit)
Enumeration: SMSSelect
0 : NO
No supply monitor detection since the last read of SUPC_SR.
1 : PRESENT
At least one supply monitor detection since the last read of SUPC_SR.
End of enumeration elements list.
SMOS : Supply Monitor Output Status
bits : 6 - 6 (1 bit)
Enumeration: SMOSSelect
0 : HIGH
The supply monitor detected VDDIO higher than its threshold at its last measurement.
1 : LOW
The supply monitor detected VDDIO lower than its threshold at its last measurement.
End of enumeration elements list.
OSCSEL : 32-kHz Oscillator Selection Status
bits : 7 - 7 (1 bit)
Enumeration: OSCSELSelect
0 : RC
The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator.
1 : CRYST
The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.
End of enumeration elements list.
LPDBCS0 : Low-power Debouncer Wake-up Status on WKUP0 (cleared on read)
bits : 13 - 13 (1 bit)
Enumeration: LPDBCS0Select
0 : NO
No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
End of enumeration elements list.
LPDBCS1 : Low-power Debouncer Wake-up Status on WKUP1 (cleared on read)
bits : 14 - 14 (1 bit)
Enumeration: LPDBCS1Select
0 : NO
No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS0 : WKUPx Input Status (cleared on read)
bits : 16 - 16 (1 bit)
Enumeration: WKUPIS0Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS1 : WKUPx Input Status (cleared on read)
bits : 17 - 17 (1 bit)
Enumeration: WKUPIS1Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS2 : WKUPx Input Status (cleared on read)
bits : 18 - 18 (1 bit)
Enumeration: WKUPIS2Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS3 : WKUPx Input Status (cleared on read)
bits : 19 - 19 (1 bit)
Enumeration: WKUPIS3Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS4 : WKUPx Input Status (cleared on read)
bits : 20 - 20 (1 bit)
Enumeration: WKUPIS4Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS5 : WKUPx Input Status (cleared on read)
bits : 21 - 21 (1 bit)
Enumeration: WKUPIS5Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS6 : WKUPx Input Status (cleared on read)
bits : 22 - 22 (1 bit)
Enumeration: WKUPIS6Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS7 : WKUPx Input Status (cleared on read)
bits : 23 - 23 (1 bit)
Enumeration: WKUPIS7Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS8 : WKUPx Input Status (cleared on read)
bits : 24 - 24 (1 bit)
Enumeration: WKUPIS8Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS9 : WKUPx Input Status (cleared on read)
bits : 25 - 25 (1 bit)
Enumeration: WKUPIS9Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS10 : WKUPx Input Status (cleared on read)
bits : 26 - 26 (1 bit)
Enumeration: WKUPIS10Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS11 : WKUPx Input Status (cleared on read)
bits : 27 - 27 (1 bit)
Enumeration: WKUPIS11Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS12 : WKUPx Input Status (cleared on read)
bits : 28 - 28 (1 bit)
Enumeration: WKUPIS12Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
WKUPIS13 : WKUPx Input Status (cleared on read)
bits : 29 - 29 (1 bit)
Enumeration: WKUPIS13Select
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
End of enumeration elements list.
Supply Controller Supply Monitor Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMTH : Supply Monitor Threshold
bits : 0 - 3 (4 bit)
SMSMPL : Supply Monitor Sampling Period
bits : 8 - 10 (3 bit)
Enumeration: SMSMPLSelect
0x0 : SMD
Supply Monitor disabled
0x1 : CSM
Continuous Supply Monitor
0x2 : _32SLCK
Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3 : _256SLCK
Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4 : _2048SLCK
Supply Monitor enabled one SLCK period every 2,048 SLCK periods
End of enumeration elements list.
SMRSTEN : Supply Monitor Reset Enable
bits : 12 - 12 (1 bit)
Enumeration: SMRSTENSelect
0 : NOT_ENABLE
The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs.
1 : ENABLE
The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
End of enumeration elements list.
SMIEN : Supply Monitor Interrupt Enable
bits : 13 - 13 (1 bit)
Enumeration: SMIENSelect
0 : NOT_ENABLE
The SUPC interrupt signal is not affected when a supply monitor detection occurs.
1 : ENABLE
The SUPC interrupt signal is asserted when a supply monitor detection occurs.
End of enumeration elements list.
Supply Controller Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODRSTEN : Brownout Detector Reset Enable
bits : 12 - 12 (1 bit)
Enumeration: BODRSTENSelect
0 : NOT_ENABLE
The core reset signal vddcore_nreset is not affected when a brownout detection occurs.
1 : ENABLE
The core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
End of enumeration elements list.
BODDIS : Brownout Detector Disable
bits : 13 - 13 (1 bit)
Enumeration: BODDISSelect
0 : ENABLE
The core brownout detector is enabled.
1 : DISABLE
The core brownout detector is disabled.
End of enumeration elements list.
ONREG : Voltage Regulator Enable
bits : 14 - 14 (1 bit)
Enumeration: ONREGSelect
0 : ONREG_UNUSED
Internal voltage regulator is not used (external power supply is used).
1 : ONREG_USED
Internal voltage regulator is used.
End of enumeration elements list.
BKUPRETON : SRAM On In Backup Mode
bits : 17 - 17 (1 bit)
OSCBYPASS : Oscillator Bypass
bits : 20 - 20 (1 bit)
Enumeration: OSCBYPASSSelect
0 : NO_EFFECT
No effect. Clock selection depends on the value of XTALSEL (SUPC_CR).
1 : BYPASS
The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL.
End of enumeration elements list.
KEY : Password Key
bits : 24 - 31 (8 bit)
Enumeration: KEYSelect
0xA5 : PASSWD
Writing any other value in this field aborts the write operation.
End of enumeration elements list.
Supply Controller Wake-up Mode Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMEN : Supply Monitor Wake-up Enable
bits : 1 - 1 (1 bit)
Enumeration: SMENSelect
0 : NOT_ENABLE
The supply monitor detection has no wake-up effect.
1 : ENABLE
The supply monitor detection forces the wake-up of the core power supply.
End of enumeration elements list.
RTTEN : Real-time Timer Wake-up Enable
bits : 2 - 2 (1 bit)
Enumeration: RTTENSelect
0 : NOT_ENABLE
The RTT alarm signal has no wake-up effect.
1 : ENABLE
The RTT alarm signal forces the wake-up of the core power supply.
End of enumeration elements list.
RTCEN : Real-time Clock Wake-up Enable
bits : 3 - 3 (1 bit)
Enumeration: RTCENSelect
0 : NOT_ENABLE
The RTC alarm signal has no wake-up effect.
1 : ENABLE
The RTC alarm signal forces the wake-up of the core power supply.
End of enumeration elements list.
LPDBCEN0 : Low-power Debouncer Enable WKUP0
bits : 5 - 5 (1 bit)
Enumeration: LPDBCEN0Select
0 : NOT_ENABLE
The WKUP0 input pin is not connected to the low-power debouncer.
1 : ENABLE
The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up.
End of enumeration elements list.
LPDBCEN1 : Low-power Debouncer Enable WKUP1
bits : 6 - 6 (1 bit)
Enumeration: LPDBCEN1Select
0 : NOT_ENABLE
The WKUP1 input pin is not connected to the low-power debouncer.
1 : ENABLE
The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up.
End of enumeration elements list.
LPDBCCLR : Low-power Debouncer Clear
bits : 7 - 7 (1 bit)
Enumeration: LPDBCCLRSelect
0 : NOT_ENABLE
A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
1 : ENABLE
A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers.
End of enumeration elements list.
WKUPDBC : Wake-up Inputs Debouncer Period
bits : 12 - 14 (3 bit)
Enumeration: WKUPDBCSelect
0x0 : IMMEDIATE
Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x1 : _3_SLCK
WKUPx shall be in its active state for at least 3 SLCK periods
0x2 : _32_SLCK
WKUPx shall be in its active state for at least 32 SLCK periods
0x3 : _512_SLCK
WKUPx shall be in its active state for at least 512 SLCK periods
0x4 : _4096_SLCK
WKUPx shall be in its active state for at least 4,096 SLCK periods
0x5 : _32768_SLCK
WKUPx shall be in its active state for at least 32,768 SLCK periods
End of enumeration elements list.
LPDBC : Low-power Debouncer Period
bits : 16 - 18 (3 bit)
Enumeration: LPDBCSelect
0x0 : DISABLE
Disable the low-power debouncers.
0x1 : _2_RTCOUT
WKUP0/1 in active state for at least 2 RTCOUTx clock periods
0x2 : _3_RTCOUT
WKUP0/1 in active state for at least 3 RTCOUTx clock periods
0x3 : _4_RTCOUT
WKUP0/1 in active state for at least 4 RTCOUTx clock periods
0x4 : _5_RTCOUT
WKUP0/1 in active state for at least 5 RTCOUTx clock periods
0x5 : _6_RTCOUT
WKUP0/1 in active state for at least 6 RTCOUTx clock periods
0x6 : _7_RTCOUT
WKUP0/1 in active state for at least 7 RTCOUTx clock periods
0x7 : _8_RTCOUT
WKUP0/1 in active state for at least 8 RTCOUTx clock periods
End of enumeration elements list.
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