\n

XDMAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GTYPE

CIE

GID

CSA

CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CSUS2

CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CDUS2

CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CIE3

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CID3

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CIM3

CIS3

CSA3

CDA3

CNDA3

CNDC3

CUBC3

CBC3

CC3

CDS_MSP3

GIM

CDA

CSUS3

CDUS3

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CIE4

CID4

CIM4

CIS4

CSA4

CDA4

CNDA4

CNDC4

CUBC4

CBC4

CC4

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CDS_MSP4

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

GIS

CNDA

CSUS4

CDUS4

CIE5

CID5

CIM5

CIS5

CSA5

CDA5

CNDA5

CNDC5

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CUBC5

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CBC5

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CC5

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CDS_MSP5

GE

CNDC

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CSUS5

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CDUS5

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CIE6

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CID6

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CIM6

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CIS6

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CSA6

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CDA6

CNDA6

CNDC6

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CUBC6

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CBC6

CC6

CDS_MSP6

GD

CUBC

CSUS6

CDUS6

CIE7

CID7

CIM7

CIS7

CSA7

CDA7

CNDA7

CNDC7

CUBC7

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CBC7

CC7

CDS_MSP7

GS

CBC

CSUS7

CDUS7

CIE8

CID8

CIM8

CIS8

CSA8

CDA8

CNDA8

CNDC8

CUBC8

CBC8

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CC8

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CDS_MSP8

GRS

CC

CSUS8

CDUS8

CIE9

CID9

CIM9

CIS9

CSA9

CDA9

CNDA9

CNDC9

CUBC9

CBC9

CC9

CDS_MSP9

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

GWS

CDS_MSP

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CSUS9

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CDUS9

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CIE10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CID10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CIM10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CIS10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CSA10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CDA10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CNDA10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CNDC10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CUBC10

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CBC10

CC10

CDS_MSP10

GRWS

CSUS

CSUS10

CDUS10

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CIE11

CID11

CIM11

CIS11

CSA11

CDA11

CNDA11

CNDC11

CUBC11

CBC11

CC11

CDS_MSP11

GRWR

CDUS

CSUS11

CDUS11

CIE12

CID12

CIM12

CIS12

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CSA12

CDA12

CNDA12

CNDC12

CUBC12

CBC12

CC12

CDS_MSP12

GSWR

CSUS12

CDUS12

CIE13

CID13

CIM13

CIS13

CSA13

CDA13

CNDA13

CNDC13

CUBC13

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CBC13

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CC13

CDS_MSP13

GSWS

CSUS13

CDUS13

CIE14

CID14

CIM14

CIS14

CSA14

CDA14

CNDA14

CNDC14

CUBC14

CBC14

CC14

CDS_MSP14

GCFG

CID

GSWF

CSUS14

CDUS14

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CIE15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CID15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CIM15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CIS15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CSA15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CDA15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CNDA15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CNDC15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CUBC15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CBC15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CC15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CDS_MSP15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CSUS15

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CDUS15

CIE16

CID16

CIM16

CIS16

CSA16

CDA16

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CNDA16

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CNDC16

CUBC16

CBC16

CC16

CDS_MSP16

CSUS16

CDUS16

CIE17

CID17

CIM17

CIS17

CSA17

CDA17

CNDA17

CNDC17

CUBC17

CBC17

CC17

CDS_MSP17

CSUS17

CDUS17

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CIE18

CID18

CIM18

CIS18

CSA18

CDA18

CNDA18

CNDC18

CUBC18

CBC18

CC18

CDS_MSP18

CHID[0]-XDMAC_CIE

CIE0

CSUS18

CDUS18

CIE19

CID19

CIM19

CIS19

CSA19

CDA19

CNDA19

CNDC19

CUBC19

CBC19

CC19

CDS_MSP19

CHID[0]-XDMAC_CID

CID0

CSUS19

CDUS19

CIE20

CID20

CIM20

CIS20

CSA20

CDA20

CNDA20

CNDC20

CUBC20

CBC20

CC20

CDS_MSP20

CHID[0]-XDMAC_CIM

CIM0

CSUS20

CDUS20

CIE21

CID21

CIM21

CIS21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CSA21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CDA21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CNDA21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CNDC21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CUBC21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CBC21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CC21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CDS_MSP21

CHID[0]-XDMAC_CIS

CIS0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CSUS21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CDUS21

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CIE22

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CID22

CIM22

CIS22

CSA22

CDA22

CNDA22

CNDC22

CUBC22

CBC22

CC22

CDS_MSP22

CHID[0]-XDMAC_CSA

CSA0

CSUS22

CDUS22

CIE23

CID23

CIM23

CIS23

CSA23

CDA23

CNDA23

CNDC23

CUBC23

CBC23

CC23

CDS_MSP23

CHID[0]-XDMAC_CDA

CDA0

CSUS23

CDUS23

CHID[0]-XDMAC_CNDA

CNDA0

CHID[0]-XDMAC_CNDC

CNDC0

CHID[0]-XDMAC_CUBC

CUBC0

CHID[0]-XDMAC_CBC

CBC0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[0]-XDMAC_CC

CC0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CHID[0]-XDMAC_CDS_MSP

CDS_MSP0

GWAC

CIM

CHID[0]-XDMAC_CSUS

CSUS0

CHID[0]-XDMAC_CDUS

CDUS0

CIE1

CID1

CIM1

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CIS1

CSA1

CDA1

CNDA1

CNDC1

CUBC1

CBC1

CC1

CDS_MSP1

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

GIE

CIS

CSUS1

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CDUS1

CIE2

CID2

CIM2

CIS2

CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CSA2

CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CDA2

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

CNDA2

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

CNDC2

CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

CUBC2

CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

CBC2

CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

CC2

CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

CDS_MSP2

VERSION


GTYPE

Global Type Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GTYPE GTYPE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NB_CH FIFO_SZ NB_REQ

NB_CH : Number of Channels Minus One
bits : 0 - 4 (5 bit)

FIFO_SZ : Number of Bytes
bits : 5 - 15 (11 bit)

NB_REQ : Number of Peripheral Requests Minus One
bits : 16 - 22 (7 bit)


CIE

Channel Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CIE CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


GID

Global Interrupt Disable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GID GID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 ID11 ID12 ID13 ID14 ID15 ID16 ID17 ID18 ID19 ID20 ID21 ID22 ID23

ID0 : XDMAC Channel 0 Interrupt Disable Bit
bits : 0 - 0 (1 bit)

ID1 : XDMAC Channel 1 Interrupt Disable Bit
bits : 1 - 1 (1 bit)

ID2 : XDMAC Channel 2 Interrupt Disable Bit
bits : 2 - 2 (1 bit)

ID3 : XDMAC Channel 3 Interrupt Disable Bit
bits : 3 - 3 (1 bit)

ID4 : XDMAC Channel 4 Interrupt Disable Bit
bits : 4 - 4 (1 bit)

ID5 : XDMAC Channel 5 Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ID6 : XDMAC Channel 6 Interrupt Disable Bit
bits : 6 - 6 (1 bit)

ID7 : XDMAC Channel 7 Interrupt Disable Bit
bits : 7 - 7 (1 bit)

ID8 : XDMAC Channel 8 Interrupt Disable Bit
bits : 8 - 8 (1 bit)

ID9 : XDMAC Channel 9 Interrupt Disable Bit
bits : 9 - 9 (1 bit)

ID10 : XDMAC Channel 10 Interrupt Disable Bit
bits : 10 - 10 (1 bit)

ID11 : XDMAC Channel 11 Interrupt Disable Bit
bits : 11 - 11 (1 bit)

ID12 : XDMAC Channel 12 Interrupt Disable Bit
bits : 12 - 12 (1 bit)

ID13 : XDMAC Channel 13 Interrupt Disable Bit
bits : 13 - 13 (1 bit)

ID14 : XDMAC Channel 14 Interrupt Disable Bit
bits : 14 - 14 (1 bit)

ID15 : XDMAC Channel 15 Interrupt Disable Bit
bits : 15 - 15 (1 bit)

ID16 : XDMAC Channel 16 Interrupt Disable Bit
bits : 16 - 16 (1 bit)

ID17 : XDMAC Channel 17 Interrupt Disable Bit
bits : 17 - 17 (1 bit)

ID18 : XDMAC Channel 18 Interrupt Disable Bit
bits : 18 - 18 (1 bit)

ID19 : XDMAC Channel 19 Interrupt Disable Bit
bits : 19 - 19 (1 bit)

ID20 : XDMAC Channel 20 Interrupt Disable Bit
bits : 20 - 20 (1 bit)

ID21 : XDMAC Channel 21 Interrupt Disable Bit
bits : 21 - 21 (1 bit)

ID22 : XDMAC Channel 22 Interrupt Disable Bit
bits : 22 - 22 (1 bit)

ID23 : XDMAC Channel 23 Interrupt Disable Bit
bits : 23 - 23 (1 bit)


CSA

Channel Source Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSA CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CSUS2

Channel Source Microblock Stride (chid = 2)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS2 CSUS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CDUS2

Channel Destination Microblock Stride (chid = 2)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS2 CDUS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CIE3

Channel Interrupt Enable Register (chid = 3)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE3 CIE3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x1130 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x1134 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x1138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x113C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CID3

Channel Interrupt Disable Register (chid = 3)
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID3 CID3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x1140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x1148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x114C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x1150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x1154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x1158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x115C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x1160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x1164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CIM3

Channel Interrupt Mask Register (chid = 3)
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM3 CIM3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS3

Channel Interrupt Status Register (chid = 3)
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS3 CIS3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA3

Channel Source Address Register (chid = 3)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA3 CSA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA3

Channel Destination Address Register (chid = 3)
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA3 CDA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA3

Channel Next Descriptor Address Register (chid = 3)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA3 CNDA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC3

Channel Next Descriptor Control Register (chid = 3)
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC3 CNDC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC3

Channel Microblock Control Register (chid = 3)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC3 CUBC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC3

Channel Block Control Register (chid = 3)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC3 CBC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC3

Channel Configuration Register (chid = 3)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC3 CC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP3

Channel Data Stride Memory Set Pattern (chid = 3)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP3 CDS_MSP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GIM

Global Interrupt Mask Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GIM GIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IM0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 IM8 IM9 IM10 IM11 IM12 IM13 IM14 IM15 IM16 IM17 IM18 IM19 IM20 IM21 IM22 IM23

IM0 : XDMAC Channel 0 Interrupt Mask Bit
bits : 0 - 0 (1 bit)

IM1 : XDMAC Channel 1 Interrupt Mask Bit
bits : 1 - 1 (1 bit)

IM2 : XDMAC Channel 2 Interrupt Mask Bit
bits : 2 - 2 (1 bit)

IM3 : XDMAC Channel 3 Interrupt Mask Bit
bits : 3 - 3 (1 bit)

IM4 : XDMAC Channel 4 Interrupt Mask Bit
bits : 4 - 4 (1 bit)

IM5 : XDMAC Channel 5 Interrupt Mask Bit
bits : 5 - 5 (1 bit)

IM6 : XDMAC Channel 6 Interrupt Mask Bit
bits : 6 - 6 (1 bit)

IM7 : XDMAC Channel 7 Interrupt Mask Bit
bits : 7 - 7 (1 bit)

IM8 : XDMAC Channel 8 Interrupt Mask Bit
bits : 8 - 8 (1 bit)

IM9 : XDMAC Channel 9 Interrupt Mask Bit
bits : 9 - 9 (1 bit)

IM10 : XDMAC Channel 10 Interrupt Mask Bit
bits : 10 - 10 (1 bit)

IM11 : XDMAC Channel 11 Interrupt Mask Bit
bits : 11 - 11 (1 bit)

IM12 : XDMAC Channel 12 Interrupt Mask Bit
bits : 12 - 12 (1 bit)

IM13 : XDMAC Channel 13 Interrupt Mask Bit
bits : 13 - 13 (1 bit)

IM14 : XDMAC Channel 14 Interrupt Mask Bit
bits : 14 - 14 (1 bit)

IM15 : XDMAC Channel 15 Interrupt Mask Bit
bits : 15 - 15 (1 bit)

IM16 : XDMAC Channel 16 Interrupt Mask Bit
bits : 16 - 16 (1 bit)

IM17 : XDMAC Channel 17 Interrupt Mask Bit
bits : 17 - 17 (1 bit)

IM18 : XDMAC Channel 18 Interrupt Mask Bit
bits : 18 - 18 (1 bit)

IM19 : XDMAC Channel 19 Interrupt Mask Bit
bits : 19 - 19 (1 bit)

IM20 : XDMAC Channel 20 Interrupt Mask Bit
bits : 20 - 20 (1 bit)

IM21 : XDMAC Channel 21 Interrupt Mask Bit
bits : 21 - 21 (1 bit)

IM22 : XDMAC Channel 22 Interrupt Mask Bit
bits : 22 - 22 (1 bit)

IM23 : XDMAC Channel 23 Interrupt Mask Bit
bits : 23 - 23 (1 bit)


CDA

Channel Destination Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDA CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CSUS3

Channel Source Microblock Stride (chid = 3)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS3 CSUS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS3

Channel Destination Microblock Stride (chid = 3)
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS3 CDUS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x1440 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x1444 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x1448 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x144C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x1450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x1454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x1458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x145C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x1460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x1464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x1468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x146C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x1470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x1474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CIE4

Channel Interrupt Enable Register (chid = 4)
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE4 CIE4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID4

Channel Interrupt Disable Register (chid = 4)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID4 CID4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM4

Channel Interrupt Mask Register (chid = 4)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM4 CIM4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS4

Channel Interrupt Status Register (chid = 4)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS4 CIS4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA4

Channel Source Address Register (chid = 4)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA4 CSA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA4

Channel Destination Address Register (chid = 4)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA4 CDA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA4

Channel Next Descriptor Address Register (chid = 4)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA4 CNDA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC4

Channel Next Descriptor Control Register (chid = 4)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC4 CNDC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC4

Channel Microblock Control Register (chid = 4)
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC4 CUBC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC4

Channel Block Control Register (chid = 4)
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC4 CBC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC4

Channel Configuration Register (chid = 4)
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC4 CC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x1790 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x1794 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x1798 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x179C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x17A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x17A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x17A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x17AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x17B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x17B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x17B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x17BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CDS_MSP4

Channel Data Stride Memory Set Pattern (chid = 4)
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP4 CDS_MSP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x17C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x17C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


GIS

Global Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GIS GIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IS0 IS1 IS2 IS3 IS4 IS5 IS6 IS7 IS8 IS9 IS10 IS11 IS12 IS13 IS14 IS15 IS16 IS17 IS18 IS19 IS20 IS21 IS22 IS23

IS0 : XDMAC Channel 0 Interrupt Status Bit
bits : 0 - 0 (1 bit)

IS1 : XDMAC Channel 1 Interrupt Status Bit
bits : 1 - 1 (1 bit)

IS2 : XDMAC Channel 2 Interrupt Status Bit
bits : 2 - 2 (1 bit)

IS3 : XDMAC Channel 3 Interrupt Status Bit
bits : 3 - 3 (1 bit)

IS4 : XDMAC Channel 4 Interrupt Status Bit
bits : 4 - 4 (1 bit)

IS5 : XDMAC Channel 5 Interrupt Status Bit
bits : 5 - 5 (1 bit)

IS6 : XDMAC Channel 6 Interrupt Status Bit
bits : 6 - 6 (1 bit)

IS7 : XDMAC Channel 7 Interrupt Status Bit
bits : 7 - 7 (1 bit)

IS8 : XDMAC Channel 8 Interrupt Status Bit
bits : 8 - 8 (1 bit)

IS9 : XDMAC Channel 9 Interrupt Status Bit
bits : 9 - 9 (1 bit)

IS10 : XDMAC Channel 10 Interrupt Status Bit
bits : 10 - 10 (1 bit)

IS11 : XDMAC Channel 11 Interrupt Status Bit
bits : 11 - 11 (1 bit)

IS12 : XDMAC Channel 12 Interrupt Status Bit
bits : 12 - 12 (1 bit)

IS13 : XDMAC Channel 13 Interrupt Status Bit
bits : 13 - 13 (1 bit)

IS14 : XDMAC Channel 14 Interrupt Status Bit
bits : 14 - 14 (1 bit)

IS15 : XDMAC Channel 15 Interrupt Status Bit
bits : 15 - 15 (1 bit)

IS16 : XDMAC Channel 16 Interrupt Status Bit
bits : 16 - 16 (1 bit)

IS17 : XDMAC Channel 17 Interrupt Status Bit
bits : 17 - 17 (1 bit)

IS18 : XDMAC Channel 18 Interrupt Status Bit
bits : 18 - 18 (1 bit)

IS19 : XDMAC Channel 19 Interrupt Status Bit
bits : 19 - 19 (1 bit)

IS20 : XDMAC Channel 20 Interrupt Status Bit
bits : 20 - 20 (1 bit)

IS21 : XDMAC Channel 21 Interrupt Status Bit
bits : 21 - 21 (1 bit)

IS22 : XDMAC Channel 22 Interrupt Status Bit
bits : 22 - 22 (1 bit)

IS23 : XDMAC Channel 23 Interrupt Status Bit
bits : 23 - 23 (1 bit)


CNDA

Channel Next Descriptor Address Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDA CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CSUS4

Channel Source Microblock Stride (chid = 4)
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS4 CSUS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS4

Channel Destination Microblock Stride (chid = 4)
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS4 CDUS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE5

Channel Interrupt Enable Register (chid = 5)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE5 CIE5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID5

Channel Interrupt Disable Register (chid = 5)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID5 CID5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM5

Channel Interrupt Mask Register (chid = 5)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM5 CIM5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS5

Channel Interrupt Status Register (chid = 5)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS5 CIS5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA5

Channel Source Address Register (chid = 5)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA5 CSA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA5

Channel Destination Address Register (chid = 5)
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA5 CDA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA5

Channel Next Descriptor Address Register (chid = 5)
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA5 CNDA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC5

Channel Next Descriptor Control Register (chid = 5)
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC5 CNDC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CUBC5

Channel Microblock Control Register (chid = 5)
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC5 CUBC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x1B20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x1B24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x1B28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x1B2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x1B30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x1B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x1B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x1B3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CBC5

Channel Block Control Register (chid = 5)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC5 CBC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x1B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x1B44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x1B48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x1B4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x1B50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x1B54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CC5

Channel Configuration Register (chid = 5)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC5 CC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CDS_MSP5

Channel Data Stride Memory Set Pattern (chid = 5)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP5 CDS_MSP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GE

Global Channel Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GE GE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 EN8 EN9 EN10 EN11 EN12 EN13 EN14 EN15 EN16 EN17 EN18 EN19 EN20 EN21 EN22 EN23

EN0 : XDMAC Channel 0 Enable Bit
bits : 0 - 0 (1 bit)

EN1 : XDMAC Channel 1 Enable Bit
bits : 1 - 1 (1 bit)

EN2 : XDMAC Channel 2 Enable Bit
bits : 2 - 2 (1 bit)

EN3 : XDMAC Channel 3 Enable Bit
bits : 3 - 3 (1 bit)

EN4 : XDMAC Channel 4 Enable Bit
bits : 4 - 4 (1 bit)

EN5 : XDMAC Channel 5 Enable Bit
bits : 5 - 5 (1 bit)

EN6 : XDMAC Channel 6 Enable Bit
bits : 6 - 6 (1 bit)

EN7 : XDMAC Channel 7 Enable Bit
bits : 7 - 7 (1 bit)

EN8 : XDMAC Channel 8 Enable Bit
bits : 8 - 8 (1 bit)

EN9 : XDMAC Channel 9 Enable Bit
bits : 9 - 9 (1 bit)

EN10 : XDMAC Channel 10 Enable Bit
bits : 10 - 10 (1 bit)

EN11 : XDMAC Channel 11 Enable Bit
bits : 11 - 11 (1 bit)

EN12 : XDMAC Channel 12 Enable Bit
bits : 12 - 12 (1 bit)

EN13 : XDMAC Channel 13 Enable Bit
bits : 13 - 13 (1 bit)

EN14 : XDMAC Channel 14 Enable Bit
bits : 14 - 14 (1 bit)

EN15 : XDMAC Channel 15 Enable Bit
bits : 15 - 15 (1 bit)

EN16 : XDMAC Channel 16 Enable Bit
bits : 16 - 16 (1 bit)

EN17 : XDMAC Channel 17 Enable Bit
bits : 17 - 17 (1 bit)

EN18 : XDMAC Channel 18 Enable Bit
bits : 18 - 18 (1 bit)

EN19 : XDMAC Channel 19 Enable Bit
bits : 19 - 19 (1 bit)

EN20 : XDMAC Channel 20 Enable Bit
bits : 20 - 20 (1 bit)

EN21 : XDMAC Channel 21 Enable Bit
bits : 21 - 21 (1 bit)

EN22 : XDMAC Channel 22 Enable Bit
bits : 22 - 22 (1 bit)

EN23 : XDMAC Channel 23 Enable Bit
bits : 23 - 23 (1 bit)


CNDC

Channel Next Descriptor Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNDC CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CSUS5

Channel Source Microblock Stride (chid = 5)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS5 CSUS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CDUS5

Channel Destination Microblock Stride (chid = 5)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS5 CDUS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CIE6

Channel Interrupt Enable Register (chid = 6)
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE6 CIE6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CID6

Channel Interrupt Disable Register (chid = 6)
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID6 CID6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CIM6

Channel Interrupt Mask Register (chid = 6)
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM6 CIM6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CIS6

Channel Interrupt Status Register (chid = 6)
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS6 CIS6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CSA6

Channel Source Address Register (chid = 6)
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA6 CSA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CDA6

Channel Destination Address Register (chid = 6)
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA6 CDA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA6

Channel Next Descriptor Address Register (chid = 6)
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA6 CNDA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC6

Channel Next Descriptor Control Register (chid = 6)
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC6 CNDC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x1EF0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x1EF4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x1EF8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x1EFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CUBC6

Channel Microblock Control Register (chid = 6)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC6 CUBC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x1F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x1F04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x1F08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x1F0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x1F10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x1F14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x1F18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x1F1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x1F20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x1F24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CBC6

Channel Block Control Register (chid = 6)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC6 CBC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC6

Channel Configuration Register (chid = 6)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC6 CC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP6

Channel Data Stride Memory Set Pattern (chid = 6)
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP6 CDS_MSP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GD

Global Channel Disable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GD GD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 DI16 DI17 DI18 DI19 DI20 DI21 DI22 DI23

DI0 : XDMAC Channel 0 Disable Bit
bits : 0 - 0 (1 bit)

DI1 : XDMAC Channel 1 Disable Bit
bits : 1 - 1 (1 bit)

DI2 : XDMAC Channel 2 Disable Bit
bits : 2 - 2 (1 bit)

DI3 : XDMAC Channel 3 Disable Bit
bits : 3 - 3 (1 bit)

DI4 : XDMAC Channel 4 Disable Bit
bits : 4 - 4 (1 bit)

DI5 : XDMAC Channel 5 Disable Bit
bits : 5 - 5 (1 bit)

DI6 : XDMAC Channel 6 Disable Bit
bits : 6 - 6 (1 bit)

DI7 : XDMAC Channel 7 Disable Bit
bits : 7 - 7 (1 bit)

DI8 : XDMAC Channel 8 Disable Bit
bits : 8 - 8 (1 bit)

DI9 : XDMAC Channel 9 Disable Bit
bits : 9 - 9 (1 bit)

DI10 : XDMAC Channel 10 Disable Bit
bits : 10 - 10 (1 bit)

DI11 : XDMAC Channel 11 Disable Bit
bits : 11 - 11 (1 bit)

DI12 : XDMAC Channel 12 Disable Bit
bits : 12 - 12 (1 bit)

DI13 : XDMAC Channel 13 Disable Bit
bits : 13 - 13 (1 bit)

DI14 : XDMAC Channel 14 Disable Bit
bits : 14 - 14 (1 bit)

DI15 : XDMAC Channel 15 Disable Bit
bits : 15 - 15 (1 bit)

DI16 : XDMAC Channel 16 Disable Bit
bits : 16 - 16 (1 bit)

DI17 : XDMAC Channel 17 Disable Bit
bits : 17 - 17 (1 bit)

DI18 : XDMAC Channel 18 Disable Bit
bits : 18 - 18 (1 bit)

DI19 : XDMAC Channel 19 Disable Bit
bits : 19 - 19 (1 bit)

DI20 : XDMAC Channel 20 Disable Bit
bits : 20 - 20 (1 bit)

DI21 : XDMAC Channel 21 Disable Bit
bits : 21 - 21 (1 bit)

DI22 : XDMAC Channel 22 Disable Bit
bits : 22 - 22 (1 bit)

DI23 : XDMAC Channel 23 Disable Bit
bits : 23 - 23 (1 bit)


CUBC

Channel Microblock Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CUBC CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CSUS6

Channel Source Microblock Stride (chid = 6)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS6 CSUS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS6

Channel Destination Microblock Stride (chid = 6)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS6 CDUS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE7

Channel Interrupt Enable Register (chid = 7)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE7 CIE7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID7

Channel Interrupt Disable Register (chid = 7)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID7 CID7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM7

Channel Interrupt Mask Register (chid = 7)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM7 CIM7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS7

Channel Interrupt Status Register (chid = 7)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS7 CIS7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA7

Channel Source Address Register (chid = 7)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA7 CSA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA7

Channel Destination Address Register (chid = 7)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA7 CDA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA7

Channel Next Descriptor Address Register (chid = 7)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA7 CNDA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC7

Channel Next Descriptor Control Register (chid = 7)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC7 CNDC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC7

Channel Microblock Control Register (chid = 7)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC7 CUBC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x2300 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x2304 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x2308 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x230C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x2310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x2314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x2318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x231C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x2320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x2324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x2328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x232C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x2330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x2334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CBC7

Channel Block Control Register (chid = 7)
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC7 CBC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC7

Channel Configuration Register (chid = 7)
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC7 CC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP7

Channel Data Stride Memory Set Pattern (chid = 7)
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP7 CDS_MSP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GS

Global Channel Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GS GS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7 ST8 ST9 ST10 ST11 ST12 ST13 ST14 ST15 ST16 ST17 ST18 ST19 ST20 ST21 ST22 ST23

ST0 : XDMAC Channel 0 Status Bit
bits : 0 - 0 (1 bit)

ST1 : XDMAC Channel 1 Status Bit
bits : 1 - 1 (1 bit)

ST2 : XDMAC Channel 2 Status Bit
bits : 2 - 2 (1 bit)

ST3 : XDMAC Channel 3 Status Bit
bits : 3 - 3 (1 bit)

ST4 : XDMAC Channel 4 Status Bit
bits : 4 - 4 (1 bit)

ST5 : XDMAC Channel 5 Status Bit
bits : 5 - 5 (1 bit)

ST6 : XDMAC Channel 6 Status Bit
bits : 6 - 6 (1 bit)

ST7 : XDMAC Channel 7 Status Bit
bits : 7 - 7 (1 bit)

ST8 : XDMAC Channel 8 Status Bit
bits : 8 - 8 (1 bit)

ST9 : XDMAC Channel 9 Status Bit
bits : 9 - 9 (1 bit)

ST10 : XDMAC Channel 10 Status Bit
bits : 10 - 10 (1 bit)

ST11 : XDMAC Channel 11 Status Bit
bits : 11 - 11 (1 bit)

ST12 : XDMAC Channel 12 Status Bit
bits : 12 - 12 (1 bit)

ST13 : XDMAC Channel 13 Status Bit
bits : 13 - 13 (1 bit)

ST14 : XDMAC Channel 14 Status Bit
bits : 14 - 14 (1 bit)

ST15 : XDMAC Channel 15 Status Bit
bits : 15 - 15 (1 bit)

ST16 : XDMAC Channel 16 Status Bit
bits : 16 - 16 (1 bit)

ST17 : XDMAC Channel 17 Status Bit
bits : 17 - 17 (1 bit)

ST18 : XDMAC Channel 18 Status Bit
bits : 18 - 18 (1 bit)

ST19 : XDMAC Channel 19 Status Bit
bits : 19 - 19 (1 bit)

ST20 : XDMAC Channel 20 Status Bit
bits : 20 - 20 (1 bit)

ST21 : XDMAC Channel 21 Status Bit
bits : 21 - 21 (1 bit)

ST22 : XDMAC Channel 22 Status Bit
bits : 22 - 22 (1 bit)

ST23 : XDMAC Channel 23 Status Bit
bits : 23 - 23 (1 bit)


CBC

Channel Block Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CBC CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CSUS7

Channel Source Microblock Stride (chid = 7)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS7 CSUS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS7

Channel Destination Microblock Stride (chid = 7)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS7 CDUS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE8

Channel Interrupt Enable Register (chid = 8)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE8 CIE8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID8

Channel Interrupt Disable Register (chid = 8)
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID8 CID8 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM8

Channel Interrupt Mask Register (chid = 8)
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM8 CIM8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS8

Channel Interrupt Status Register (chid = 8)
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS8 CIS8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA8

Channel Source Address Register (chid = 8)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA8 CSA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA8

Channel Destination Address Register (chid = 8)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA8 CDA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA8

Channel Next Descriptor Address Register (chid = 8)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA8 CNDA8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC8

Channel Next Descriptor Control Register (chid = 8)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC8 CNDC8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC8

Channel Microblock Control Register (chid = 8)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC8 CUBC8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC8

Channel Block Control Register (chid = 8)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC8 CBC8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x2750 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x2754 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x2758 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x275C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x2760 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x2764 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x2768 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x276C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x2770 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x2774 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x2778 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x277C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CC8

Channel Configuration Register (chid = 8)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC8 CC8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x2780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x2784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CDS_MSP8

Channel Data Stride Memory Set Pattern (chid = 8)
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP8 CDS_MSP8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GRS

Global Channel Read Suspend Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRS GRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS0 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 RS17 RS18 RS19 RS20 RS21 RS22 RS23

RS0 : XDMAC Channel 0 Read Suspend Bit
bits : 0 - 0 (1 bit)

RS1 : XDMAC Channel 1 Read Suspend Bit
bits : 1 - 1 (1 bit)

RS2 : XDMAC Channel 2 Read Suspend Bit
bits : 2 - 2 (1 bit)

RS3 : XDMAC Channel 3 Read Suspend Bit
bits : 3 - 3 (1 bit)

RS4 : XDMAC Channel 4 Read Suspend Bit
bits : 4 - 4 (1 bit)

RS5 : XDMAC Channel 5 Read Suspend Bit
bits : 5 - 5 (1 bit)

RS6 : XDMAC Channel 6 Read Suspend Bit
bits : 6 - 6 (1 bit)

RS7 : XDMAC Channel 7 Read Suspend Bit
bits : 7 - 7 (1 bit)

RS8 : XDMAC Channel 8 Read Suspend Bit
bits : 8 - 8 (1 bit)

RS9 : XDMAC Channel 9 Read Suspend Bit
bits : 9 - 9 (1 bit)

RS10 : XDMAC Channel 10 Read Suspend Bit
bits : 10 - 10 (1 bit)

RS11 : XDMAC Channel 11 Read Suspend Bit
bits : 11 - 11 (1 bit)

RS12 : XDMAC Channel 12 Read Suspend Bit
bits : 12 - 12 (1 bit)

RS13 : XDMAC Channel 13 Read Suspend Bit
bits : 13 - 13 (1 bit)

RS14 : XDMAC Channel 14 Read Suspend Bit
bits : 14 - 14 (1 bit)

RS15 : XDMAC Channel 15 Read Suspend Bit
bits : 15 - 15 (1 bit)

RS16 : XDMAC Channel 16 Read Suspend Bit
bits : 16 - 16 (1 bit)

RS17 : XDMAC Channel 17 Read Suspend Bit
bits : 17 - 17 (1 bit)

RS18 : XDMAC Channel 18 Read Suspend Bit
bits : 18 - 18 (1 bit)

RS19 : XDMAC Channel 19 Read Suspend Bit
bits : 19 - 19 (1 bit)

RS20 : XDMAC Channel 20 Read Suspend Bit
bits : 20 - 20 (1 bit)

RS21 : XDMAC Channel 21 Read Suspend Bit
bits : 21 - 21 (1 bit)

RS22 : XDMAC Channel 22 Read Suspend Bit
bits : 22 - 22 (1 bit)

RS23 : XDMAC Channel 23 Read Suspend Bit
bits : 23 - 23 (1 bit)


CC

Channel Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CSUS8

Channel Source Microblock Stride (chid = 8)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS8 CSUS8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS8

Channel Destination Microblock Stride (chid = 8)
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS8 CDUS8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE9

Channel Interrupt Enable Register (chid = 9)
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE9 CIE9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID9

Channel Interrupt Disable Register (chid = 9)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID9 CID9 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM9

Channel Interrupt Mask Register (chid = 9)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM9 CIM9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS9

Channel Interrupt Status Register (chid = 9)
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS9 CIS9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA9

Channel Source Address Register (chid = 9)
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA9 CSA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA9

Channel Destination Address Register (chid = 9)
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA9 CDA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA9

Channel Next Descriptor Address Register (chid = 9)
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA9 CNDA9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC9

Channel Next Descriptor Control Register (chid = 9)
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC9 CNDC9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC9

Channel Microblock Control Register (chid = 9)
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC9 CUBC9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC9

Channel Block Control Register (chid = 9)
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC9 CBC9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC9

Channel Configuration Register (chid = 9)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC9 CC9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP9

Channel Data Stride Memory Set Pattern (chid = 9)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP9 CDS_MSP9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x2BE0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x2BE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x2BE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x2BEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x2BF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x2BF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x2BF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x2BFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


GWS

Global Channel Write Suspend Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GWS GWS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WS0 WS1 WS2 WS3 WS4 WS5 WS6 WS7 WS8 WS9 WS10 WS11 WS12 WS13 WS14 WS15 WS16 WS17 WS18 WS19 WS20 WS21 WS22 WS23

WS0 : XDMAC Channel 0 Write Suspend Bit
bits : 0 - 0 (1 bit)

WS1 : XDMAC Channel 1 Write Suspend Bit
bits : 1 - 1 (1 bit)

WS2 : XDMAC Channel 2 Write Suspend Bit
bits : 2 - 2 (1 bit)

WS3 : XDMAC Channel 3 Write Suspend Bit
bits : 3 - 3 (1 bit)

WS4 : XDMAC Channel 4 Write Suspend Bit
bits : 4 - 4 (1 bit)

WS5 : XDMAC Channel 5 Write Suspend Bit
bits : 5 - 5 (1 bit)

WS6 : XDMAC Channel 6 Write Suspend Bit
bits : 6 - 6 (1 bit)

WS7 : XDMAC Channel 7 Write Suspend Bit
bits : 7 - 7 (1 bit)

WS8 : XDMAC Channel 8 Write Suspend Bit
bits : 8 - 8 (1 bit)

WS9 : XDMAC Channel 9 Write Suspend Bit
bits : 9 - 9 (1 bit)

WS10 : XDMAC Channel 10 Write Suspend Bit
bits : 10 - 10 (1 bit)

WS11 : XDMAC Channel 11 Write Suspend Bit
bits : 11 - 11 (1 bit)

WS12 : XDMAC Channel 12 Write Suspend Bit
bits : 12 - 12 (1 bit)

WS13 : XDMAC Channel 13 Write Suspend Bit
bits : 13 - 13 (1 bit)

WS14 : XDMAC Channel 14 Write Suspend Bit
bits : 14 - 14 (1 bit)

WS15 : XDMAC Channel 15 Write Suspend Bit
bits : 15 - 15 (1 bit)

WS16 : XDMAC Channel 16 Write Suspend Bit
bits : 16 - 16 (1 bit)

WS17 : XDMAC Channel 17 Write Suspend Bit
bits : 17 - 17 (1 bit)

WS18 : XDMAC Channel 18 Write Suspend Bit
bits : 18 - 18 (1 bit)

WS19 : XDMAC Channel 19 Write Suspend Bit
bits : 19 - 19 (1 bit)

WS20 : XDMAC Channel 20 Write Suspend Bit
bits : 20 - 20 (1 bit)

WS21 : XDMAC Channel 21 Write Suspend Bit
bits : 21 - 21 (1 bit)

WS22 : XDMAC Channel 22 Write Suspend Bit
bits : 22 - 22 (1 bit)

WS23 : XDMAC Channel 23 Write Suspend Bit
bits : 23 - 23 (1 bit)


CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDS_MSP CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CSUS9

Channel Source Microblock Stride (chid = 9)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS9 CSUS9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x2C00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x2C04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x2C08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x2C0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x2C10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x2C14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CDUS9

Channel Destination Microblock Stride (chid = 9)
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS9 CDUS9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CIE10

Channel Interrupt Enable Register (chid = 10)
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE10 CIE10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CID10

Channel Interrupt Disable Register (chid = 10)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID10 CID10 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CIM10

Channel Interrupt Mask Register (chid = 10)
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM10 CIM10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CIS10

Channel Interrupt Status Register (chid = 10)
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS10 CIS10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CSA10

Channel Source Address Register (chid = 10)
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA10 CSA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CDA10

Channel Destination Address Register (chid = 10)
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA10 CDA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CNDA10

Channel Next Descriptor Address Register (chid = 10)
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA10 CNDA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CNDC10

Channel Next Descriptor Control Register (chid = 10)
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC10 CNDC10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CUBC10

Channel Microblock Control Register (chid = 10)
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC10 CUBC10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CBC10

Channel Block Control Register (chid = 10)
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC10 CBC10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC10

Channel Configuration Register (chid = 10)
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC10 CC10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP10

Channel Data Stride Memory Set Pattern (chid = 10)
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP10 CDS_MSP10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GRWS

Global Channel Read Write Suspend Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GRWS GRWS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWS0 RWS1 RWS2 RWS3 RWS4 RWS5 RWS6 RWS7 RWS8 RWS9 RWS10 RWS11 RWS12 RWS13 RWS14 RWS15 RWS16 RWS17 RWS18 RWS19 RWS20 RWS21 RWS22 RWS23

RWS0 : XDMAC Channel 0 Read Write Suspend Bit
bits : 0 - 0 (1 bit)

RWS1 : XDMAC Channel 1 Read Write Suspend Bit
bits : 1 - 1 (1 bit)

RWS2 : XDMAC Channel 2 Read Write Suspend Bit
bits : 2 - 2 (1 bit)

RWS3 : XDMAC Channel 3 Read Write Suspend Bit
bits : 3 - 3 (1 bit)

RWS4 : XDMAC Channel 4 Read Write Suspend Bit
bits : 4 - 4 (1 bit)

RWS5 : XDMAC Channel 5 Read Write Suspend Bit
bits : 5 - 5 (1 bit)

RWS6 : XDMAC Channel 6 Read Write Suspend Bit
bits : 6 - 6 (1 bit)

RWS7 : XDMAC Channel 7 Read Write Suspend Bit
bits : 7 - 7 (1 bit)

RWS8 : XDMAC Channel 8 Read Write Suspend Bit
bits : 8 - 8 (1 bit)

RWS9 : XDMAC Channel 9 Read Write Suspend Bit
bits : 9 - 9 (1 bit)

RWS10 : XDMAC Channel 10 Read Write Suspend Bit
bits : 10 - 10 (1 bit)

RWS11 : XDMAC Channel 11 Read Write Suspend Bit
bits : 11 - 11 (1 bit)

RWS12 : XDMAC Channel 12 Read Write Suspend Bit
bits : 12 - 12 (1 bit)

RWS13 : XDMAC Channel 13 Read Write Suspend Bit
bits : 13 - 13 (1 bit)

RWS14 : XDMAC Channel 14 Read Write Suspend Bit
bits : 14 - 14 (1 bit)

RWS15 : XDMAC Channel 15 Read Write Suspend Bit
bits : 15 - 15 (1 bit)

RWS16 : XDMAC Channel 16 Read Write Suspend Bit
bits : 16 - 16 (1 bit)

RWS17 : XDMAC Channel 17 Read Write Suspend Bit
bits : 17 - 17 (1 bit)

RWS18 : XDMAC Channel 18 Read Write Suspend Bit
bits : 18 - 18 (1 bit)

RWS19 : XDMAC Channel 19 Read Write Suspend Bit
bits : 19 - 19 (1 bit)

RWS20 : XDMAC Channel 20 Read Write Suspend Bit
bits : 20 - 20 (1 bit)

RWS21 : XDMAC Channel 21 Read Write Suspend Bit
bits : 21 - 21 (1 bit)

RWS22 : XDMAC Channel 22 Read Write Suspend Bit
bits : 22 - 22 (1 bit)

RWS23 : XDMAC Channel 23 Read Write Suspend Bit
bits : 23 - 23 (1 bit)


CSUS

Channel Source Microblock Stride
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSUS CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CSUS10

Channel Source Microblock Stride (chid = 10)
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS10 CSUS10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS10

Channel Destination Microblock Stride (chid = 10)
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS10 CDUS10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x30B0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x30B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x30B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x30BC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x30C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x30C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x30C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x30CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x30D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x30D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x30D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x30DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x30E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x30E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CIE11

Channel Interrupt Enable Register (chid = 11)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE11 CIE11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID11

Channel Interrupt Disable Register (chid = 11)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID11 CID11 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM11

Channel Interrupt Mask Register (chid = 11)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM11 CIM11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS11

Channel Interrupt Status Register (chid = 11)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS11 CIS11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA11

Channel Source Address Register (chid = 11)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA11 CSA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA11

Channel Destination Address Register (chid = 11)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA11 CDA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA11

Channel Next Descriptor Address Register (chid = 11)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA11 CNDA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC11

Channel Next Descriptor Control Register (chid = 11)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC11 CNDC11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC11

Channel Microblock Control Register (chid = 11)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC11 CUBC11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC11

Channel Block Control Register (chid = 11)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC11 CBC11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC11

Channel Configuration Register (chid = 11)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC11 CC11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP11

Channel Data Stride Memory Set Pattern (chid = 11)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP11 CDS_MSP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GRWR

Global Channel Read Write Resume Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GRWR GRWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWR0 RWR1 RWR2 RWR3 RWR4 RWR5 RWR6 RWR7 RWR8 RWR9 RWR10 RWR11 RWR12 RWR13 RWR14 RWR15 RWR16 RWR17 RWR18 RWR19 RWR20 RWR21 RWR22 RWR23

RWR0 : XDMAC Channel 0 Read Write Resume Bit
bits : 0 - 0 (1 bit)

RWR1 : XDMAC Channel 1 Read Write Resume Bit
bits : 1 - 1 (1 bit)

RWR2 : XDMAC Channel 2 Read Write Resume Bit
bits : 2 - 2 (1 bit)

RWR3 : XDMAC Channel 3 Read Write Resume Bit
bits : 3 - 3 (1 bit)

RWR4 : XDMAC Channel 4 Read Write Resume Bit
bits : 4 - 4 (1 bit)

RWR5 : XDMAC Channel 5 Read Write Resume Bit
bits : 5 - 5 (1 bit)

RWR6 : XDMAC Channel 6 Read Write Resume Bit
bits : 6 - 6 (1 bit)

RWR7 : XDMAC Channel 7 Read Write Resume Bit
bits : 7 - 7 (1 bit)

RWR8 : XDMAC Channel 8 Read Write Resume Bit
bits : 8 - 8 (1 bit)

RWR9 : XDMAC Channel 9 Read Write Resume Bit
bits : 9 - 9 (1 bit)

RWR10 : XDMAC Channel 10 Read Write Resume Bit
bits : 10 - 10 (1 bit)

RWR11 : XDMAC Channel 11 Read Write Resume Bit
bits : 11 - 11 (1 bit)

RWR12 : XDMAC Channel 12 Read Write Resume Bit
bits : 12 - 12 (1 bit)

RWR13 : XDMAC Channel 13 Read Write Resume Bit
bits : 13 - 13 (1 bit)

RWR14 : XDMAC Channel 14 Read Write Resume Bit
bits : 14 - 14 (1 bit)

RWR15 : XDMAC Channel 15 Read Write Resume Bit
bits : 15 - 15 (1 bit)

RWR16 : XDMAC Channel 16 Read Write Resume Bit
bits : 16 - 16 (1 bit)

RWR17 : XDMAC Channel 17 Read Write Resume Bit
bits : 17 - 17 (1 bit)

RWR18 : XDMAC Channel 18 Read Write Resume Bit
bits : 18 - 18 (1 bit)

RWR19 : XDMAC Channel 19 Read Write Resume Bit
bits : 19 - 19 (1 bit)

RWR20 : XDMAC Channel 20 Read Write Resume Bit
bits : 20 - 20 (1 bit)

RWR21 : XDMAC Channel 21 Read Write Resume Bit
bits : 21 - 21 (1 bit)

RWR22 : XDMAC Channel 22 Read Write Resume Bit
bits : 22 - 22 (1 bit)

RWR23 : XDMAC Channel 23 Read Write Resume Bit
bits : 23 - 23 (1 bit)


CDUS

Channel Destination Microblock Stride
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDUS CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CSUS11

Channel Source Microblock Stride (chid = 11)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS11 CSUS11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS11

Channel Destination Microblock Stride (chid = 11)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS11 CDUS11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE12

Channel Interrupt Enable Register (chid = 12)
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE12 CIE12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID12

Channel Interrupt Disable Register (chid = 12)
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID12 CID12 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM12

Channel Interrupt Mask Register (chid = 12)
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM12 CIM12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS12

Channel Interrupt Status Register (chid = 12)
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS12 CIS12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x35C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x35C4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x35C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x35CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x35D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x35D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x35D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x35DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x35E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x35E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x35E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x35EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x35F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x35F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CSA12

Channel Source Address Register (chid = 12)
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA12 CSA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA12

Channel Destination Address Register (chid = 12)
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA12 CDA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA12

Channel Next Descriptor Address Register (chid = 12)
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA12 CNDA12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC12

Channel Next Descriptor Control Register (chid = 12)
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC12 CNDC12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC12

Channel Microblock Control Register (chid = 12)
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC12 CUBC12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC12

Channel Block Control Register (chid = 12)
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC12 CBC12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC12

Channel Configuration Register (chid = 12)
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC12 CC12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP12

Channel Data Stride Memory Set Pattern (chid = 12)
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP12 CDS_MSP12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GSWR

Global Channel Software Request Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GSWR GSWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWREQ0 SWREQ1 SWREQ2 SWREQ3 SWREQ4 SWREQ5 SWREQ6 SWREQ7 SWREQ8 SWREQ9 SWREQ10 SWREQ11 SWREQ12 SWREQ13 SWREQ14 SWREQ15 SWREQ16 SWREQ17 SWREQ18 SWREQ19 SWREQ20 SWREQ21 SWREQ22 SWREQ23

SWREQ0 : XDMAC Channel 0 Software Request Bit
bits : 0 - 0 (1 bit)

SWREQ1 : XDMAC Channel 1 Software Request Bit
bits : 1 - 1 (1 bit)

SWREQ2 : XDMAC Channel 2 Software Request Bit
bits : 2 - 2 (1 bit)

SWREQ3 : XDMAC Channel 3 Software Request Bit
bits : 3 - 3 (1 bit)

SWREQ4 : XDMAC Channel 4 Software Request Bit
bits : 4 - 4 (1 bit)

SWREQ5 : XDMAC Channel 5 Software Request Bit
bits : 5 - 5 (1 bit)

SWREQ6 : XDMAC Channel 6 Software Request Bit
bits : 6 - 6 (1 bit)

SWREQ7 : XDMAC Channel 7 Software Request Bit
bits : 7 - 7 (1 bit)

SWREQ8 : XDMAC Channel 8 Software Request Bit
bits : 8 - 8 (1 bit)

SWREQ9 : XDMAC Channel 9 Software Request Bit
bits : 9 - 9 (1 bit)

SWREQ10 : XDMAC Channel 10 Software Request Bit
bits : 10 - 10 (1 bit)

SWREQ11 : XDMAC Channel 11 Software Request Bit
bits : 11 - 11 (1 bit)

SWREQ12 : XDMAC Channel 12 Software Request Bit
bits : 12 - 12 (1 bit)

SWREQ13 : XDMAC Channel 13 Software Request Bit
bits : 13 - 13 (1 bit)

SWREQ14 : XDMAC Channel 14 Software Request Bit
bits : 14 - 14 (1 bit)

SWREQ15 : XDMAC Channel 15 Software Request Bit
bits : 15 - 15 (1 bit)

SWREQ16 : XDMAC Channel 16 Software Request Bit
bits : 16 - 16 (1 bit)

SWREQ17 : XDMAC Channel 17 Software Request Bit
bits : 17 - 17 (1 bit)

SWREQ18 : XDMAC Channel 18 Software Request Bit
bits : 18 - 18 (1 bit)

SWREQ19 : XDMAC Channel 19 Software Request Bit
bits : 19 - 19 (1 bit)

SWREQ20 : XDMAC Channel 20 Software Request Bit
bits : 20 - 20 (1 bit)

SWREQ21 : XDMAC Channel 21 Software Request Bit
bits : 21 - 21 (1 bit)

SWREQ22 : XDMAC Channel 22 Software Request Bit
bits : 22 - 22 (1 bit)

SWREQ23 : XDMAC Channel 23 Software Request Bit
bits : 23 - 23 (1 bit)


CSUS12

Channel Source Microblock Stride (chid = 12)
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS12 CSUS12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS12

Channel Destination Microblock Stride (chid = 12)
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS12 CDUS12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE13

Channel Interrupt Enable Register (chid = 13)
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE13 CIE13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID13

Channel Interrupt Disable Register (chid = 13)
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID13 CID13 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM13

Channel Interrupt Mask Register (chid = 13)
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM13 CIM13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS13

Channel Interrupt Status Register (chid = 13)
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS13 CIS13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA13

Channel Source Address Register (chid = 13)
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA13 CSA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA13

Channel Destination Address Register (chid = 13)
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA13 CDA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA13

Channel Next Descriptor Address Register (chid = 13)
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA13 CNDA13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC13

Channel Next Descriptor Control Register (chid = 13)
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC13 CNDC13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC13

Channel Microblock Control Register (chid = 13)
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC13 CUBC13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x3B10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x3B14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x3B18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x3B1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x3B20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x3B24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x3B28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x3B2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x3B30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x3B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x3B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x3B3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CBC13

Channel Block Control Register (chid = 13)
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC13 CBC13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x3B40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x3B44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CC13

Channel Configuration Register (chid = 13)
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC13 CC13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP13

Channel Data Stride Memory Set Pattern (chid = 13)
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP13 CDS_MSP13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GSWS

Global Channel Software Request Status Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GSWS GSWS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRS0 SWRS1 SWRS2 SWRS3 SWRS4 SWRS5 SWRS6 SWRS7 SWRS8 SWRS9 SWRS10 SWRS11 SWRS12 SWRS13 SWRS14 SWRS15 SWRS16 SWRS17 SWRS18 SWRS19 SWRS20 SWRS21 SWRS22 SWRS23

SWRS0 : XDMAC Channel 0 Software Request Status Bit
bits : 0 - 0 (1 bit)

SWRS1 : XDMAC Channel 1 Software Request Status Bit
bits : 1 - 1 (1 bit)

SWRS2 : XDMAC Channel 2 Software Request Status Bit
bits : 2 - 2 (1 bit)

SWRS3 : XDMAC Channel 3 Software Request Status Bit
bits : 3 - 3 (1 bit)

SWRS4 : XDMAC Channel 4 Software Request Status Bit
bits : 4 - 4 (1 bit)

SWRS5 : XDMAC Channel 5 Software Request Status Bit
bits : 5 - 5 (1 bit)

SWRS6 : XDMAC Channel 6 Software Request Status Bit
bits : 6 - 6 (1 bit)

SWRS7 : XDMAC Channel 7 Software Request Status Bit
bits : 7 - 7 (1 bit)

SWRS8 : XDMAC Channel 8 Software Request Status Bit
bits : 8 - 8 (1 bit)

SWRS9 : XDMAC Channel 9 Software Request Status Bit
bits : 9 - 9 (1 bit)

SWRS10 : XDMAC Channel 10 Software Request Status Bit
bits : 10 - 10 (1 bit)

SWRS11 : XDMAC Channel 11 Software Request Status Bit
bits : 11 - 11 (1 bit)

SWRS12 : XDMAC Channel 12 Software Request Status Bit
bits : 12 - 12 (1 bit)

SWRS13 : XDMAC Channel 13 Software Request Status Bit
bits : 13 - 13 (1 bit)

SWRS14 : XDMAC Channel 14 Software Request Status Bit
bits : 14 - 14 (1 bit)

SWRS15 : XDMAC Channel 15 Software Request Status Bit
bits : 15 - 15 (1 bit)

SWRS16 : XDMAC Channel 16 Software Request Status Bit
bits : 16 - 16 (1 bit)

SWRS17 : XDMAC Channel 17 Software Request Status Bit
bits : 17 - 17 (1 bit)

SWRS18 : XDMAC Channel 18 Software Request Status Bit
bits : 18 - 18 (1 bit)

SWRS19 : XDMAC Channel 19 Software Request Status Bit
bits : 19 - 19 (1 bit)

SWRS20 : XDMAC Channel 20 Software Request Status Bit
bits : 20 - 20 (1 bit)

SWRS21 : XDMAC Channel 21 Software Request Status Bit
bits : 21 - 21 (1 bit)

SWRS22 : XDMAC Channel 22 Software Request Status Bit
bits : 22 - 22 (1 bit)

SWRS23 : XDMAC Channel 23 Software Request Status Bit
bits : 23 - 23 (1 bit)


CSUS13

Channel Source Microblock Stride (chid = 13)
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS13 CSUS13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS13

Channel Destination Microblock Stride (chid = 13)
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS13 CDUS13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE14

Channel Interrupt Enable Register (chid = 14)
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE14 CIE14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID14

Channel Interrupt Disable Register (chid = 14)
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID14 CID14 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM14

Channel Interrupt Mask Register (chid = 14)
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM14 CIM14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS14

Channel Interrupt Status Register (chid = 14)
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS14 CIS14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA14

Channel Source Address Register (chid = 14)
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA14 CSA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA14

Channel Destination Address Register (chid = 14)
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA14 CDA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA14

Channel Next Descriptor Address Register (chid = 14)
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA14 CNDA14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC14

Channel Next Descriptor Control Register (chid = 14)
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC14 CNDC14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC14

Channel Microblock Control Register (chid = 14)
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC14 CUBC14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC14

Channel Block Control Register (chid = 14)
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC14 CBC14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC14

Channel Configuration Register (chid = 14)
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC14 CC14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP14

Channel Data Stride Memory Set Pattern (chid = 14)
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP14 CDS_MSP14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GCFG

Global Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCFG GCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CGDISREG CGDISPIPE CGDISFIFO CGDISIF BXKBEN

CGDISREG : Configuration Registers Clock Gating Disable
bits : 0 - 0 (1 bit)

CGDISPIPE : Pipeline Clock Gating Disable
bits : 1 - 1 (1 bit)

CGDISFIFO : FIFO Clock Gating Disable
bits : 2 - 2 (1 bit)

CGDISIF : Bus Interface Clock Gating Disable
bits : 3 - 3 (1 bit)

BXKBEN : Boundary X Kilobyte Enable
bits : 8 - 8 (1 bit)


CID

Channel Interrupt Disable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CID CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


GSWF

Global Channel Software Flush Request Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GSWF GSWF write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWF0 SWF1 SWF2 SWF3 SWF4 SWF5 SWF6 SWF7 SWF8 SWF9 SWF10 SWF11 SWF12 SWF13 SWF14 SWF15 SWF16 SWF17 SWF18 SWF19 SWF20 SWF21 SWF22 SWF23

SWF0 : XDMAC Channel 0 Software Flush Request Bit
bits : 0 - 0 (1 bit)

SWF1 : XDMAC Channel 1 Software Flush Request Bit
bits : 1 - 1 (1 bit)

SWF2 : XDMAC Channel 2 Software Flush Request Bit
bits : 2 - 2 (1 bit)

SWF3 : XDMAC Channel 3 Software Flush Request Bit
bits : 3 - 3 (1 bit)

SWF4 : XDMAC Channel 4 Software Flush Request Bit
bits : 4 - 4 (1 bit)

SWF5 : XDMAC Channel 5 Software Flush Request Bit
bits : 5 - 5 (1 bit)

SWF6 : XDMAC Channel 6 Software Flush Request Bit
bits : 6 - 6 (1 bit)

SWF7 : XDMAC Channel 7 Software Flush Request Bit
bits : 7 - 7 (1 bit)

SWF8 : XDMAC Channel 8 Software Flush Request Bit
bits : 8 - 8 (1 bit)

SWF9 : XDMAC Channel 9 Software Flush Request Bit
bits : 9 - 9 (1 bit)

SWF10 : XDMAC Channel 10 Software Flush Request Bit
bits : 10 - 10 (1 bit)

SWF11 : XDMAC Channel 11 Software Flush Request Bit
bits : 11 - 11 (1 bit)

SWF12 : XDMAC Channel 12 Software Flush Request Bit
bits : 12 - 12 (1 bit)

SWF13 : XDMAC Channel 13 Software Flush Request Bit
bits : 13 - 13 (1 bit)

SWF14 : XDMAC Channel 14 Software Flush Request Bit
bits : 14 - 14 (1 bit)

SWF15 : XDMAC Channel 15 Software Flush Request Bit
bits : 15 - 15 (1 bit)

SWF16 : XDMAC Channel 16 Software Flush Request Bit
bits : 16 - 16 (1 bit)

SWF17 : XDMAC Channel 17 Software Flush Request Bit
bits : 17 - 17 (1 bit)

SWF18 : XDMAC Channel 18 Software Flush Request Bit
bits : 18 - 18 (1 bit)

SWF19 : XDMAC Channel 19 Software Flush Request Bit
bits : 19 - 19 (1 bit)

SWF20 : XDMAC Channel 20 Software Flush Request Bit
bits : 20 - 20 (1 bit)

SWF21 : XDMAC Channel 21 Software Flush Request Bit
bits : 21 - 21 (1 bit)

SWF22 : XDMAC Channel 22 Software Flush Request Bit
bits : 22 - 22 (1 bit)

SWF23 : XDMAC Channel 23 Software Flush Request Bit
bits : 23 - 23 (1 bit)


CSUS14

Channel Source Microblock Stride (chid = 14)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS14 CSUS14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS14

Channel Destination Microblock Stride (chid = 14)
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS14 CDUS14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x40A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x40A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x40A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x40AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x40B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x40B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x40B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x40BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x40C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x40C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x40C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x40CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x40D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x40D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CIE15

Channel Interrupt Enable Register (chid = 15)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE15 CIE15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CID15

Channel Interrupt Disable Register (chid = 15)
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID15 CID15 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CIM15

Channel Interrupt Mask Register (chid = 15)
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM15 CIM15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CIS15

Channel Interrupt Status Register (chid = 15)
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS15 CIS15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CSA15

Channel Source Address Register (chid = 15)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA15 CSA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CDA15

Channel Destination Address Register (chid = 15)
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA15 CDA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CNDA15

Channel Next Descriptor Address Register (chid = 15)
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA15 CNDA15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CNDC15

Channel Next Descriptor Control Register (chid = 15)
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC15 CNDC15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CUBC15

Channel Microblock Control Register (chid = 15)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC15 CUBC15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CBC15

Channel Block Control Register (chid = 15)
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC15 CBC15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CC15

Channel Configuration Register (chid = 15)
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC15 CC15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CDS_MSP15

Channel Data Stride Memory Set Pattern (chid = 15)
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP15 CDS_MSP15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CSUS15

Channel Source Microblock Stride (chid = 15)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS15 CSUS15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CDUS15

Channel Destination Microblock Stride (chid = 15)
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS15 CDUS15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE16

Channel Interrupt Enable Register (chid = 16)
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE16 CIE16 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID16

Channel Interrupt Disable Register (chid = 16)
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID16 CID16 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM16

Channel Interrupt Mask Register (chid = 16)
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM16 CIM16 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS16

Channel Interrupt Status Register (chid = 16)
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS16 CIS16 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA16

Channel Source Address Register (chid = 16)
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA16 CSA16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA16

Channel Destination Address Register (chid = 16)
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA16 CDA16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x4670 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x4674 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x4678 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x467C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CNDA16

Channel Next Descriptor Address Register (chid = 16)
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA16 CNDA16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x4680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x4684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x4688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x468C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x4690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x4694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x4698 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x469C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x46A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x46A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CNDC16

Channel Next Descriptor Control Register (chid = 16)
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC16 CNDC16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC16

Channel Microblock Control Register (chid = 16)
address_offset : 0x470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC16 CUBC16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC16

Channel Block Control Register (chid = 16)
address_offset : 0x474 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC16 CBC16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC16

Channel Configuration Register (chid = 16)
address_offset : 0x478 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC16 CC16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP16

Channel Data Stride Memory Set Pattern (chid = 16)
address_offset : 0x47C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP16 CDS_MSP16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CSUS16

Channel Source Microblock Stride (chid = 16)
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS16 CSUS16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS16

Channel Destination Microblock Stride (chid = 16)
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS16 CDUS16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE17

Channel Interrupt Enable Register (chid = 17)
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE17 CIE17 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID17

Channel Interrupt Disable Register (chid = 17)
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID17 CID17 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM17

Channel Interrupt Mask Register (chid = 17)
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM17 CIM17 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS17

Channel Interrupt Status Register (chid = 17)
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS17 CIS17 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA17

Channel Source Address Register (chid = 17)
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA17 CSA17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA17

Channel Destination Address Register (chid = 17)
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA17 CDA17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA17

Channel Next Descriptor Address Register (chid = 17)
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA17 CNDA17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC17

Channel Next Descriptor Control Register (chid = 17)
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC17 CNDC17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC17

Channel Microblock Control Register (chid = 17)
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC17 CUBC17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC17

Channel Block Control Register (chid = 17)
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC17 CBC17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC17

Channel Configuration Register (chid = 17)
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC17 CC17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP17

Channel Data Stride Memory Set Pattern (chid = 17)
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP17 CDS_MSP17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CSUS17

Channel Source Microblock Stride (chid = 17)
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS17 CSUS17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS17

Channel Destination Microblock Stride (chid = 17)
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS17 CDUS17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x4C80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x4C84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x4C88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x4C8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x4C90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x4C94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x4C98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x4C9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x4CA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x4CA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x4CA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x4CAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x4CB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x4CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CIE18

Channel Interrupt Enable Register (chid = 18)
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE18 CIE18 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID18

Channel Interrupt Disable Register (chid = 18)
address_offset : 0x4D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID18 CID18 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM18

Channel Interrupt Mask Register (chid = 18)
address_offset : 0x4D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM18 CIM18 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS18

Channel Interrupt Status Register (chid = 18)
address_offset : 0x4DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS18 CIS18 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA18

Channel Source Address Register (chid = 18)
address_offset : 0x4E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA18 CSA18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA18

Channel Destination Address Register (chid = 18)
address_offset : 0x4E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA18 CDA18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA18

Channel Next Descriptor Address Register (chid = 18)
address_offset : 0x4E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA18 CNDA18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC18

Channel Next Descriptor Control Register (chid = 18)
address_offset : 0x4EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC18 CNDC18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC18

Channel Microblock Control Register (chid = 18)
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC18 CUBC18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC18

Channel Block Control Register (chid = 18)
address_offset : 0x4F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC18 CBC18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC18

Channel Configuration Register (chid = 18)
address_offset : 0x4F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC18 CC18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP18

Channel Data Stride Memory Set Pattern (chid = 18)
address_offset : 0x4FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP18 CDS_MSP18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CIE CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CIE0

Channel Interrupt Enable Register (chid = 0)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE0 CIE0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CSUS18

Channel Source Microblock Stride (chid = 18)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS18 CSUS18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS18

Channel Destination Microblock Stride (chid = 18)
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS18 CDUS18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE19

Channel Interrupt Enable Register (chid = 19)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE19 CIE19 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID19

Channel Interrupt Disable Register (chid = 19)
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID19 CID19 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM19

Channel Interrupt Mask Register (chid = 19)
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM19 CIM19 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS19

Channel Interrupt Status Register (chid = 19)
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS19 CIS19 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA19

Channel Source Address Register (chid = 19)
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA19 CSA19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA19

Channel Destination Address Register (chid = 19)
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA19 CDA19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA19

Channel Next Descriptor Address Register (chid = 19)
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA19 CNDA19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC19

Channel Next Descriptor Control Register (chid = 19)
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC19 CNDC19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC19

Channel Microblock Control Register (chid = 19)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC19 CUBC19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC19

Channel Block Control Register (chid = 19)
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC19 CBC19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC19

Channel Configuration Register (chid = 19)
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC19 CC19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP19

Channel Data Stride Memory Set Pattern (chid = 19)
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP19 CDS_MSP19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CID CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CID0

Channel Interrupt Disable Register (chid = 0)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID0 CID0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CSUS19

Channel Source Microblock Stride (chid = 19)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS19 CSUS19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS19

Channel Destination Microblock Stride (chid = 19)
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS19 CDUS19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE20

Channel Interrupt Enable Register (chid = 20)
address_offset : 0x550 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE20 CIE20 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID20

Channel Interrupt Disable Register (chid = 20)
address_offset : 0x554 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID20 CID20 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM20

Channel Interrupt Mask Register (chid = 20)
address_offset : 0x558 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM20 CIM20 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS20

Channel Interrupt Status Register (chid = 20)
address_offset : 0x55C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS20 CIS20 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA20

Channel Source Address Register (chid = 20)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA20 CSA20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA20

Channel Destination Address Register (chid = 20)
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA20 CDA20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA20

Channel Next Descriptor Address Register (chid = 20)
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA20 CNDA20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC20

Channel Next Descriptor Control Register (chid = 20)
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC20 CNDC20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC20

Channel Microblock Control Register (chid = 20)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC20 CUBC20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC20

Channel Block Control Register (chid = 20)
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC20 CBC20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC20

Channel Configuration Register (chid = 20)
address_offset : 0x578 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC20 CC20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP20

Channel Data Stride Memory Set Pattern (chid = 20)
address_offset : 0x57C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP20 CDS_MSP20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CIM CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CIM0

Channel Interrupt Mask Register (chid = 0)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM0 CIM0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CSUS20

Channel Source Microblock Stride (chid = 20)
address_offset : 0x580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS20 CSUS20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS20

Channel Destination Microblock Stride (chid = 20)
address_offset : 0x584 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS20 CDUS20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE21

Channel Interrupt Enable Register (chid = 21)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE21 CIE21 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID21

Channel Interrupt Disable Register (chid = 21)
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID21 CID21 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM21

Channel Interrupt Mask Register (chid = 21)
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM21 CIM21 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS21

Channel Interrupt Status Register (chid = 21)
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS21 CIS21 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CSA21

Channel Source Address Register (chid = 21)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA21 CSA21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CDA21

Channel Destination Address Register (chid = 21)
address_offset : 0x5A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA21 CDA21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CNDA21

Channel Next Descriptor Address Register (chid = 21)
address_offset : 0x5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA21 CNDA21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CNDC21

Channel Next Descriptor Control Register (chid = 21)
address_offset : 0x5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC21 CNDC21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CUBC21

Channel Microblock Control Register (chid = 21)
address_offset : 0x5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC21 CUBC21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CBC21

Channel Block Control Register (chid = 21)
address_offset : 0x5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC21 CBC21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CC21

Channel Configuration Register (chid = 21)
address_offset : 0x5B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC21 CC21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CDS_MSP21

Channel Data Stride Memory Set Pattern (chid = 21)
address_offset : 0x5BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP21 CDS_MSP21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CIS CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CIS0

Channel Interrupt Status Register (chid = 0)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS0 CIS0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CSUS21

Channel Source Microblock Stride (chid = 21)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS21 CSUS21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CDUS21

Channel Destination Microblock Stride (chid = 21)
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS21 CDUS21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CIE22

Channel Interrupt Enable Register (chid = 22)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE22 CIE22 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CID22

Channel Interrupt Disable Register (chid = 22)
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID22 CID22 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM22

Channel Interrupt Mask Register (chid = 22)
address_offset : 0x5D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM22 CIM22 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS22

Channel Interrupt Status Register (chid = 22)
address_offset : 0x5DC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS22 CIS22 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA22

Channel Source Address Register (chid = 22)
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA22 CSA22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA22

Channel Destination Address Register (chid = 22)
address_offset : 0x5E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA22 CDA22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA22

Channel Next Descriptor Address Register (chid = 22)
address_offset : 0x5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA22 CNDA22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC22

Channel Next Descriptor Control Register (chid = 22)
address_offset : 0x5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC22 CNDC22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC22

Channel Microblock Control Register (chid = 22)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC22 CUBC22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC22

Channel Block Control Register (chid = 22)
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC22 CBC22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC22

Channel Configuration Register (chid = 22)
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC22 CC22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP22

Channel Data Stride Memory Set Pattern (chid = 22)
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP22 CDS_MSP22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CSA CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CSA0

Channel Source Address Register (chid = 0)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA0 CSA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CSUS22

Channel Source Microblock Stride (chid = 22)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS22 CSUS22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS22

Channel Destination Microblock Stride (chid = 22)
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS22 CDUS22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE23

Channel Interrupt Enable Register (chid = 23)
address_offset : 0x610 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE23 CIE23 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID23

Channel Interrupt Disable Register (chid = 23)
address_offset : 0x614 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID23 CID23 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM23

Channel Interrupt Mask Register (chid = 23)
address_offset : 0x618 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM23 CIM23 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS23

Channel Interrupt Status Register (chid = 23)
address_offset : 0x61C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS23 CIS23 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA23

Channel Source Address Register (chid = 23)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA23 CSA23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA23

Channel Destination Address Register (chid = 23)
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA23 CDA23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA23

Channel Next Descriptor Address Register (chid = 23)
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA23 CNDA23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC23

Channel Next Descriptor Control Register (chid = 23)
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC23 CNDC23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC23

Channel Microblock Control Register (chid = 23)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC23 CUBC23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC23

Channel Block Control Register (chid = 23)
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC23 CBC23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC23

Channel Configuration Register (chid = 23)
address_offset : 0x638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC23 CC23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP23

Channel Data Stride Memory Set Pattern (chid = 23)
address_offset : 0x63C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP23 CDS_MSP23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CDA CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CDA0

Channel Destination Address Register (chid = 0)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA0 CDA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CSUS23

Channel Source Microblock Stride (chid = 23)
address_offset : 0x640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS23 CSUS23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CDUS23

Channel Destination Microblock Stride (chid = 23)
address_offset : 0x644 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS23 CDUS23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CNDA CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CNDA0

Channel Next Descriptor Address Register (chid = 0)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA0 CNDA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CNDC CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CNDC0

Channel Next Descriptor Control Register (chid = 0)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC0 CNDC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CUBC CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CUBC0

Channel Microblock Control Register (chid = 0)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC0 CUBC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CBC CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CBC0

Channel Block Control Register (chid = 0)
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC0 CBC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x770 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x774 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x778 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x77C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CC CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CC0

Channel Configuration Register (chid = 0)
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC0 CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x780 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x78C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x790 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x794 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x79C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x7A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x7A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CDS_MSP CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CDS_MSP0

Channel Data Stride Memory Set Pattern (chid = 0)
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP0 CDS_MSP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


GWAC

Global Weighted Arbiter Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GWAC GWAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PW0 PW1 PW2 PW3

PW0 : Pool Weight 0
bits : 0 - 3 (4 bit)

PW1 : Pool Weight 1
bits : 4 - 7 (4 bit)

PW2 : Pool Weight 2
bits : 8 - 11 (4 bit)

PW3 : Pool Weight 3
bits : 12 - 15 (4 bit)


CIM

Channel Interrupt Mask Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIM CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CSUS CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CSUS0

Channel Source Microblock Stride (chid = 0)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS0 CSUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[0]-XDMAC_CDUS CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CDUS0

Channel Destination Microblock Stride (chid = 0)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS0 CDUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE1

Channel Interrupt Enable Register (chid = 1)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE1 CIE1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID1

Channel Interrupt Disable Register (chid = 1)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID1 CID1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM1

Channel Interrupt Mask Register (chid = 1)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM1 CIM1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0x984 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0x98C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0x990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0x994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0x998 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0x99C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0x9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0x9AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0x9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0x9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CIS1

Channel Interrupt Status Register (chid = 1)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS1 CIS1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CSA1

Channel Source Address Register (chid = 1)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA1 CSA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CDA1

Channel Destination Address Register (chid = 1)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA1 CDA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CNDA1

Channel Next Descriptor Address Register (chid = 1)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA1 CNDA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CNDC1

Channel Next Descriptor Control Register (chid = 1)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC1 CNDC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CUBC1

Channel Microblock Control Register (chid = 1)
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC1 CUBC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CBC1

Channel Block Control Register (chid = 1)
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC1 CBC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CC1

Channel Configuration Register (chid = 1)
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC1 CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CDS_MSP1

Channel Data Stride Memory Set Pattern (chid = 1)
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP1 CDS_MSP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0xBD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0xBD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0xBD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0xBDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0xBE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0xBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0xBE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0xBEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0xBF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0xBF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0xBF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0xBFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


GIE

Global Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

GIE GIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IE0 IE1 IE2 IE3 IE4 IE5 IE6 IE7 IE8 IE9 IE10 IE11 IE12 IE13 IE14 IE15 IE16 IE17 IE18 IE19 IE20 IE21 IE22 IE23

IE0 : XDMAC Channel 0 Interrupt Enable Bit
bits : 0 - 0 (1 bit)

IE1 : XDMAC Channel 1 Interrupt Enable Bit
bits : 1 - 1 (1 bit)

IE2 : XDMAC Channel 2 Interrupt Enable Bit
bits : 2 - 2 (1 bit)

IE3 : XDMAC Channel 3 Interrupt Enable Bit
bits : 3 - 3 (1 bit)

IE4 : XDMAC Channel 4 Interrupt Enable Bit
bits : 4 - 4 (1 bit)

IE5 : XDMAC Channel 5 Interrupt Enable Bit
bits : 5 - 5 (1 bit)

IE6 : XDMAC Channel 6 Interrupt Enable Bit
bits : 6 - 6 (1 bit)

IE7 : XDMAC Channel 7 Interrupt Enable Bit
bits : 7 - 7 (1 bit)

IE8 : XDMAC Channel 8 Interrupt Enable Bit
bits : 8 - 8 (1 bit)

IE9 : XDMAC Channel 9 Interrupt Enable Bit
bits : 9 - 9 (1 bit)

IE10 : XDMAC Channel 10 Interrupt Enable Bit
bits : 10 - 10 (1 bit)

IE11 : XDMAC Channel 11 Interrupt Enable Bit
bits : 11 - 11 (1 bit)

IE12 : XDMAC Channel 12 Interrupt Enable Bit
bits : 12 - 12 (1 bit)

IE13 : XDMAC Channel 13 Interrupt Enable Bit
bits : 13 - 13 (1 bit)

IE14 : XDMAC Channel 14 Interrupt Enable Bit
bits : 14 - 14 (1 bit)

IE15 : XDMAC Channel 15 Interrupt Enable Bit
bits : 15 - 15 (1 bit)

IE16 : XDMAC Channel 16 Interrupt Enable Bit
bits : 16 - 16 (1 bit)

IE17 : XDMAC Channel 17 Interrupt Enable Bit
bits : 17 - 17 (1 bit)

IE18 : XDMAC Channel 18 Interrupt Enable Bit
bits : 18 - 18 (1 bit)

IE19 : XDMAC Channel 19 Interrupt Enable Bit
bits : 19 - 19 (1 bit)

IE20 : XDMAC Channel 20 Interrupt Enable Bit
bits : 20 - 20 (1 bit)

IE21 : XDMAC Channel 21 Interrupt Enable Bit
bits : 21 - 21 (1 bit)

IE22 : XDMAC Channel 22 Interrupt Enable Bit
bits : 22 - 22 (1 bit)

IE23 : XDMAC Channel 23 Interrupt Enable Bit
bits : 23 - 23 (1 bit)


CIS

Channel Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CIS CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CSUS1

Channel Source Microblock Stride (chid = 1)
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSUS1 CSUS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0xC00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CDUS1

Channel Destination Microblock Stride (chid = 1)
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDUS1 CDUS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)
access : read-write


CIE2

Channel Interrupt Enable Register (chid = 2)
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CIE2 CIE2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : write-only

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : write-only

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : write-only

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : write-only


CID2

Channel Interrupt Disable Register (chid = 2)
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

CID2 CID2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)
access : write-only

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)
access : write-only

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)
access : write-only

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)
access : write-only

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)
access : write-only

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)
access : write-only

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)
access : write-only


CIM2

Channel Interrupt Mask Register (chid = 2)
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIM2 CIM2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)
access : read-only

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)
access : read-only

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)
access : read-only

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)
access : read-only


CIS2

Channel Interrupt Status Register (chid = 2)
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

CIS2 CIS2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)
access : read-only

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)
access : read-only

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)
access : read-only

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)
access : read-only

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)
access : read-only

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)
access : read-only

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)
access : read-only


CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CSA2

Channel Source Address Register (chid = 2)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSA2 CSA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CDA2

Channel Destination Address Register (chid = 2)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDA2 CDA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)
access : read-write


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE

Channel Interrupt Enable Register
address_offset : 0xE60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIE LIE DIE FIE RBIE WBIE ROIE

BIE : End of Block Interrupt Enable Bit
bits : 0 - 0 (1 bit)

LIE : End of Linked List Interrupt Enable Bit
bits : 1 - 1 (1 bit)

DIE : End of Disable Interrupt Enable Bit
bits : 2 - 2 (1 bit)

FIE : End of Flush Interrupt Enable Bit
bits : 3 - 3 (1 bit)

RBIE : Read Bus Error Interrupt Enable Bit
bits : 4 - 4 (1 bit)

WBIE : Write Bus Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)

ROIE : Request Overflow Error Interrupt Enable Bit
bits : 6 - 6 (1 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID

Channel Interrupt Disable Register
address_offset : 0xE64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BID LID DID FID RBEID WBEID ROID

BID : End of Block Interrupt Disable Bit
bits : 0 - 0 (1 bit)

LID : End of Linked List Interrupt Disable Bit
bits : 1 - 1 (1 bit)

DID : End of Disable Interrupt Disable Bit
bits : 2 - 2 (1 bit)

FID : End of Flush Interrupt Disable Bit
bits : 3 - 3 (1 bit)

RBEID : Read Bus Error Interrupt Disable Bit
bits : 4 - 4 (1 bit)

WBEID : Write Bus Error Interrupt Disable Bit
bits : 5 - 5 (1 bit)

ROID : Request Overflow Error Interrupt Disable Bit
bits : 6 - 6 (1 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0xE68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0xE6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0xE70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0xE74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0xE78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0xE7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[1]-XDMAC_CHID[0]-XDMAC_CIM

Channel Interrupt Mask Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CIM CHID[1]-XDMAC_CHID[0]-XDMAC_CIM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIM LIM DIM FIM RBEIM WBEIM ROIM

BIM : End of Block Interrupt Mask Bit
bits : 0 - 0 (1 bit)

LIM : End of Linked List Interrupt Mask Bit
bits : 1 - 1 (1 bit)

DIM : End of Disable Interrupt Mask Bit
bits : 2 - 2 (1 bit)

FIM : End of Flush Interrupt Mask Bit
bits : 3 - 3 (1 bit)

RBEIM : Read Bus Error Interrupt Mask Bit
bits : 4 - 4 (1 bit)

WBEIM : Write Bus Error Interrupt Mask Bit
bits : 5 - 5 (1 bit)

ROIM : Request Overflow Error Interrupt Mask Bit
bits : 6 - 6 (1 bit)


CNDA2

Channel Next Descriptor Address Register (chid = 2)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDA2 CNDA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)
access : read-write

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)
access : read-write


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC

Channel Microblock Control Register
address_offset : 0xE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC

Channel Block Control Register
address_offset : 0xE84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC

Channel Configuration Register
address_offset : 0xE88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)

Enumeration: TYPESelect

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)

Enumeration: MBSIZESelect

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)

Enumeration: DSYNCSelect

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)

Enumeration: SWREQSelect

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of memory
bits : 7 - 7 (1 bit)

Enumeration: MEMSETSelect

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)

Enumeration: CSIZESelect

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)

Enumeration: DWIDTHSelect

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)

Enumeration: SIFSelect

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)

Enumeration: DIFSelect

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)

Enumeration: SAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)

Enumeration: DAMSelect

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary; the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Terminated (this bit is read-only)
bits : 21 - 21 (1 bit)

Enumeration: INITDSelect

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)

Enumeration: RDIPSelect

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)

Enumeration: WRIPSelect

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)

Enumeration: PERIDSelect

0 : HSMCI

HSMCI

1 : SPI0_TX

SPI0_TX

2 : SPI0_RX

SPI0_RX

5 : QSPI_TX

QSPI_TX

6 : QSPI_RX

QSPI_RX

7 : USART0_TX

USART0_TX

8 : USART0_RX

USART0_RX

9 : USART1_TX

USART1_TX

10 : USART1_RX

USART1_RX

11 : USART2_TX

USART2_TX

12 : USART2_RX

USART2_RX

13 : PWM0

PWM0

14 : TWIHS0_TX

TWIHS0_TX

15 : TWIHS0_RX

TWIHS0_RX

16 : TWIHS1_TX

TWIHS1_TX

17 : TWIHS1_RX

TWIHS1_RX

18 : TWIHS2_TX

TWIHS2_TX

19 : TWIHS2_RX

TWIHS2_RX

20 : UART0_TX

UART0_TX

21 : UART0_RX

UART0_RX

22 : UART1_TX

UART1_TX

23 : UART1_RX

UART1_RX

24 : UART2_TX

UART2_TX

25 : UART2_RX

UART2_RX

26 : UART3_TX

UART3_TX

27 : UART3_RX

UART3_RX

28 : UART4_TX

UART4_TX

29 : UART4_RX

UART4_RX

30 : DACC0

DACC0

31 : DACC1

DACC1

32 : SSC_TX

SSC_TX

33 : SSC_RX

SSC_RX

34 : PIOA

PIOA

35 : AFEC0

AFEC0

36 : AFEC1

AFEC1

37 : AES_TX

AES_TX

38 : AES_RX

AES_RX

39 : PWM1

PWM1

40 : TC0

TC0

41 : TC3

TC3

42 : TC6

TC6

43 : TC9

TC9

44 : I2SC0_TX_LEFT

I2SC0_TX_LEFT

45 : I2SC0_RX_LEFT

I2SC0_RX_LEFT

48 : I2SC0_TX_RIGHT

I2SC0_TX_RIGHT

49 : I2SC0_RX_RIGHT

I2SC0_RX_RIGHT

End of enumeration elements list.


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP

Channel Data Stride Memory Set Pattern
address_offset : 0xE8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS

Channel Source Microblock Stride
address_offset : 0xE90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUBS

SUBS : Channel x Source Microblock Stride
bits : 0 - 23 (24 bit)


CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS

Channel Destination Microblock Stride
address_offset : 0xE94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DUBS

DUBS : Channel x Destination Microblock Stride
bits : 0 - 23 (24 bit)


CHID[1]-XDMAC_CHID[0]-XDMAC_CIS

Channel Interrupt Status Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CIS CHID[1]-XDMAC_CHID[0]-XDMAC_CIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIS LIS DIS FIS RBEIS WBEIS ROIS

BIS : End of Block Interrupt Status Bit
bits : 0 - 0 (1 bit)

LIS : End of Linked List Interrupt Status Bit
bits : 1 - 1 (1 bit)

DIS : End of Disable Interrupt Status Bit
bits : 2 - 2 (1 bit)

FIS : End of Flush Interrupt Status Bit
bits : 3 - 3 (1 bit)

RBEIS : Read Bus Error Interrupt Status Bit
bits : 4 - 4 (1 bit)

WBEIS : Write Bus Error Interrupt Status Bit
bits : 5 - 5 (1 bit)

ROIS : Request Overflow Error Interrupt Status Bit
bits : 6 - 6 (1 bit)


CNDC2

Channel Next Descriptor Control Register (chid = 2)
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CNDC2 CNDC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CHID[1]-XDMAC_CHID[0]-XDMAC_CSA

Channel Source Address Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CSA CHID[1]-XDMAC_CHID[0]-XDMAC_CSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SA

SA : Channel x Source Address
bits : 0 - 31 (32 bit)


CUBC2

Channel Microblock Control Register (chid = 2)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CUBC2 CUBC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBLEN

UBLEN : Channel x Microblock Length
bits : 0 - 23 (24 bit)
access : read-write


CHID[1]-XDMAC_CHID[0]-XDMAC_CDA

Channel Destination Address Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CDA CHID[1]-XDMAC_CHID[0]-XDMAC_CDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DA

DA : Channel x Destination Address
bits : 0 - 31 (32 bit)


CBC2

Channel Block Control Register (chid = 2)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CBC2 CBC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLEN

BLEN : Channel x Block Length
bits : 0 - 11 (12 bit)
access : read-write


CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA

Channel Next Descriptor Address Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDAIF NDA

NDAIF : Channel x Next Descriptor Interface
bits : 0 - 0 (1 bit)

NDA : Channel x Next Descriptor Address
bits : 2 - 31 (30 bit)


CC2

Channel Configuration Register (chid = 2)
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CC2 CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE MBSIZE DSYNC SWREQ MEMSET CSIZE DWIDTH SIF DIF SAM DAM INITD RDIP WRIP PERID

TYPE : Channel x Transfer Type
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : MEM_TRAN

Self-triggered mode (memory-to-memory transfer).

1 : PER_TRAN

Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer).

End of enumeration elements list.

MBSIZE : Channel x Memory Burst Size
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x0 : SINGLE

The memory burst size is set to one.

0x1 : FOUR

The memory burst size is set to four.

0x2 : EIGHT

The memory burst size is set to eight.

0x3 : SIXTEEN

The memory burst size is set to sixteen.

End of enumeration elements list.

DSYNC : Channel x Synchronization
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : PER2MEM

Peripheral-to-memory transfer.

1 : MEM2PER

Memory-to-peripheral transfer.

End of enumeration elements list.

SWREQ : Channel x Software Request Trigger
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : HWR_CONNECTED

Hardware request line is connected to the peripheral request line.

1 : SWR_CONNECTED

Software request is connected to the peripheral request line.

End of enumeration elements list.

MEMSET : Channel x Fill Block of Memory
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL_MODE

Memset is not activated.

1 : HW_MODE

Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis.

End of enumeration elements list.

CSIZE : Channel x Chunk Size
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x0 : CHK_1

1 data transferred

0x1 : CHK_2

2 data transferred

0x2 : CHK_4

4 data transferred

0x3 : CHK_8

8 data transferred

0x4 : CHK_16

16 data transferred

End of enumeration elements list.

DWIDTH : Channel x Data Width
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : BYTE

The data size is set to 8 bits

0x1 : HALFWORD

The data size is set to 16 bits

0x2 : WORD

The data size is set to 32 bits

End of enumeration elements list.

SIF : Channel x Source Interface Identifier
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is read through the system bus interface 0.

1 : AHB_IF1

The data is read through the system bus interface 1.

End of enumeration elements list.

DIF : Channel x Destination Interface Identifier
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : AHB_IF0

The data is written through the system bus interface 0.

1 : AHB_IF1

The data is written though the system bus interface 1.

End of enumeration elements list.

SAM : Channel x Source Addressing Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary, the data stride is added at the data boundary.

End of enumeration elements list.

DAM : Channel x Destination Addressing Mode
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x0 : FIXED_AM

The address remains unchanged.

0x1 : INCREMENTED_AM

The addressing mode is incremented (the increment size is set to the data size).

0x2 : UBS_AM

The microblock stride is added at the microblock boundary.

0x3 : UBS_DS_AM

The microblock stride is added at the microblock boundary the data stride is added at the data boundary.

End of enumeration elements list.

INITD : Channel Initialization Done (this bit is read-only)
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : IN_PROGRESS

Channel initialization is in progress.

1 : TERMINATED

Channel initialization is completed.

End of enumeration elements list.

RDIP : Read in Progress (this bit is read-only)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active read transaction on the bus.

1 : IN_PROGRESS

A read transaction is in progress.

End of enumeration elements list.

WRIP : Write in Progress (this bit is read-only)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DONE

No active write transaction on the bus.

1 : IN_PROGRESS

A write transaction is in progress.

End of enumeration elements list.

PERID : Channel x Peripheral Hardware Request Line Identifier
bits : 24 - 30 (7 bit)
access : read-write


CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC

Channel Next Descriptor Control Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NDE NDSUP NDDUP NDVIEW

NDE : Channel x Next Descriptor Enable
bits : 0 - 0 (1 bit)

Enumeration: NDESelect

0 : DSCR_FETCH_DIS

Descriptor fetch is disabled.

1 : DSCR_FETCH_EN

Descriptor fetch is enabled.

End of enumeration elements list.

NDSUP : Channel x Next Descriptor Source Update
bits : 1 - 1 (1 bit)

Enumeration: NDSUPSelect

0 : SRC_PARAMS_UNCHANGED

Source parameters remain unchanged.

1 : SRC_PARAMS_UPDATED

Source parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDDUP : Channel x Next Descriptor Destination Update
bits : 2 - 2 (1 bit)

Enumeration: NDDUPSelect

0 : DST_PARAMS_UNCHANGED

Destination parameters remain unchanged.

1 : DST_PARAMS_UPDATED

Destination parameters are updated when the descriptor is retrieved.

End of enumeration elements list.

NDVIEW : Channel x Next Descriptor View
bits : 3 - 4 (2 bit)

Enumeration: NDVIEWSelect

0x0 : NDV0

Next Descriptor View 0

0x1 : NDV1

Next Descriptor View 1

0x2 : NDV2

Next Descriptor View 2

0x3 : NDV3

Next Descriptor View 3

End of enumeration elements list.


CDS_MSP2

Channel Data Stride Memory Set Pattern (chid = 2)
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CDS_MSP2 CDS_MSP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDS_MSP DDS_MSP

SDS_MSP : Channel x Source Data stride or Memory Set Pattern
bits : 0 - 15 (16 bit)
access : read-write

DDS_MSP : Channel x Destination Data Stride or Memory Set Pattern
bits : 16 - 31 (16 bit)
access : read-write


VERSION

XDMAC Version Register
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

VERSION VERSION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION MFN

VERSION : Version of the Hardware Module
bits : 0 - 11 (12 bit)
access : read-write

MFN : Metal Fix Number
bits : 16 - 18 (3 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.