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AES

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

IER

IDATAR[2]

TAGR[0]

KEYWR[5]

IVR[1]

GCMHR[0]

IDR

ODATAR[2]

KEYWR[6]

IDATAR[3]

GHASHR[1]

IMR

IVR[2]

KEYWR[7]

TAGR[1]

ODATAR[3]

ISR

GCMHR[1]

GHASHR[2]

IVR[3]

KEYWR0

TAGR[2]

KEYWR1

GHASHR[3]

GCMHR[2]

KEYWR2

KEYWR3

TAGR[3]

KEYWR4

GCMHR[3]

KEYWR5

KEYWR6

KEYWR7

MR

KEYWR[0]

IDATAR0

IDATAR1

IDATAR2

IDATAR3

ODATAR0

ODATAR1

ODATAR2

ODATAR3

IVR0

KEYWR[1]

IVR1

IVR2

IVR3

AADLENR

CLENR

GHASHR0

GHASHR1

IDATAR[0]

GHASHR2

GHASHR3

TAGR0

KEYWR[2]

TAGR1

TAGR2

TAGR3

CTRR

GCMHR0

ODATAR[0]

GCMHR1

GCMHR2

GCMHR3

KEYWR[3]

IVR[0]

IDATAR[1]

KEYWR[4]

GHASHR[0]

ODATAR[1]

VERSION


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START SWRST LOADSEED

START : Start Processing
bits : 0 - 0 (1 bit)

SWRST : Software Reset
bits : 8 - 8 (1 bit)

LOADSEED : Random Number Generator Seed Loading
bits : 16 - 16 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATRDY URAD TAGRDY

DATRDY : Data Ready Interrupt Enable
bits : 0 - 0 (1 bit)

URAD : Unspecified Register Access Detection Interrupt Enable
bits : 8 - 8 (1 bit)

TAGRDY : GCM Tag Ready Interrupt Enable
bits : 16 - 16 (1 bit)


IDATAR[2]

Input Data Register 0
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR[2] IDATAR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)


TAGR[0]

GCM Authentication Tag Word Register 0
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAGR[0] TAGR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)


KEYWR[5]

Key Word Register 0
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[5] KEYWR[5] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


IVR[1]

Initialization Vector Register 0
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR[1] IVR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)


GCMHR[0]

GCM H Word Register 0
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCMHR[0] GCMHR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H

H : GCM H Word x
bits : 0 - 31 (32 bit)


IDR

Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATRDY URAD TAGRDY

DATRDY : Data Ready Interrupt Disable
bits : 0 - 0 (1 bit)

URAD : Unspecified Register Access Detection Interrupt Disable
bits : 8 - 8 (1 bit)

TAGRDY : GCM Tag Ready Interrupt Disable
bits : 16 - 16 (1 bit)


ODATAR[2]

Output Data Register 0
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR[2] ODATAR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)


KEYWR[6]

Key Word Register 0
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[6] KEYWR[6] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


IDATAR[3]

Input Data Register 0
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR[3] IDATAR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)


GHASHR[1]

GCM Intermediate Hash Word Register 0
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GHASHR[1] GHASHR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GHASH

GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)


IMR

Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATRDY URAD TAGRDY

DATRDY : Data Ready Interrupt Mask
bits : 0 - 0 (1 bit)

URAD : Unspecified Register Access Detection Interrupt Mask
bits : 8 - 8 (1 bit)

TAGRDY : GCM Tag Ready Interrupt Mask
bits : 16 - 16 (1 bit)


IVR[2]

Initialization Vector Register 0
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR[2] IVR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)


KEYWR[7]

Key Word Register 0
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[7] KEYWR[7] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


TAGR[1]

GCM Authentication Tag Word Register 0
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAGR[1] TAGR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)


ODATAR[3]

Output Data Register 0
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR[3] ODATAR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)


ISR

Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATRDY URAD URAT TAGRDY

DATRDY : Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)
bits : 0 - 0 (1 bit)

URAD : Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)
bits : 8 - 8 (1 bit)

URAT : Unspecified Register Access (cleared by writing SWRST in AES_CR)
bits : 12 - 15 (4 bit)

Enumeration: URATSelect

0x0 : IDR_WR_PROCESSING

Input Data register written during the data processing when SMOD = 0x2 mode.

0x1 : ODR_RD_PROCESSING

Output Data register read during the data processing.

0x2 : MR_WR_PROCESSING

Mode register written during the data processing.

0x3 : ODR_RD_SUBKGEN

Output Data register read during the sub-keys generation.

0x4 : MR_WR_SUBKGEN

Mode register written during the sub-keys generation.

0x5 : WOR_RD_ACCESS

Write-only register read access.

End of enumeration elements list.

TAGRDY : GCM Tag Ready
bits : 16 - 16 (1 bit)


GCMHR[1]

GCM H Word Register 0
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCMHR[1] GCMHR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H

H : GCM H Word x
bits : 0 - 31 (32 bit)


GHASHR[2]

GCM Intermediate Hash Word Register 0
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GHASHR[2] GHASHR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GHASH

GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)


IVR[3]

Initialization Vector Register 0
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR[3] IVR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)


KEYWR0

Key Word Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR0 KEYWR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


TAGR[2]

GCM Authentication Tag Word Register 0
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAGR[2] TAGR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)


KEYWR1

Key Word Register 0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR1 KEYWR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


GHASHR[3]

GCM Intermediate Hash Word Register 0
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GHASHR[3] GHASHR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GHASH

GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)


GCMHR[2]

GCM H Word Register 0
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCMHR[2] GCMHR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H

H : GCM H Word x
bits : 0 - 31 (32 bit)


KEYWR2

Key Word Register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR2 KEYWR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


KEYWR3

Key Word Register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR3 KEYWR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


TAGR[3]

GCM Authentication Tag Word Register 0
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAGR[3] TAGR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)


KEYWR4

Key Word Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR4 KEYWR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


GCMHR[3]

GCM H Word Register 0
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCMHR[3] GCMHR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H

H : GCM H Word x
bits : 0 - 31 (32 bit)


KEYWR5

Key Word Register 0
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR5 KEYWR5 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


KEYWR6

Key Word Register 0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR6 KEYWR6 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


KEYWR7

Key Word Register 0
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR7 KEYWR7 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIPHER GTAGEN DUALBUFF PROCDLY SMOD KEYSIZE OPMOD LOD CFBS CKEY CMTYP1 CMTYP2 CMTYP3 CMTYP4 CMTYP5 CMTYP6

CIPHER : Processing Mode
bits : 0 - 0 (1 bit)

GTAGEN : GCM Automatic Tag Generation Enable
bits : 1 - 1 (1 bit)

DUALBUFF : Dual Input Buffer
bits : 3 - 3 (1 bit)

Enumeration: DUALBUFFSelect

0 : INACTIVE

AES_IDATARx cannot be written during processing of previous block.

1 : ACTIVE

AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files.

End of enumeration elements list.

PROCDLY : Processing Delay
bits : 4 - 7 (4 bit)

SMOD : Start Mode
bits : 8 - 9 (2 bit)

Enumeration: SMODSelect

0x0 : MANUAL_START

Manual Mode

0x1 : AUTO_START

Auto Mode

0x2 : IDATAR0_START

AES_IDATAR0 access only Auto Mode (DMA)

End of enumeration elements list.

KEYSIZE : Key Size
bits : 10 - 11 (2 bit)

Enumeration: KEYSIZESelect

0x0 : AES128

AES Key Size is 128 bits

0x1 : AES192

AES Key Size is 192 bits

0x2 : AES256

AES Key Size is 256 bits

End of enumeration elements list.

OPMOD : Operating Mode
bits : 12 - 14 (3 bit)

Enumeration: OPMODSelect

0x0 : ECB

ECB: Electronic Code Book mode

0x1 : CBC

CBC: Cipher Block Chaining mode

0x2 : OFB

OFB: Output Feedback mode

0x3 : CFB

CFB: Cipher Feedback mode

0x4 : CTR

CTR: Counter mode (16-bit internal counter)

0x5 : GCM

GCM: Galois/Counter mode

End of enumeration elements list.

LOD : Last Output Data Mode
bits : 15 - 15 (1 bit)

CFBS : Cipher Feedback Data Size
bits : 16 - 18 (3 bit)

Enumeration: CFBSSelect

0x0 : SIZE_128BIT

128-bit

0x1 : SIZE_64BIT

64-bit

0x2 : SIZE_32BIT

32-bit

0x3 : SIZE_16BIT

16-bit

0x4 : SIZE_8BIT

8-bit

End of enumeration elements list.

CKEY : Countermeasure Key
bits : 20 - 23 (4 bit)

Enumeration: CKEYSelect

0xE : PASSWD

This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0.

End of enumeration elements list.

CMTYP1 : Countermeasure Type 1
bits : 24 - 24 (1 bit)

Enumeration: CMTYP1Select

0 : NOPROT_EXTKEY

Countermeasure type 1 is disabled.

1 : PROT_EXTKEY

Countermeasure type 1 is enabled.

End of enumeration elements list.

CMTYP2 : Countermeasure Type 2
bits : 25 - 25 (1 bit)

Enumeration: CMTYP2Select

0 : NO_PAUSE

Countermeasure type 2 is disabled.

1 : PAUSE

Countermeasure type 2 is enabled.

End of enumeration elements list.

CMTYP3 : Countermeasure Type 3
bits : 26 - 26 (1 bit)

Enumeration: CMTYP3Select

0 : NO_DUMMY

Countermeasure type 3 is disabled.

1 : DUMMY

Countermeasure type 3 is enabled.

End of enumeration elements list.

CMTYP4 : Countermeasure Type 4
bits : 27 - 27 (1 bit)

Enumeration: CMTYP4Select

0 : NO_RESTART

Countermeasure type 4 is disabled.

1 : RESTART

Countermeasure type 4 is enabled.

End of enumeration elements list.

CMTYP5 : Countermeasure Type 5
bits : 28 - 28 (1 bit)

Enumeration: CMTYP5Select

0 : NO_ADDACCESS

Countermeasure type 5 is disabled.

1 : ADDACCESS

Countermeasure type 5 is enabled.

End of enumeration elements list.

CMTYP6 : Countermeasure Type 6
bits : 29 - 29 (1 bit)

Enumeration: CMTYP6Select

0 : NO_IDLECURRENT

Countermeasure type 6 is disabled.

1 : IDLECURRENT

Countermeasure type 6 is enabled.

End of enumeration elements list.


KEYWR[0]

Key Word Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[0] KEYWR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


IDATAR0

Input Data Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR0 IDATAR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)


IDATAR1

Input Data Register 0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR1 IDATAR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)


IDATAR2

Input Data Register 0
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR2 IDATAR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)


IDATAR3

Input Data Register 0
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR3 IDATAR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)


ODATAR0

Output Data Register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR0 ODATAR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)


ODATAR1

Output Data Register 0
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR1 ODATAR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)


ODATAR2

Output Data Register 0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR2 ODATAR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)


ODATAR3

Output Data Register 0
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR3 ODATAR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)


IVR0

Initialization Vector Register 0
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR0 IVR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)


KEYWR[1]

Key Word Register 0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[1] KEYWR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


IVR1

Initialization Vector Register 0
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR1 IVR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)


IVR2

Initialization Vector Register 0
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR2 IVR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)


IVR3

Initialization Vector Register 0
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR3 IVR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)


AADLENR

Additional Authenticated Data Length Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AADLENR AADLENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AADLEN

AADLEN : Additional Authenticated Data Length
bits : 0 - 31 (32 bit)


CLENR

Plaintext/Ciphertext Length Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLENR CLENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLEN

CLEN : Plaintext/Ciphertext Length
bits : 0 - 31 (32 bit)


GHASHR0

GCM Intermediate Hash Word Register 0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GHASHR0 GHASHR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GHASH

GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)


GHASHR1

GCM Intermediate Hash Word Register 0
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GHASHR1 GHASHR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GHASH

GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)


IDATAR[0]

Input Data Register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR[0] IDATAR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)


GHASHR2

GCM Intermediate Hash Word Register 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GHASHR2 GHASHR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GHASH

GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)


GHASHR3

GCM Intermediate Hash Word Register 0
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GHASHR3 GHASHR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GHASH

GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)


TAGR0

GCM Authentication Tag Word Register 0
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAGR0 TAGR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)


KEYWR[2]

Key Word Register 0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[2] KEYWR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


TAGR1

GCM Authentication Tag Word Register 0
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAGR1 TAGR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)


TAGR2

GCM Authentication Tag Word Register 0
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAGR2 TAGR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)


TAGR3

GCM Authentication Tag Word Register 0
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TAGR3 TAGR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)


CTRR

GCM Encryption Counter Value Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTRR CTRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTR

CTR : GCM Encryption Counter
bits : 0 - 31 (32 bit)


GCMHR0

GCM H Word Register 0
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCMHR0 GCMHR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H

H : GCM H Word x
bits : 0 - 31 (32 bit)


ODATAR[0]

Output Data Register 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR[0] ODATAR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)


GCMHR1

GCM H Word Register 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCMHR1 GCMHR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H

H : GCM H Word x
bits : 0 - 31 (32 bit)


GCMHR2

GCM H Word Register 0
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCMHR2 GCMHR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H

H : GCM H Word x
bits : 0 - 31 (32 bit)


GCMHR3

GCM H Word Register 0
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCMHR3 GCMHR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H

H : GCM H Word x
bits : 0 - 31 (32 bit)


KEYWR[3]

Key Word Register 0
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[3] KEYWR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


IVR[0]

Initialization Vector Register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IVR[0] IVR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : Initialization Vector
bits : 0 - 31 (32 bit)


IDATAR[1]

Input Data Register 0
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDATAR[1] IDATAR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDATA

IDATA : Input Data Word
bits : 0 - 31 (32 bit)


KEYWR[4]

Key Word Register 0
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYWR[4] KEYWR[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYW

KEYW : Key Word
bits : 0 - 31 (32 bit)


GHASHR[0]

GCM Intermediate Hash Word Register 0
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GHASHR[0] GHASHR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GHASH

GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)


ODATAR[1]

Output Data Register 0
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ODATAR[1] ODATAR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ODATA

ODATA : Output Data
bits : 0 - 31 (32 bit)


VERSION

Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION MFN

VERSION : Version of the Hardware Module
bits : 0 - 11 (12 bit)

MFN : Metal Fix Number
bits : 16 - 18 (3 bit)



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