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EFC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xE8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EEFC_FMR

FMR

EEFC_VERSION

VERSION

EEFC_FCR

FCR

EEFC_FSR

FSR

EEFC_FRR

FRR

EEFC_WPMR

WPMR


EEFC_FMR

EEFC Flash Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EEFC_FMR EEFC_FMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRDY FWS SCOD CLOE

FRDY : Flash Ready Interrupt Enable
bits : 0 - 0 (1 bit)

FWS : Flash Wait State
bits : 8 - 11 (4 bit)

SCOD : Sequential Code Optimization Disable
bits : 16 - 16 (1 bit)

CLOE : Code Loop Optimization Enable
bits : 26 - 26 (1 bit)


FMR

EEFC Flash Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

FMR FMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRDY FWS SCOD CLOE

FRDY : Flash Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

FWS : Flash Wait State
bits : 8 - 11 (4 bit)
access : read-write

SCOD : Sequential Code Optimization Disable
bits : 16 - 16 (1 bit)
access : read-write

CLOE : Code Loop Optimization Enable
bits : 26 - 26 (1 bit)
access : read-write


EEFC_VERSION

EEFC Version Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EEFC_VERSION EEFC_VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION MFN

VERSION : Version of the Hardware Module
bits : 0 - 11 (12 bit)

MFN : Metal Fix Number
bits : 16 - 18 (3 bit)


VERSION

EEFC Version Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION MFN

VERSION : Version of the Hardware Module
bits : 0 - 11 (12 bit)
access : read-only

MFN : Metal Fix Number
bits : 16 - 18 (3 bit)
access : read-only


EEFC_FCR

EEFC Flash Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EEFC_FCR EEFC_FCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCMD FARG FKEY

FCMD : Flash Command
bits : 0 - 7 (8 bit)

Enumeration: FCMDSelect

0x00 : GETD

Get Flash descriptor

0x01 : WP

Write page

0x02 : WPL

Write page and lock

0x03 : EWP

Erase page and write page

0x04 : EWPL

Erase page and write page then lock

0x05 : EA

Erase all

0x07 : EPA

Erase pages

0x08 : SLB

Set lock bit

0x09 : CLB

Clear lock bit

0x0A : GLB

Get lock bit

0x0B : SGPB

Set GPNVM bit

0x0C : CGPB

Clear GPNVM bit

0x0D : GGPB

Get GPNVM bit

0x0E : STUI

Start read unique identifier

0x0F : SPUI

Stop read unique identifier

0x10 : GCALB

Get CALIB bit

0x11 : ES

Erase sector

0x12 : WUS

Write user signature

0x13 : EUS

Erase user signature

0x14 : STUS

Start read user signature

0x15 : SPUS

Stop read user signature

End of enumeration elements list.

FARG : Flash Command Argument
bits : 8 - 23 (16 bit)

FKEY : Flash Writing Protection Key
bits : 24 - 31 (8 bit)

Enumeration: FKEYSelect

0x5A : PASSWD

The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.

End of enumeration elements list.


FCR

EEFC Flash Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

FCR FCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCMD FARG FKEY

FCMD : Flash Command
bits : 0 - 7 (8 bit)
access : write-only

Enumeration:

0x00 : GETD

Get Flash descriptor

0x01 : WP

Write page

0x02 : WPL

Write page and lock

0x03 : EWP

Erase page and write page

0x04 : EWPL

Erase page and write page then lock

0x05 : EA

Erase all

0x07 : EPA

Erase pages

0x08 : SLB

Set lock bit

0x09 : CLB

Clear lock bit

0x0A : GLB

Get lock bit

0x0B : SGPB

Set GPNVM bit

0x0C : CGPB

Clear GPNVM bit

0x0D : GGPB

Get GPNVM bit

0x0E : STUI

Start read unique identifier

0x0F : SPUI

Stop read unique identifier

0x10 : GCALB

Get CALIB bit

0x11 : ES

Erase sector

0x12 : WUS

Write user signature

0x13 : EUS

Erase user signature

0x14 : STUS

Start read user signature

0x15 : SPUS

Stop read user signature

End of enumeration elements list.

FARG : Flash Command Argument
bits : 8 - 23 (16 bit)
access : write-only

FKEY : Flash Writing Protection Key
bits : 24 - 31 (8 bit)
access : write-only

Enumeration:

0x5A : PASSWD

The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.

End of enumeration elements list.


EEFC_FSR

EEFC Flash Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EEFC_FSR EEFC_FSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRDY FCMDE FLOCKE FLERR UECCELSB MECCELSB UECCEMSB MECCEMSB

FRDY : Flash Ready Status (cleared when Flash is busy)
bits : 0 - 0 (1 bit)

FCMDE : Flash Command Error Status (cleared on read or by writing EEFC_FCR)
bits : 1 - 1 (1 bit)

FLOCKE : Flash Lock Error Status (cleared on read)
bits : 2 - 2 (1 bit)

FLERR : Flash Error Status (cleared when a programming operation starts)
bits : 3 - 3 (1 bit)

UECCELSB : Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
bits : 16 - 16 (1 bit)

MECCELSB : Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
bits : 17 - 17 (1 bit)

UECCEMSB : Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
bits : 18 - 18 (1 bit)

MECCEMSB : Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
bits : 19 - 19 (1 bit)


FSR

EEFC Flash Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

FSR FSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRDY FCMDE FLOCKE FLERR UECCELSB MECCELSB UECCEMSB MECCEMSB

FRDY : Flash Ready Status (cleared when Flash is busy)
bits : 0 - 0 (1 bit)
access : read-only

FCMDE : Flash Command Error Status (cleared on read or by writing EEFC_FCR)
bits : 1 - 1 (1 bit)
access : read-only

FLOCKE : Flash Lock Error Status (cleared on read)
bits : 2 - 2 (1 bit)
access : read-only

FLERR : Flash Error Status (cleared when a programming operation starts)
bits : 3 - 3 (1 bit)
access : read-only

UECCELSB : Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
bits : 16 - 16 (1 bit)
access : read-only

MECCELSB : Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)
bits : 17 - 17 (1 bit)
access : read-only

UECCEMSB : Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
bits : 18 - 18 (1 bit)
access : read-only

MECCEMSB : Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)
bits : 19 - 19 (1 bit)
access : read-only


EEFC_FRR

EEFC Flash Result Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EEFC_FRR EEFC_FRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FVALUE

FVALUE : Flash Result Value
bits : 0 - 31 (32 bit)


FRR

EEFC Flash Result Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

FRR FRR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FVALUE

FVALUE : Flash Result Value
bits : 0 - 31 (32 bit)
access : read-only


EEFC_WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EEFC_WPMR EEFC_WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)

Enumeration: WPKEYSelect

0x454643 : PASSWD

Writing any other value in this field aborts the write operation.Always reads as 0.

End of enumeration elements list.


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x454643 : PASSWD

Writing any other value in this field aborts the write operation.Always reads as 0.

End of enumeration elements list.



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